| /external/chromium_org/net/disk_cache/blockfile/ |
| stats.cc | 47 "Open miss",
49 "Create miss",
310 int Stats::GetRatio(Counters hit, Counters miss) const {
315 ratio /= (GetCounter(hit) + GetCounter(miss));
|
| /packages/apps/Email/src/com/android/email/provider/ |
| ContentCache.java | 107 // able to avoid a cache miss)
408 * included in baseProjection will always generate a cache miss
705 mStats.miss++;
740 // Basic cache miss (the item is not cached)
744 // A projection miss occurs when the item is cached, but not all requested columns are
754 private long miss = 0; field in class:ContentCache.Statistics
780 miss += cache.mStats.miss;
806 append(sb, "Miss time", missTimes / 1000000.0 / miss);
[all...] |
| /external/oprofile/events/x86-64/family10/ |
| unit_masks | 80 0x02 DCT0 Page miss
83 0x10 DCT1 Page miss
111 0x01 Probe miss
137 0x04 GART miss
140 0x20 DEV miss
176 0x04 Read Block (Dcache load miss refill)
178 0x10 Read Block Modified (Dcache store miss refill)
240 0x04 Cycles in non-speculative phase (including cache miss penalty)
241 0x08 Cache miss penalty in cycles
|
| /external/chromium_org/third_party/libxml/src/ |
| gentest.py | 945 for miss in missing_list:
946 lst.write("%s: %d :" % (miss[1], miss[0]))
948 for n in missing_types[miss[1]]:
|
| /external/chromium_org/v8/test/mjsunit/ |
| keyed-call-ic.js | 116 key = 'two'; // the name change should case a miss
126 key = 'two'; // the name change should case a miss
|
| array-store-and-grow.js | 33 // by the runtime in the miss stub.
|
| elements-transition.js | 53 // triggers an IC miss, upon which the conversion stub is generated, but the
|
| /external/oprofile/events/mips/sb1/ |
| events | 42 event:0x3 counters:1,2,3 um:zero minimum:500 name:DCACHE_READ_MISS :Dcache read results in a miss
46 event:0xc counters:1,2,3 um:zero minimum:500 name:DCACHE_READ_MISS :Dcache read results in a miss
|
| /external/chromium_org/v8/src/arm/ |
| code-stubs-arm.h | 366 Label* miss,
374 Label* miss,
|
| /external/oprofile/events/i386/westmere/ |
| events | 17 event:0x0c counters:0,1,2,3 um:x01 minimum:200000 name:MEM_STORE_RETIRED : Retired stores that miss the DTLB (Precise Event)
33 event:0x2e counters:0,1,2,3 um:longest_lat_cache minimum:100000 name:LONGEST_LAT_CACHE : Longest latency cache miss
46 event:0x85 counters:0,1,2,3 um:itlb_misses minimum:200000 name:ITLB_MISSES : ITLB miss
70 event:0xcb counters:0,1,2,3 um:mem_load_retired minimum:200000 name:MEM_LOAD_RETIRED : Retired loads that miss the DTLB (Precise Event)
|
| /external/linux-tools-perf/perf-3.12.0/tools/perf/util/ |
| sort.c | 586 "MISS",
601 u64 hit, miss; local
609 miss = m & PERF_MEM_TLB_MISS;
628 if (miss)
629 strncat(out, " miss", sz - l);
656 "MISS",
678 u64 hit, miss; local
686 miss = m & PERF_MEM_LVL_MISS;
705 if (miss)
706 strncat(out, " miss", sz - l)
[all...] |
| parse-events.l | 163 misses|miss { return str(yyscanner, PE_NAME_CACHE_OP_RESULT); }
202 * state we need to put the escaping char back, so we dont miss it.
|
| /external/oprofile/events/i386/atom/ |
| unit_masks | 44 0x02 misses Icache miss
98 0x02 l2_miss Retired loads that miss the L2 cache (precise event)
99 0x04 dtlb_miss Retired loads that miss the DTLB (precise event)
|
| /external/oprofile/events/x86-64/family11h/ |
| events | 68 event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB miss and L2 ITLB hit
69 event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB miss and L2 ITLB miss
|
| /external/oprofile/events/x86-64/hammer/ |
| events | 68 event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB miss and L2 ITLB hit
69 event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB miss and L2 ITLB miss
|
| /external/chromium_org/v8/src/arm64/ |
| code-stubs-arm64.h | 374 Label* miss,
382 Label* miss,
|
| /external/chromium_org/v8/src/ia32/ |
| code-stubs-ia32.h | 131 Label* miss,
138 Label* miss,
|
| macro-assembler-ia32.h | 578 Label* miss);
582 void LoadFromNumberDictionary(Label* miss,
716 // function and jumps to the miss label if the fast checks fail. The
722 Label* miss,
[all...] |
| /external/chromium_org/v8/src/mips/ |
| code-stubs-mips.h | 408 Label* miss,
416 Label* miss,
|
| /external/chromium_org/v8/src/x64/ |
| code-stubs-x64.h | 131 Label* miss,
138 Label* miss,
|
| /external/chromium_org/v8/src/x87/ |
| code-stubs-x87.h | 129 Label* miss,
136 Label* miss,
|
| /external/oprofile/events/i386/nehalem/ |
| unit_masks | 25 0x02 walk_completed Counts number of completed page walks due to load miss in the STLB
29 0x80 large_walk_completed Counts number of completed large page walks due to load miss in the STLB
82 0x02 ld_miss Counts the number of loads that miss the L2 cache
85 0x08 rfo_miss Counts the number of store RFO requests that miss the L2 cache
88 0x20 ifetch_miss Counts number of instruction fetches that miss the L2 cache
93 0xAA miss Counts all L2 misses for both code and data
128 0x41 miss This event counts each cache miss condition for references to the last level cache
166 0x02 miss Counts number of hardware prefetch requests that miss the L1
[all...] |
| /external/oprofile/events/mips/rm9000/ |
| events | 24 event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache-miss stall cycles
|
| /external/chromium_org/third_party/lcov/bin/ |
| geninfo | [all...] |
| /external/oprofile/events/mips/74K/ |
| events | 25 event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
120 event:0x41a counters:1,3 um:zero minimum:500 name:VA_TRANSALTION_CORNER_CASES : 26-1 Virtual memory address translation synonyms, homonyms, and aliases (loads/stores treated as miss in the cache)
123 event:0x41d counters:1,3 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 29-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
143 event:0x435 counters:1,3 um:zero minimum:500 name:LOAD_MISS_INSNS : 53-1 Cacheable load instructions that miss in the cache graduated
|
