| /external/llvm/include/llvm/Analysis/ |
| ScalarEvolution.h | 607 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
610 Ops.push_back(Op0);
625 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
628 Ops.push_back(Op0);
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 70 const MCOperand &Op0 = MI->getOperand(0);
103 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
139 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
149 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
157 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
164 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
174 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
184 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 248 MachineOperand &Op0 = MI->getOperand(0);
249 unsigned Reg0 = Op0.getReg();
252 // Handle instructions that have a prediate register in op0
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| DAGCombiner.cpp | 331 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const;
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 113 unsigned Op0, bool Op0IsKill,
117 unsigned Op0, bool Op0IsKill);
120 unsigned Op0, bool Op0IsKill,
653 Value *Op0 = I->getOperand(0);
662 if (!isLoadTypeLegal(Op0->getType(), VT))
666 SrcReg = getRegForValue(Op0);
[all...] |
| PPCISelDAGToDAG.cpp | 415 SDValue Op0 = N->getOperand(0);
420 CurDAG->computeKnownBits(Op0, LKZ, LKO);
427 unsigned Op0Opc = Op0.getOpcode();
436 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
437 Op0.getOperand(0).getOpcode() == ISD::SRL) {
440 std::swap(Op0, Op1);
448 std::swap(Op0, Op1);
482 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
[all...] |
| /external/llvm/lib/AsmParser/ |
| LLParser.cpp | [all...] |
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| IntrinsicLowering.cpp | 488 Value *Op0 = CI->getArgOperand(0);
489 Type *IntPtr = DL.getIntPtrType(Op0->getType());
493 Ops[0] = Op0;
|
| /external/llvm/lib/IR/ |
| AutoUpgrade.cpp | 366 Value *Op0 = CI->getArgOperand(0);
387 Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVector::get(Idxs));
|
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | 765 void InitOperands(SDUse *Ops, const SDValue &Op0) {
767 Ops[0].setInitial(Op0);
774 void InitOperands(SDUse *Ops, const SDValue &Op0, const SDValue &Op1) {
776 Ops[0].setInitial(Op0);
785 void InitOperands(SDUse *Ops, const SDValue &Op0, const SDValue &Op1,
788 Ops[0].setInitial(Op0);
799 void InitOperands(SDUse *Ops, const SDValue &Op0, const SDValue &Op1,
802 Ops[0].setInitial(Op0);
[all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | 612 /// SymbolicallyEvaluateBinop - One of Op0/Op1 is a constant expression.
616 static Constant *SymbolicallyEvaluateBinop(unsigned Opc, Constant *Op0,
626 unsigned BitWidth = DL->getTypeSizeInBits(Op0->getType()->getScalarType());
629 computeKnownBits(Op0, KnownZero0, KnownOne0, DL);
632 // All the bits of Op0 that the 'and' could be masking are already zero.
633 return Op0;
643 return ConstantInt::get(Op0->getType(), KnownOne);
653 if (IsConstantOffsetFromGlobal(Op0, GV1, Offs1, *DL))
656 unsigned OpSize = DL->getTypeSizeInBits(Op0->getType());
661 return ConstantInt::get(Op0->getType(), Offs1.zextOrTrunc(OpSize)
[all...] |
| ValueTracking.cpp | 48 static void computeKnownBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW,
53 if (ConstantInt *CLHS = dyn_cast<ConstantInt>(Op0)) {
83 llvm::computeKnownBits(Op0, LHSKnownZero, LHSKnownOne, TD, Depth+1);
131 static void computeKnownBitsMul(Value *Op0, Value *Op1, bool NSW,
137 computeKnownBits(Op0, KnownZero2, KnownOne2, TD, Depth+1);
143 if (Op0 == Op1) {
158 isKnownNonZero(Op0, TD, Depth)) ||
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86ISelLowering.h | [all...] |
| X86MCInstLower.cpp | 264 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
269 if (Op0 == X86::AX && Op1 == X86::AL)
273 if (Op0 == X86::EAX && Op1 == X86::AX)
277 if (Op0 == X86::RAX && Op1 == X86::EAX)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 417 static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp,
420 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) {
421 std::swap(Op0, Op1);
422 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx))
433 SDValue Op0 = N->getOperand(0);
442 std::swap(Op0, Op1);
451 SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };
[all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 527 static bool compareMachineOp(const MachineOperand &Op0,
529 if (Op0.getType() != Op1.getType())
532 switch (Op0.getType()) {
534 return Op0.getReg() == Op1.getReg();
536 return Op0.getImm() == Op1.getImm();
538 return Op0.getFPImm() == Op1.getFPImm();
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCasts.cpp | [all...] |
| InstCombineCalls.cpp | [all...] |
