1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 // This peephole pass optimizes in the following cases. 9 // 1. Optimizes redundant sign extends for the following case 10 // Transform the following pattern 11 // %vreg170<def> = SXTW %vreg166 12 // ... 13 // %vreg176<def> = COPY %vreg170:subreg_loreg 14 // 15 // Into 16 // %vreg176<def> = COPY vreg166 17 // 18 // 2. Optimizes redundant negation of predicates. 19 // %vreg15<def> = CMPGTrr %vreg6, %vreg2 20 // ... 21 // %vreg16<def> = NOT_p %vreg15<kill> 22 // ... 23 // JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead> 24 // 25 // Into 26 // %vreg15<def> = CMPGTrr %vreg6, %vreg2; 27 // ... 28 // JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>; 29 // 30 // Note: The peephole pass makes the instrucstions like 31 // %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill> 32 // redundant and relies on some form of dead removal instructions, like 33 // DCE or DIE to actually eliminate them. 34 35 36 //===----------------------------------------------------------------------===// 37 38 #include "Hexagon.h" 39 #include "HexagonTargetMachine.h" 40 #include "llvm/ADT/DenseMap.h" 41 #include "llvm/ADT/Statistic.h" 42 #include "llvm/CodeGen/MachineFunction.h" 43 #include "llvm/CodeGen/MachineFunctionPass.h" 44 #include "llvm/CodeGen/MachineInstrBuilder.h" 45 #include "llvm/CodeGen/MachineRegisterInfo.h" 46 #include "llvm/CodeGen/Passes.h" 47 #include "llvm/IR/Constants.h" 48 #include "llvm/PassSupport.h" 49 #include "llvm/Support/CommandLine.h" 50 #include "llvm/Support/Debug.h" 51 #include "llvm/Support/raw_ostream.h" 52 #include "llvm/Target/TargetInstrInfo.h" 53 #include "llvm/Target/TargetMachine.h" 54 #include "llvm/Target/TargetRegisterInfo.h" 55 #include <algorithm> 56 57 using namespace llvm; 58 59 #define DEBUG_TYPE "hexagon-peephole" 60 61 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole", 62 cl::Hidden, cl::ZeroOrMore, cl::init(false), 63 cl::desc("Disable Peephole Optimization")); 64 65 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp", 66 cl::Hidden, cl::ZeroOrMore, cl::init(false), 67 cl::desc("Disable Optimization of PNotP")); 68 69 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext", 70 cl::Hidden, cl::ZeroOrMore, cl::init(false), 71 cl::desc("Disable Optimization of Sign/Zero Extends")); 72 73 static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64", 74 cl::Hidden, cl::ZeroOrMore, cl::init(false), 75 cl::desc("Disable Optimization of extensions to i64.")); 76 77 namespace llvm { 78 void initializeHexagonPeepholePass(PassRegistry&); 79 } 80 81 namespace { 82 struct HexagonPeephole : public MachineFunctionPass { 83 const HexagonInstrInfo *QII; 84 const HexagonRegisterInfo *QRI; 85 const MachineRegisterInfo *MRI; 86 87 public: 88 static char ID; 89 HexagonPeephole() : MachineFunctionPass(ID) { 90 initializeHexagonPeepholePass(*PassRegistry::getPassRegistry()); 91 } 92 93 bool runOnMachineFunction(MachineFunction &MF) override; 94 95 const char *getPassName() const override { 96 return "Hexagon optimize redundant zero and size extends"; 97 } 98 99 void getAnalysisUsage(AnalysisUsage &AU) const override { 100 MachineFunctionPass::getAnalysisUsage(AU); 101 } 102 103 private: 104 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src); 105 }; 106 } 107 108 char HexagonPeephole::ID = 0; 109 110 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole", 111 false, false) 112 113 bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { 114 QII = static_cast<const HexagonInstrInfo *>(MF.getTarget(). 115 getInstrInfo()); 116 QRI = static_cast<const HexagonRegisterInfo *>(MF.getTarget(). 117 getRegisterInfo()); 118 MRI = &MF.getRegInfo(); 119 120 DenseMap<unsigned, unsigned> PeepholeMap; 121 DenseMap<unsigned, std::pair<unsigned, unsigned> > PeepholeDoubleRegsMap; 122 123 if (DisableHexagonPeephole) return false; 124 125 // Loop over all of the basic blocks. 126 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end(); 127 MBBb != MBBe; ++MBBb) { 128 MachineBasicBlock* MBB = MBBb; 129 PeepholeMap.clear(); 130 PeepholeDoubleRegsMap.clear(); 131 132 // Traverse the basic block. 133 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end(); 134 ++MII) { 135 MachineInstr *MI = MII; 136 // Look for sign extends: 137 // %vreg170<def> = SXTW %vreg166 138 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) { 139 assert (MI->getNumOperands() == 2); 140 MachineOperand &Dst = MI->getOperand(0); 141 MachineOperand &Src = MI->getOperand(1); 142 unsigned DstReg = Dst.getReg(); 143 unsigned SrcReg = Src.getReg(); 144 // Just handle virtual registers. 145 if (TargetRegisterInfo::isVirtualRegister(DstReg) && 146 TargetRegisterInfo::isVirtualRegister(SrcReg)) { 147 // Map the following: 148 // %vreg170<def> = SXTW %vreg166 149 // PeepholeMap[170] = vreg166 150 PeepholeMap[DstReg] = SrcReg; 151 } 152 } 153 154 // Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169) 155 // %vreg170:DoublRegs, %vreg169:IntRegs 156 if (!DisableOptExtTo64 && 157 MI->getOpcode () == Hexagon::COMBINE_Ir_V4) { 158 assert (MI->getNumOperands() == 3); 159 MachineOperand &Dst = MI->getOperand(0); 160 MachineOperand &Src1 = MI->getOperand(1); 161 MachineOperand &Src2 = MI->getOperand(2); 162 if (Src1.getImm() != 0) 163 continue; 164 unsigned DstReg = Dst.getReg(); 165 unsigned SrcReg = Src2.getReg(); 166 PeepholeMap[DstReg] = SrcReg; 167 } 168 169 // Look for this sequence below 170 // %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32 171 // %vregIntReg = COPY %vregDoubleReg1:subreg_loreg. 172 // and convert into 173 // %vregIntReg = COPY %vregDoubleReg0:subreg_hireg. 174 if (MI->getOpcode() == Hexagon::LSRd_ri) { 175 assert(MI->getNumOperands() == 3); 176 MachineOperand &Dst = MI->getOperand(0); 177 MachineOperand &Src1 = MI->getOperand(1); 178 MachineOperand &Src2 = MI->getOperand(2); 179 if (Src2.getImm() != 32) 180 continue; 181 unsigned DstReg = Dst.getReg(); 182 unsigned SrcReg = Src1.getReg(); 183 PeepholeDoubleRegsMap[DstReg] = 184 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/); 185 } 186 187 // Look for P=NOT(P). 188 if (!DisablePNotP && 189 (MI->getOpcode() == Hexagon::NOT_p)) { 190 assert (MI->getNumOperands() == 2); 191 MachineOperand &Dst = MI->getOperand(0); 192 MachineOperand &Src = MI->getOperand(1); 193 unsigned DstReg = Dst.getReg(); 194 unsigned SrcReg = Src.getReg(); 195 // Just handle virtual registers. 196 if (TargetRegisterInfo::isVirtualRegister(DstReg) && 197 TargetRegisterInfo::isVirtualRegister(SrcReg)) { 198 // Map the following: 199 // %vreg170<def> = NOT_xx %vreg166 200 // PeepholeMap[170] = vreg166 201 PeepholeMap[DstReg] = SrcReg; 202 } 203 } 204 205 // Look for copy: 206 // %vreg176<def> = COPY %vreg170:subreg_loreg 207 if (!DisableOptSZExt && MI->isCopy()) { 208 assert (MI->getNumOperands() == 2); 209 MachineOperand &Dst = MI->getOperand(0); 210 MachineOperand &Src = MI->getOperand(1); 211 212 // Make sure we are copying the lower 32 bits. 213 if (Src.getSubReg() != Hexagon::subreg_loreg) 214 continue; 215 216 unsigned DstReg = Dst.getReg(); 217 unsigned SrcReg = Src.getReg(); 218 if (TargetRegisterInfo::isVirtualRegister(DstReg) && 219 TargetRegisterInfo::isVirtualRegister(SrcReg)) { 220 // Try to find in the map. 221 if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) { 222 // Change the 1st operand. 223 MI->RemoveOperand(1); 224 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); 225 } else { 226 DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI = 227 PeepholeDoubleRegsMap.find(SrcReg); 228 if (DI != PeepholeDoubleRegsMap.end()) { 229 std::pair<unsigned,unsigned> PeepholeSrc = DI->second; 230 MI->RemoveOperand(1); 231 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first, 232 false /*isDef*/, 233 false /*isImp*/, 234 false /*isKill*/, 235 false /*isDead*/, 236 false /*isUndef*/, 237 false /*isEarlyClobber*/, 238 PeepholeSrc.second)); 239 } 240 } 241 } 242 } 243 244 // Look for Predicated instructions. 245 if (!DisablePNotP) { 246 bool Done = false; 247 if (QII->isPredicated(MI)) { 248 MachineOperand &Op0 = MI->getOperand(0); 249 unsigned Reg0 = Op0.getReg(); 250 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); 251 if (RC0->getID() == Hexagon::PredRegsRegClassID) { 252 // Handle instructions that have a prediate register in op0 253 // (most cases of predicable instructions). 254 if (TargetRegisterInfo::isVirtualRegister(Reg0)) { 255 // Try to find in the map. 256 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { 257 // Change the 1st operand and, flip the opcode. 258 MI->getOperand(0).setReg(PeepholeSrc); 259 int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode()); 260 MI->setDesc(QII->get(NewOp)); 261 Done = true; 262 } 263 } 264 } 265 } 266 267 if (!Done) { 268 // Handle special instructions. 269 unsigned Op = MI->getOpcode(); 270 unsigned NewOp = 0; 271 unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices. 272 273 switch (Op) { 274 case Hexagon::TFR_condset_rr: 275 case Hexagon::TFR_condset_ii: 276 case Hexagon::MUX_ii: 277 case Hexagon::MUX_rr: 278 NewOp = Op; 279 break; 280 case Hexagon::TFR_condset_ri: 281 NewOp = Hexagon::TFR_condset_ir; 282 break; 283 case Hexagon::TFR_condset_ir: 284 NewOp = Hexagon::TFR_condset_ri; 285 break; 286 case Hexagon::MUX_ri: 287 NewOp = Hexagon::MUX_ir; 288 break; 289 case Hexagon::MUX_ir: 290 NewOp = Hexagon::MUX_ri; 291 break; 292 } 293 if (NewOp) { 294 unsigned PSrc = MI->getOperand(PR).getReg(); 295 if (unsigned POrig = PeepholeMap.lookup(PSrc)) { 296 MI->getOperand(PR).setReg(POrig); 297 MI->setDesc(QII->get(NewOp)); 298 // Swap operands S1 and S2. 299 MachineOperand Op1 = MI->getOperand(S1); 300 MachineOperand Op2 = MI->getOperand(S2); 301 ChangeOpInto(MI->getOperand(S1), Op2); 302 ChangeOpInto(MI->getOperand(S2), Op1); 303 } 304 } // if (NewOp) 305 } // if (!Done) 306 307 } // if (!DisablePNotP) 308 309 } // Instruction 310 } // Basic Block 311 return true; 312 } 313 314 void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) { 315 assert (&Dst != &Src && "Cannot duplicate into itself"); 316 switch (Dst.getType()) { 317 case MachineOperand::MO_Register: 318 if (Src.isReg()) { 319 Dst.setReg(Src.getReg()); 320 } else if (Src.isImm()) { 321 Dst.ChangeToImmediate(Src.getImm()); 322 } else { 323 llvm_unreachable("Unexpected src operand type"); 324 } 325 break; 326 327 case MachineOperand::MO_Immediate: 328 if (Src.isImm()) { 329 Dst.setImm(Src.getImm()); 330 } else if (Src.isReg()) { 331 Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(), 332 Src.isKill(), Src.isDead(), Src.isUndef(), 333 Src.isDebug()); 334 } else { 335 llvm_unreachable("Unexpected src operand type"); 336 } 337 break; 338 339 default: 340 llvm_unreachable("Unexpected dst operand type"); 341 break; 342 } 343 } 344 345 FunctionPass *llvm::createHexagonPeephole() { 346 return new HexagonPeephole(); 347 } 348
