| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 118 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
122 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
125 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real),
127 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr),
132 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
157 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
161 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME));
162 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::ADD_rr),
183 BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4));
198 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME))
[all...] |
| HexagonFixupHwLoops.cpp | 163 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
171 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
175 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFRI), Scratch)
177 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
181 BuildMI(*MBB, MII, DL, TII->get(Hexagon::CONST32_Label), Scratch)
183 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::SA0)
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPURegisterInfo.cpp | 20 const TargetInstrInfo &tii)
23 TII(tii)
|
| R600RegisterInfo.h | 28 const TargetInstrInfo &TII;
30 R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
|
| R600ISelLowering.cpp | 27 TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo()))
65 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
70 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
76 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
81 TII->addFlag(NewMI, 1, MO_FLAG_ABS);
88 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
93 TII->addFlag(NewMI, 1, MO_FLAG_NEG);
101 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::COPY))
112 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
129 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV_IMM_I32)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 38 const TargetInstrInfo *TII;
44 TargetSchedModel(): STI(nullptr), TII(nullptr) {}
52 const TargetInstrInfo *tii);
58 const TargetInstrInfo *getInstrInfo() const { return TII; }
165 /// present this method falls back to TII->getInstrLatency with an empty
|
| /external/llvm/lib/Target/Mips/ |
| Mips16FrameLowering.cpp | 38 const Mips16InstrInfo &TII =
52 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
57 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
72 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
77 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
86 const Mips16InstrInfo &TII =
95 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
100 TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI);
156 const Mips16InstrInfo &TII =
159 TII.adjustStackPtr(Mips::SP, Amount, MBB, I)
[all...] |
| Mips16RegisterInfo.cpp | 68 const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo();
69 TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
70 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
142 const Mips16InstrInfo &TII =
145 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
|
| MipsSEFrameLowering.cpp | 129 const MipsSEInstrInfo &TII =
138 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
139 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
149 const MipsSEInstrInfo &TII =
158 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
160 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
172 const MipsSEInstrInfo &TII =
184 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
186 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
188 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 111 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
120 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
125 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
138 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
140 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
143 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
177 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
182 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
185 MI.setDesc(TII.get(SP::STDFri));
189 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo()
[all...] |
| SparcFrameLowering.cpp | 48 const SparcInstrInfo &TII =
52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
90 const SparcInstrInfo &TII =
118 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 152 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
177 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
189 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
192 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
317 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
333 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
444 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
510 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
553 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
563 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)
[all...] |
| X86PadShortFunction.cpp | 54 , Threshold(4), TM(nullptr), TII(nullptr) {}
83 const TargetInstrInfo *TII;
108 TII = TM->getInstrInfo();
198 CyclesToEnd += TII->getInstrLatency(TM->getInstrItineraryData(), MI);
214 BuildMI(*MBB, MBBI, DL, TII->get(X86::NOOP));
215 BuildMI(*MBB, MBBI, DL, TII->get(X86::NOOP));
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 49 const ARMBaseInstrInfo &TII =
55 !(TII.getSubtarget().isLikeA9() &&
65 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
66 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
67 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
|
| ARMFrameLowering.cpp | 93 const ARMBaseInstrInfo &TII,
116 const ARMBaseInstrInfo &TII, unsigned DestReg,
123 Pred, PredReg, TII, MIFlags);
126 Pred, PredReg, TII, MIFlags);
131 const ARMBaseInstrInfo &TII, int NumBytes,
135 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
168 const ARMBaseInstrInfo &TII =
194 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
199 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
206 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize)
[all...] |
| Thumb1RegisterInfo.cpp | 70 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
76 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
93 const TargetInstrInfo &TII,
115 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
118 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
120 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
169 int NumBytes, const TargetInstrInfo &TII,
229 TII, MRI, MIFlags);
239 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCBranchSelector.cpp | 66 const PPCInstrInfo *TII =
81 BlockSize += TII->GetInstSizeInBytes(MBBI);
128 MBBStartOffset += TII->GetInstSizeInBytes(I);
171 BuildMI(MBB, I, dl, TII->get(PPC::BCC))
175 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2);
178 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2);
180 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
182 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
184 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
186 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 63 const TargetInstrInfo &TII,
67 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
73 const TargetInstrInfo &TII,
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
83 const TargetInstrInfo &TII, MachineModuleInfo *MMI,
87 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
99 const TargetInstrInfo &TII, MachineModuleInfo *MMI,
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
123 const TargetInstrInfo &TII, int OffsetFromTop
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZLongBranch.cpp | 135 : MachineFunctionPass(ID), TII(nullptr) {}
157 const SystemZInstrInfo *TII;
212 Terminator.Size = TII->getInstSizeInBytes(MI);
253 TII->getBranchInfo(MI).Target->getMBB()->getNumber();
283 Block.Size += TII->getInstSizeInBytes(MI);
351 BuildMI(*MBB, MI, DL, TII->get(AddOpcode))
355 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
360 BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo());
370 BuildMI(*MBB, MI, DL, TII->get(CompareOpcode))
373 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL)
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 56 const TargetInstrInfo *tii) {
59 TII = tii;
81 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
160 return TII->defaultDefLatency(&SchedModel, DefMI);
165 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx,
176 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
179 // Rather than directly querying InstrItins stage latency, we call a TII
182 // special cases without TII hooks.
184 TII->defaultDefLatency(&SchedModel, DefMI))
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 27 TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo()))
65 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
70 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
76 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
81 TII->addFlag(NewMI, 1, MO_FLAG_ABS);
88 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
93 TII->addFlag(NewMI, 1, MO_FLAG_NEG);
101 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::COPY))
112 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
129 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV_IMM_I32)
[all...] |
| AMDGPURegisterInfo.h | 33 const TargetInstrInfo &TII;
36 AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
|
| SIRegisterInfo.cpp | 21 const TargetInstrInfo &tii)
22 : AMDGPURegisterInfo(tm, tii),
24 TII(tii)
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430BranchSelector.cpp | 56 const MSP430InstrInfo *TII =
71 BlockSize += TII->GetInstSizeInBytes(MBBI);
108 MBBStartOffset += TII->GetInstSizeInBytes(I);
155 TII->ReverseBranchCondition(Cond);
156 BuildMI(MBB, I, dl, TII->get(MSP430::JCC))
162 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
|
| /external/llvm/lib/Target/R600/ |
| SILowerI1Copies.cpp | 73 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
89 MI.setDesc(TII->get(AMDGPU::V_MOV_B32_e32));
95 MI.setDesc(TII->get(AMDGPU::V_AND_B32_e32));
101 MI.setDesc(TII->get(AMDGPU::V_OR_B32_e32));
119 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CNDMASK_B32_e64))
131 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CMP_NE_I32_e64))
|
