1 //===-- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "Thumb1RegisterInfo.h" 16 #include "ARMBaseInstrInfo.h" 17 #include "ARMMachineFunctionInfo.h" 18 #include "ARMSubtarget.h" 19 #include "MCTargetDesc/ARMAddressingModes.h" 20 #include "llvm/CodeGen/MachineConstantPool.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/RegisterScavenging.h" 26 #include "llvm/IR/Constants.h" 27 #include "llvm/IR/DerivedTypes.h" 28 #include "llvm/IR/Function.h" 29 #include "llvm/IR/LLVMContext.h" 30 #include "llvm/Support/CommandLine.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Target/TargetFrameLowering.h" 33 #include "llvm/Target/TargetMachine.h" 34 35 namespace llvm { 36 extern cl::opt<bool> ReuseFrameIndexVals; 37 } 38 39 using namespace llvm; 40 41 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMSubtarget &sti) 42 : ARMBaseRegisterInfo(sti) { 43 } 44 45 const TargetRegisterClass* 46 Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 47 const { 48 if (ARM::tGPRRegClass.hasSubClassEq(RC)) 49 return &ARM::tGPRRegClass; 50 return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC); 51 } 52 53 const TargetRegisterClass * 54 Thumb1RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 55 const { 56 return &ARM::tGPRRegClass; 57 } 58 59 /// emitLoadConstPool - Emits a load from constpool to materialize the 60 /// specified immediate. 61 void 62 Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, 63 MachineBasicBlock::iterator &MBBI, 64 DebugLoc dl, 65 unsigned DestReg, unsigned SubIdx, 66 int Val, 67 ARMCC::CondCodes Pred, unsigned PredReg, 68 unsigned MIFlags) const { 69 MachineFunction &MF = *MBB.getParent(); 70 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 71 MachineConstantPool *ConstantPool = MF.getConstantPool(); 72 const Constant *C = ConstantInt::get( 73 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val); 74 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 75 76 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci)) 77 .addReg(DestReg, getDefRegState(true), SubIdx) 78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) 79 .setMIFlags(MIFlags); 80 } 81 82 83 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 84 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate 85 /// in a register using mov / mvn sequences or load the immediate from a 86 /// constpool entry. 87 static 88 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 89 MachineBasicBlock::iterator &MBBI, 90 DebugLoc dl, 91 unsigned DestReg, unsigned BaseReg, 92 int NumBytes, bool CanChangeCC, 93 const TargetInstrInfo &TII, 94 const ARMBaseRegisterInfo& MRI, 95 unsigned MIFlags = MachineInstr::NoFlags) { 96 MachineFunction &MF = *MBB.getParent(); 97 bool isHigh = !isARMLowRegister(DestReg) || 98 (BaseReg != 0 && !isARMLowRegister(BaseReg)); 99 bool isSub = false; 100 // Subtract doesn't have high register version. Load the negative value 101 // if either base or dest register is a high register. Also, if do not 102 // issue sub as part of the sequence if condition register is to be 103 // preserved. 104 if (NumBytes < 0 && !isHigh && CanChangeCC) { 105 isSub = true; 106 NumBytes = -NumBytes; 107 } 108 unsigned LdReg = DestReg; 109 if (DestReg == ARM::SP) { 110 assert(BaseReg == ARM::SP && "Unexpected!"); 111 LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass); 112 } 113 114 if (NumBytes <= 255 && NumBytes >= 0) 115 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) 116 .addImm(NumBytes).setMIFlags(MIFlags); 117 else if (NumBytes < 0 && NumBytes >= -255) { 118 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) 119 .addImm(NumBytes).setMIFlags(MIFlags); 120 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)) 121 .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags); 122 } else 123 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes, 124 ARMCC::AL, 0, MIFlags); 125 126 // Emit add / sub. 127 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 128 MachineInstrBuilder MIB = 129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); 130 if (Opc != ARM::tADDhirr) 131 MIB = AddDefaultT1CC(MIB); 132 if (DestReg == ARM::SP || isSub) 133 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); 134 else 135 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); 136 AddDefaultPred(MIB); 137 } 138 139 /// calcNumMI - Returns the number of instructions required to materialize 140 /// the specific add / sub r, c instruction. 141 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 142 unsigned NumBits, unsigned Scale) { 143 unsigned NumMIs = 0; 144 unsigned Chunk = ((1 << NumBits) - 1) * Scale; 145 146 if (Opc == ARM::tADDrSPi) { 147 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 148 Bytes -= ThisVal; 149 NumMIs++; 150 NumBits = 8; 151 Scale = 1; // Followed by a number of tADDi8. 152 Chunk = ((1 << NumBits) - 1) * Scale; 153 } 154 155 NumMIs += Bytes / Chunk; 156 if ((Bytes % Chunk) != 0) 157 NumMIs++; 158 if (ExtraOpc) 159 NumMIs++; 160 return NumMIs; 161 } 162 163 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 164 /// a destreg = basereg + immediate in Thumb code. 165 void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 166 MachineBasicBlock::iterator &MBBI, 167 DebugLoc dl, 168 unsigned DestReg, unsigned BaseReg, 169 int NumBytes, const TargetInstrInfo &TII, 170 const ARMBaseRegisterInfo& MRI, 171 unsigned MIFlags) { 172 bool isSub = NumBytes < 0; 173 unsigned Bytes = (unsigned)NumBytes; 174 if (isSub) Bytes = -NumBytes; 175 bool isMul4 = (Bytes & 3) == 0; 176 bool isTwoAddr = false; 177 bool DstNotEqBase = false; 178 unsigned NumBits = 1; 179 unsigned Scale = 1; 180 int Opc = 0; 181 int ExtraOpc = 0; 182 bool NeedCC = false; 183 184 if (DestReg == BaseReg && BaseReg == ARM::SP) { 185 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 186 NumBits = 7; 187 Scale = 4; 188 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 189 isTwoAddr = true; 190 } else if (!isSub && BaseReg == ARM::SP) { 191 // r1 = add sp, 403 192 // => 193 // r1 = add sp, 100 * 4 194 // r1 = add r1, 3 195 if (!isMul4) { 196 Bytes &= ~3; 197 ExtraOpc = ARM::tADDi3; 198 } 199 NumBits = 8; 200 Scale = 4; 201 Opc = ARM::tADDrSPi; 202 } else { 203 // sp = sub sp, c 204 // r1 = sub sp, c 205 // r8 = sub sp, c 206 if (DestReg != BaseReg) 207 DstNotEqBase = true; 208 NumBits = 8; 209 if (DestReg == ARM::SP) { 210 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 211 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 212 NumBits = 7; 213 Scale = 4; 214 } else { 215 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 216 NumBits = 8; 217 NeedCC = true; 218 } 219 isTwoAddr = true; 220 } 221 222 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 223 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 224 if (NumMIs > Threshold) { 225 // This will expand into too many instructions. Load the immediate from a 226 // constpool entry. 227 emitThumbRegPlusImmInReg(MBB, MBBI, dl, 228 DestReg, BaseReg, NumBytes, true, 229 TII, MRI, MIFlags); 230 return; 231 } 232 233 if (DstNotEqBase) { 234 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) { 235 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 236 unsigned Chunk = (1 << 3) - 1; 237 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 238 Bytes -= ThisVal; 239 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); 240 const MachineInstrBuilder MIB = 241 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg) 242 .setMIFlags(MIFlags)); 243 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); 244 } else { 245 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) 246 .addReg(BaseReg, RegState::Kill)) 247 .setMIFlags(MIFlags); 248 } 249 BaseReg = DestReg; 250 } 251 252 unsigned Chunk = ((1 << NumBits) - 1) * Scale; 253 while (Bytes) { 254 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 255 Bytes -= ThisVal; 256 ThisVal /= Scale; 257 // Build the new tADD / tSUB. 258 if (isTwoAddr) { 259 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); 260 if (NeedCC) 261 MIB = AddDefaultT1CC(MIB); 262 MIB.addReg(DestReg).addImm(ThisVal); 263 MIB = AddDefaultPred(MIB); 264 MIB.setMIFlags(MIFlags); 265 } else { 266 bool isKill = BaseReg != ARM::SP; 267 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); 268 if (NeedCC) 269 MIB = AddDefaultT1CC(MIB); 270 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal); 271 MIB = AddDefaultPred(MIB); 272 MIB.setMIFlags(MIFlags); 273 274 BaseReg = DestReg; 275 if (Opc == ARM::tADDrSPi) { 276 // r4 = add sp, imm 277 // r4 = add r4, imm 278 // ... 279 NumBits = 8; 280 Scale = 1; 281 Chunk = ((1 << NumBits) - 1) * Scale; 282 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 283 NeedCC = isTwoAddr = true; 284 } 285 } 286 } 287 288 if (ExtraOpc) { 289 const MCInstrDesc &MCID = TII.get(ExtraOpc); 290 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)) 291 .addReg(DestReg, RegState::Kill) 292 .addImm(((unsigned)NumBytes) & 3) 293 .setMIFlags(MIFlags)); 294 } 295 } 296 297 /// emitThumbConstant - Emit a series of instructions to materialize a 298 /// constant. 299 static void emitThumbConstant(MachineBasicBlock &MBB, 300 MachineBasicBlock::iterator &MBBI, 301 unsigned DestReg, int Imm, 302 const TargetInstrInfo &TII, 303 const Thumb1RegisterInfo& MRI, 304 DebugLoc dl) { 305 bool isSub = Imm < 0; 306 if (isSub) Imm = -Imm; 307 308 int Chunk = (1 << 8) - 1; 309 int ThisVal = (Imm > Chunk) ? Chunk : Imm; 310 Imm -= ThisVal; 311 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), 312 DestReg)) 313 .addImm(ThisVal)); 314 if (Imm > 0) 315 emitThumbRegPlusImmediate(MBB, MBBI, dl, DestReg, DestReg, Imm, TII, MRI); 316 if (isSub) { 317 const MCInstrDesc &MCID = TII.get(ARM::tRSB); 318 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)) 319 .addReg(DestReg, RegState::Kill)); 320 } 321 } 322 323 static void removeOperands(MachineInstr &MI, unsigned i) { 324 unsigned Op = i; 325 for (unsigned e = MI.getNumOperands(); i != e; ++i) 326 MI.RemoveOperand(Op); 327 } 328 329 /// convertToNonSPOpcode - Change the opcode to the non-SP version, because 330 /// we're replacing the frame index with a non-SP register. 331 static unsigned convertToNonSPOpcode(unsigned Opcode) { 332 switch (Opcode) { 333 case ARM::tLDRspi: 334 return ARM::tLDRi; 335 336 case ARM::tSTRspi: 337 return ARM::tSTRi; 338 } 339 340 return Opcode; 341 } 342 343 bool Thumb1RegisterInfo:: 344 rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, 345 unsigned FrameReg, int &Offset, 346 const ARMBaseInstrInfo &TII) const { 347 MachineInstr &MI = *II; 348 MachineBasicBlock &MBB = *MI.getParent(); 349 DebugLoc dl = MI.getDebugLoc(); 350 MachineInstrBuilder MIB(*MBB.getParent(), &MI); 351 unsigned Opcode = MI.getOpcode(); 352 const MCInstrDesc &Desc = MI.getDesc(); 353 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 354 355 if (Opcode == ARM::tADDrSPi) { 356 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 357 358 // Can't use tADDrSPi if it's based off the frame pointer. 359 unsigned NumBits = 0; 360 unsigned Scale = 1; 361 if (FrameReg != ARM::SP) { 362 Opcode = ARM::tADDi3; 363 NumBits = 3; 364 } else { 365 NumBits = 8; 366 Scale = 4; 367 assert((Offset & 3) == 0 && 368 "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 369 } 370 371 unsigned PredReg; 372 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { 373 // Turn it into a move. 374 MI.setDesc(TII.get(ARM::tMOVr)); 375 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 376 // Remove offset 377 MI.RemoveOperand(FrameRegIdx+1); 378 return true; 379 } 380 381 // Common case: small offset, fits into instruction. 382 unsigned Mask = (1 << NumBits) - 1; 383 if (((Offset / Scale) & ~Mask) == 0) { 384 // Replace the FrameIndex with sp / fp 385 if (Opcode == ARM::tADDi3) { 386 MI.setDesc(TII.get(Opcode)); 387 removeOperands(MI, FrameRegIdx); 388 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg) 389 .addImm(Offset / Scale)); 390 } else { 391 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 392 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset / Scale); 393 } 394 return true; 395 } 396 397 unsigned DestReg = MI.getOperand(0).getReg(); 398 unsigned Bytes = (Offset > 0) ? Offset : -Offset; 399 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale); 400 // MI would expand into a large number of instructions. Don't try to 401 // simplify the immediate. 402 if (NumMIs > 2) { 403 emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII, 404 *this); 405 MBB.erase(II); 406 return true; 407 } 408 409 if (Offset > 0) { 410 // Translate r0 = add sp, imm to 411 // r0 = add sp, 255*4 412 // r0 = add r0, (imm - 255*4) 413 if (Opcode == ARM::tADDi3) { 414 MI.setDesc(TII.get(Opcode)); 415 removeOperands(MI, FrameRegIdx); 416 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask)); 417 } else { 418 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 419 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask); 420 } 421 Offset = (Offset - Mask * Scale); 422 MachineBasicBlock::iterator NII = std::next(II); 423 emitThumbRegPlusImmediate(MBB, NII, dl, DestReg, DestReg, Offset, TII, 424 *this); 425 } else { 426 // Translate r0 = add sp, -imm to 427 // r0 = -imm (this is then translated into a series of instructions) 428 // r0 = add r0, sp 429 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl); 430 431 MI.setDesc(TII.get(ARM::tADDhirr)); 432 MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false, false, true); 433 MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false); 434 } 435 return true; 436 } else { 437 if (AddrMode != ARMII::AddrModeT1_s) 438 llvm_unreachable("Unsupported addressing mode!"); 439 440 unsigned ImmIdx = FrameRegIdx + 1; 441 int InstrOffs = MI.getOperand(ImmIdx).getImm(); 442 unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5; 443 unsigned Scale = 4; 444 445 Offset += InstrOffs * Scale; 446 assert((Offset & (Scale - 1)) == 0 && "Can't encode this offset!"); 447 448 // Common case: small offset, fits into instruction. 449 MachineOperand &ImmOp = MI.getOperand(ImmIdx); 450 int ImmedOffset = Offset / Scale; 451 unsigned Mask = (1 << NumBits) - 1; 452 453 if ((unsigned)Offset <= Mask * Scale) { 454 // Replace the FrameIndex with the frame register (e.g., sp). 455 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 456 ImmOp.ChangeToImmediate(ImmedOffset); 457 458 // If we're using a register where sp was stored, convert the instruction 459 // to the non-SP version. 460 unsigned NewOpc = convertToNonSPOpcode(Opcode); 461 if (NewOpc != Opcode && FrameReg != ARM::SP) 462 MI.setDesc(TII.get(NewOpc)); 463 464 return true; 465 } 466 467 NumBits = 5; 468 Mask = (1 << NumBits) - 1; 469 470 // If this is a thumb spill / restore, we will be using a constpool load to 471 // materialize the offset. 472 if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) { 473 ImmOp.ChangeToImmediate(0); 474 } else { 475 // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 476 ImmedOffset = ImmedOffset & Mask; 477 ImmOp.ChangeToImmediate(ImmedOffset); 478 Offset &= ~(Mask * Scale); 479 } 480 } 481 482 return Offset == 0; 483 } 484 485 void Thumb1RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 486 int64_t Offset) const { 487 const ARMBaseInstrInfo &TII = 488 *static_cast<const ARMBaseInstrInfo*>( 489 MI.getParent()->getParent()->getTarget().getInstrInfo()); 490 int Off = Offset; // ARM doesn't need the general 64-bit offsets 491 unsigned i = 0; 492 493 while (!MI.getOperand(i).isFI()) { 494 ++i; 495 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 496 } 497 bool Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII); 498 assert (Done && "Unable to resolve frame index!"); 499 (void)Done; 500 } 501 502 /// saveScavengerRegister - Spill the register so it can be used by the 503 /// register scavenger. Return true. 504 bool 505 Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB, 506 MachineBasicBlock::iterator I, 507 MachineBasicBlock::iterator &UseMI, 508 const TargetRegisterClass *RC, 509 unsigned Reg) const { 510 // Thumb1 can't use the emergency spill slot on the stack because 511 // ldr/str immediate offsets must be positive, and if we're referencing 512 // off the frame pointer (if, for example, there are alloca() calls in 513 // the function, the offset will be negative. Use R12 instead since that's 514 // a call clobbered register that we know won't be used in Thumb1 mode. 515 const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo(); 516 DebugLoc DL; 517 AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr)) 518 .addReg(ARM::R12, RegState::Define) 519 .addReg(Reg, RegState::Kill)); 520 521 // The UseMI is where we would like to restore the register. If there's 522 // interference with R12 before then, however, we'll need to restore it 523 // before that instead and adjust the UseMI. 524 bool done = false; 525 for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) { 526 if (II->isDebugValue()) 527 continue; 528 // If this instruction affects R12, adjust our restore point. 529 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) { 530 const MachineOperand &MO = II->getOperand(i); 531 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) { 532 UseMI = II; 533 done = true; 534 break; 535 } 536 if (!MO.isReg() || MO.isUndef() || !MO.getReg() || 537 TargetRegisterInfo::isVirtualRegister(MO.getReg())) 538 continue; 539 if (MO.getReg() == ARM::R12) { 540 UseMI = II; 541 done = true; 542 break; 543 } 544 } 545 } 546 // Restore the register from R12 547 AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)). 548 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill)); 549 550 return true; 551 } 552 553 void 554 Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 555 int SPAdj, unsigned FIOperandNum, 556 RegScavenger *RS) const { 557 unsigned VReg = 0; 558 MachineInstr &MI = *II; 559 MachineBasicBlock &MBB = *MI.getParent(); 560 MachineFunction &MF = *MBB.getParent(); 561 const ARMBaseInstrInfo &TII = 562 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 563 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 564 DebugLoc dl = MI.getDebugLoc(); 565 MachineInstrBuilder MIB(*MBB.getParent(), &MI); 566 567 unsigned FrameReg = ARM::SP; 568 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 569 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 570 MF.getFrameInfo()->getStackSize() + SPAdj; 571 572 if (MF.getFrameInfo()->hasVarSizedObjects()) { 573 assert(SPAdj == 0 && MF.getTarget().getFrameLowering()->hasFP(MF) && 574 "Unexpected"); 575 // There are alloca()'s in this function, must reference off the frame 576 // pointer or base pointer instead. 577 if (!hasBasePointer(MF)) { 578 FrameReg = getFrameRegister(MF); 579 Offset -= AFI->getFramePtrSpillOffset(); 580 } else 581 FrameReg = BasePtr; 582 } 583 584 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 585 // call frame setup/destroy instructions have already been eliminated. That 586 // means the stack pointer cannot be used to access the emergency spill slot 587 // when !hasReservedCallFrame(). 588 #ifndef NDEBUG 589 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 590 assert(MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF) && 591 "Cannot use SP to access the emergency spill slot in " 592 "functions without a reserved call frame"); 593 assert(!MF.getFrameInfo()->hasVarSizedObjects() && 594 "Cannot use SP to access the emergency spill slot in " 595 "functions with variable sized frame objects"); 596 } 597 #endif // NDEBUG 598 599 // Special handling of dbg_value instructions. 600 if (MI.isDebugValue()) { 601 MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/); 602 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset); 603 return; 604 } 605 606 // Modify MI as necessary to handle as much of 'Offset' as possible 607 assert(AFI->isThumbFunction() && 608 "This eliminateFrameIndex only supports Thumb1!"); 609 if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII)) 610 return; 611 612 // If we get here, the immediate doesn't fit into the instruction. We folded 613 // as much as possible above, handle the rest, providing a register that is 614 // SP+LargeImm. 615 assert(Offset && "This code isn't needed if offset already handled!"); 616 617 unsigned Opcode = MI.getOpcode(); 618 619 // Remove predicate first. 620 int PIdx = MI.findFirstPredOperandIdx(); 621 if (PIdx != -1) 622 removeOperands(MI, PIdx); 623 624 if (MI.mayLoad()) { 625 // Use the destination register to materialize sp + offset. 626 unsigned TmpReg = MI.getOperand(0).getReg(); 627 bool UseRR = false; 628 if (Opcode == ARM::tLDRspi) { 629 if (FrameReg == ARM::SP) 630 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, 631 Offset, false, TII, *this); 632 else { 633 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); 634 UseRR = true; 635 } 636 } else { 637 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, 638 *this); 639 } 640 641 MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi)); 642 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); 643 if (UseRR) 644 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame 645 // register. The offset is already handled in the vreg value. 646 MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false, 647 false); 648 } else if (MI.mayStore()) { 649 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass); 650 bool UseRR = false; 651 652 if (Opcode == ARM::tSTRspi) { 653 if (FrameReg == ARM::SP) 654 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg, 655 Offset, false, TII, *this); 656 else { 657 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset); 658 UseRR = true; 659 } 660 } else 661 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII, 662 *this); 663 MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi)); 664 MI.getOperand(FIOperandNum).ChangeToRegister(VReg, false, false, true); 665 if (UseRR) 666 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame 667 // register. The offset is already handled in the vreg value. 668 MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false, 669 false); 670 } else { 671 llvm_unreachable("Unexpected opcode!"); 672 } 673 674 // Add predicate back if it's needed. 675 if (MI.isPredicable()) 676 AddDefaultPred(MIB); 677 } 678
