| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | [all...] |
| InstrEmitter.h | 88 MVT VT, DebugLoc DL);
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| ScheduleDAGRRList.cpp | 282 MVT VT = RegDefPos.GetValue();
286 if (VT == MVT::Untyped) {
315 RegClass = TLI->getRepRegClassFor(VT)->getID();
316 Cost = TLI->getRepRegClassCostFor(VT);
[all...] |
| LegalizeFloatTypes.cpp | 30 static RTLIB::Libcall GetFPLibCall(EVT VT,
37 VT == MVT::f32 ? Call_F32 :
38 VT == MVT::f64 ? Call_F64 :
39 VT == MVT::f80 ? Call_F80 :
40 VT == MVT::f128 ? Call_F128 :
41 VT == MVT::ppcf128 ? Call_PPCF128 :
513 EVT VT = N->getValueType(0);
514 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
540 return BitConvertToInteger(DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL));
566 EVT VT = N->getValueType(0)
[all...] |
| InstrEmitter.cpp | 104 MVT VT = Node->getSimpleValueType(ResNo);
107 if (TLI->isTypeLegal(VT))
108 UseRC = TLI->getRegClassFor(VT);
127 MVT VT = Node->getSimpleValueType(Op.getResNo());
128 if (VT == MVT::Other || VT == MVT::Glue)
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
163 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
166 DstRC = TLI->getRegClassFor(VT);
437 MVT VT, DebugLoc DL)
[all...] |
| ScheduleDAGFast.cpp | 224 EVT VT = N->getValueType(i);
225 if (VT == MVT::Glue)
227 else if (VT == MVT::Other)
232 EVT VT = Op.getNode()->getValueType(Op.getResNo());
233 if (VT == MVT::Glue)
575 EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
577 TRI->getMinimalPhysRegClass(Reg, VT);
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| FunctionLoweringInfo.cpp | 209 EVT VT = ValueVTs[vti];
210 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
247 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
249 createVirtualRegister(TM.getTargetLowering()->getRegClassFor(VT));
314 "PHIs with non-vector integer types should have a single VT.");
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| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 356 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
398 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
432 MVT VT) const override;
493 bool allowsUnalignedMemoryAccesses(EVT VT,
501 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
505 shouldExpandBuildVectorWithShuffles(EVT VT,
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| PPCISelDAGToDAG.cpp | 584 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
832 MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy;
833 unsigned int VCmpInst = getVCmpInst(VT, CC, PPCSubTarget->hasVSX());
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 142 unsigned CreateReg(MVT VT);
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.h | 105 void AnalyzeCallResult(EVT VT, Hexagon_CCAssignFn Fn);
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| HexagonISelLowering.cpp | 615 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
622 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
659 EVT VT;
664 VT = LD->getMemoryVT();
667 VT = ST->getMemoryVT();
676 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
679 int ShiftAmount = VT.getSizeInBits() / 16
[all...] |
| HexagonInstrInfo.h | 117 unsigned createVR(MachineFunction* MF, MVT VT) const;
159 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
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| HexagonInstrInfo.cpp | 566 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
570 if (VT == MVT::i1) {
572 } else if (VT == MVT::i32 || VT == MVT::f32) {
574 } else if (VT == MVT::i64 || VT == MVT::f64) {
[all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.cpp | 228 OS.indent(indent) << "EmitInteger " << Val << " VT=" << VT << '\n';
233 OS.indent(indent) << "EmitStringInteger " << Val << " VT=" << VT << '\n';
242 OS << " VT=" << VT << '\n';
311 return HashString(Val) ^ VT;
|
| IntrinsicEmitter.cpp | 262 static void EncodeFixedValueType(MVT::SimpleValueType VT,
264 if (MVT(VT).isInteger()) {
265 unsigned BitWidth = MVT(VT).getSizeInBits();
276 switch (VT) {
311 MVT::SimpleValueType VT = getValueType(R->getValueAsDef("VT"));
314 switch (VT) {
348 if (MVT(VT).isVector()) {
349 MVT VVT = VT;
363 EncodeFixedValueType(VT, Sig)
[all...] |
| CallingConvEmitter.cpp | 88 Record *VT = VTs->getElementAsRecord(i);
90 O << "LocVT == " << getEnumName(getValueType(VT));
|
| CodeGenDAGPatterns.cpp | 34 static inline bool isInteger(MVT::SimpleValueType VT) {
35 return MVT(VT).isInteger();
37 static inline bool isFloatingPoint(MVT::SimpleValueType VT) {
38 return MVT(VT).isFloatingPoint();
40 static inline bool isVector(MVT::SimpleValueType VT) {
41 return MVT(VT).isVector();
43 static inline bool isScalar(MVT::SimpleValueType VT) {
44 return !MVT(VT).isVector();
47 EEVT::TypeSet::TypeSet(MVT::SimpleValueType VT, TreePattern &TP) {
48 if (VT == MVT::iAny
[all...] |
| CodeGenDAGPatterns.h | 61 TypeSet(MVT::SimpleValueType VT, TreePattern &TP);
131 /// EnforceSmallerThan - 'this' must be a smaller VT than Other. Update
136 /// whose element is VT.
137 bool EnforceVectorEltTypeIs(EEVT::TypeSet &VT, TreePattern &TP);
140 /// be a vector type VT.
141 bool EnforceVectorSubVectorTypeIs(EEVT::TypeSet &VT, TreePattern &TP);
173 MVT::SimpleValueType VT;
463 /// UpdateNodeType - Set the node type of N to VT if VT contains
|
| /external/clang/include/clang/Analysis/Analyses/ |
| ThreadSafetyTraverse.h | 612 ValueType VT = E->valueType();
613 switch (VT.Base) {
626 switch (VT.Size) {
628 if (VT.Signed)
634 if (VT.Signed)
640 if (VT.Signed)
646 if (VT.Signed)
657 switch (VT.Size) {
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelDAGToDAG.cpp | 236 EVT VT = N->getValueType(0);
237 unsigned NumVectorElts = VT.getVectorNumElements();
238 EVT EltVT = VT.getVectorElementType();
706 EVT VT = N->getValueType(0);
708 assert(VT == MVT::f32 || VT == MVT::f64);
711 = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
725 return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
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| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 246 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
420 /// Otherwise, it just returns VT.
421 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
563 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
567 MVT VT) const override;
591 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 100 MVT VT) const override;
|
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/curses/ |
| ascii.py | 16 VT = 0x0b # ^K
42 "BS", "HT", "LF", "VT", "FF", "CR", "SO", "SI",
|
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/curses/ |
| ascii.py | 16 VT = 0x0b # ^K
42 "BS", "HT", "LF", "VT", "FF", "CR", "SO", "SI",
|
