| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32;
67 Loads[i] = DAG.getLoad(VT, dl, Chain,
101 VT = MVT::i16;
104 VT = MVT::i8;
108 Loads[i] = DAG.getLoad(VT, dl, Chain,
125 VT = MVT::i16;
128 VT = MVT::i8;
|
| ARMISelLowering.h | 255 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
267 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
272 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
290 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
336 MVT VT) const override;
352 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
372 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
378 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
403 findRepresentativeClass(MVT VT) const override;
418 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.h | 70 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
71 static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
79 unsigned Reg, EVT VT) const;
107 bool isFAbsFree(EVT VT) const override;
108 bool isFNegFree(EVT VT) const override;
121 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
122 bool ShouldShrinkFPConstant(EVT VT) const override;
|
| R600RegisterInfo.cpp | 66 MVT VT) const {
67 switch(VT.SimpleTy) {
|
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 726 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
730 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
731 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
736 (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand);
746 if (VT >= MVT::FIRST_VECTOR_VALUETYPE &
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.h | 33 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0,
45 EVT VT) const override {
49 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 154 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
156 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
272 // Return an undefined value of type VT.
273 SDValue getUNDEF(SDLoc DL, EVT VT) const;
275 // Convert N to VT, if it isn't already.
276 SDValue convertTo(SDLoc DL, EVT VT, SDValue N) const;
576 EVT VT, SDValue &Base,
581 Base = CurDAG->getRegister(0, VT);
585 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT);
586 } else if (Base.getValueType() != VT) {
[all...] |
| SystemZISelLowering.cpp | 63 // Classify VT as either 32 or 64 bit.
64 static bool is32Bit(EVT VT) {
65 switch (VT.getSimpleVT().SimpleTy) {
122 MVT VT = MVT::SimpleValueType(I);
123 if (isTypeLegal(VT)) {
125 setOperationAction(ISD::SETCC, VT, Custom);
128 setOperationAction(ISD::SELECT, VT, Expand);
131 setOperationAction(ISD::SELECT_CC, VT, Custom);
132 setOperationAction(ISD::BR_CC, VT, Custom);
147 MVT VT = MVT::SimpleValueType(I)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.h | 38 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
|
| SIISelLowering.cpp | 252 EVT SITargetLowering::getSetCCResultType(EVT VT) const
272 EVT VT = Op.getValueType();
276 AMDGPU::VGPR0, VT);
334 EVT VT = Op.getValueType();
351 unsigned TypeDwordWidth = VT.getSizeInBits() / 32;
370 VT));
381 EVT VT = Op.getValueType();
385 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
396 EVT VT = N->getValueType(0);
408 && VT == MVT::i1)
[all...] |
| AMDGPUISelLowering.h | 36 unsigned Reg, EVT VT) const;
77 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
80 bool ShouldShrinkFPConstant(EVT VT) const;
|
| R600RegisterInfo.cpp | 108 MVT VT) const
110 switch(VT.SimpleTy) {
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.h | 38 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
|
| SIISelLowering.cpp | 252 EVT SITargetLowering::getSetCCResultType(EVT VT) const
272 EVT VT = Op.getValueType();
276 AMDGPU::VGPR0, VT);
334 EVT VT = Op.getValueType();
351 unsigned TypeDwordWidth = VT.getSizeInBits() / 32;
370 VT));
381 EVT VT = Op.getValueType();
385 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
396 EVT VT = N->getValueType(0);
408 && VT == MVT::i1)
[all...] |
| AMDGPUISelLowering.h | 36 unsigned Reg, EVT VT) const;
77 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
80 bool ShouldShrinkFPConstant(EVT VT) const;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 217 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
254 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
258 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
261 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
308 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
328 getPreferredVectorAction(EVT VT) const override;
335 void addTypeForNEON(EVT VT, EVT PromotedBitwiseVT);
336 void addDRTypeForNEON(MVT VT);
337 void addQRTypeForNEON(MVT VT);
429 unsigned getRegisterByName(const char* RegName, EVT VT) const override
[all...] |
| AArch64FastISel.cpp | 113 bool isTypeLegal(Type *Ty, MVT &VT);
114 bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
116 bool SimplifyAddress(Address &Addr, MVT VT, int64_t ScaleFactor,
125 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
127 bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
132 unsigned AArch64MaterializeFP(const ConstantFP *CFP, MVT VT);
198 unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
199 if (VT != MVT::f32 && VT != MVT::f64)
203 bool is64bit = (VT == MVT::f64)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 81 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
83 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, MachineMemOperand *MMO,
86 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM,
88 bool X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
149 bool isScalarFPTypeInSSEReg(EVT VT) const {
150 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
151 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
154 bool isTypeLegal(Type *Ty, MVT &VT, bool AllowI1 = false);
336 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) {
342 VT = evt.getSimpleVT()
[all...] |
| /external/clang/include/clang/AST/ |
| DeclContextInternals.h | 89 DeclsTy *VT = new DeclsTy();
91 VT->push_back(OldD);
92 Data = DeclsAndHasExternalTy(VT, true);
198 DeclsTy *VT = new DeclsTy();
199 VT->push_back(OldD);
200 Data = DeclsAndHasExternalTy(VT, false);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.h | 190 bool isTypeSupportedInIntrinsic(MVT VT) const;
205 EVT getSetCCResultType(LLVMContext &Ctx, EVT VT) const override {
206 if (VT.isVector())
207 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
215 MVT VT) const override;
246 getPreferredVectorAction(EVT VT) const override;
|
| NVPTXISelLowering.cpp | 51 static bool IsPTXVectorType(MVT VT) {
52 switch (VT.SimpleTy) {
86 EVT VT = TempVTs[i];
88 if (VT.isVector())
89 for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
90 ValueVTs.push_back(VT.getVectorElementType());
92 Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
95 ValueVTs.push_back(VT);
228 MVT VT = (MVT::SimpleValueType) i;
229 if (IsPTXVectorType(VT)) {
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 448 /// Return true if this has more bits than VT.
449 bool bitsGT(MVT VT) const {
450 return getSizeInBits() > VT.getSizeInBits();
453 /// Return true if this has no less bits than VT.
454 bool bitsGE(MVT VT) const {
455 return getSizeInBits() >= VT.getSizeInBits();
458 /// Return true if this has less bits than VT.
459 bool bitsLT(MVT VT) const {
460 return getSizeInBits() < VT.getSizeInBits();
463 /// Return true if this has no more bits than VT
[all...] |
| SelectionDAGNodes.h | 387 static const EVT *getValueTypeList(EVT VT);
736 static SDVTList getSDVTList(EVT VT) {
737 SDVTList Ret = { getValueTypeList(VT), 1 };
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 256 EVT VT = N.getValueType();
259 AM.Base.Reg = CurDAG->getRegister(0, VT);
309 EVT VT = LD->getMemoryVT();
311 switch (VT.getSimpleVT().SimpleTy) {
336 MVT VT = LD->getMemoryVT().getSimpleVT();
339 switch (VT.SimpleTy) {
351 VT, MVT::i16, MVT::Other,
365 MVT VT = LD->getMemoryVT().getSimpleVT();
366 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
371 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0)
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Scalarizer.cpp | 364 VectorType *VT = dyn_cast<VectorType>(I.getType());
365 if (!VT)
368 unsigned NumElems = VT->getNumElements();
384 VectorType *VT = dyn_cast<VectorType>(SI.getType());
385 if (!VT)
388 unsigned NumElems = VT->getNumElements();
426 VectorType *VT = dyn_cast<VectorType>(GEPI.getType());
427 if (!VT)
431 unsigned NumElems = VT->getNumElements();
459 VectorType *VT = dyn_cast<VectorType>(CI.getDestTy())
[all...] |
