1 //===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Subclass of MipsTargetLowering specialized for mips32/64. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef MIPSSEISELLOWERING_H 15 #define MIPSSEISELLOWERING_H 16 17 #include "MipsISelLowering.h" 18 #include "MipsRegisterInfo.h" 19 20 namespace llvm { 21 class MipsSETargetLowering : public MipsTargetLowering { 22 public: 23 explicit MipsSETargetLowering(MipsTargetMachine &TM); 24 25 /// \brief Enable MSA support for the given integer type and Register 26 /// class. 27 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); 28 /// \brief Enable MSA support for the given floating-point type and 29 /// Register class. 30 void addMSAFloatType(MVT::SimpleValueType Ty, 31 const TargetRegisterClass *RC); 32 33 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0, 34 bool *Fast = nullptr) const override; 35 36 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 37 38 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 39 40 MachineBasicBlock * 41 EmitInstrWithCustomInserter(MachineInstr *MI, 42 MachineBasicBlock *MBB) const override; 43 44 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 45 EVT VT) const override { 46 return false; 47 } 48 49 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; 50 51 private: 52 bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 53 unsigned NextStackOffset, 54 const MipsFunctionInfo& FI) const override; 55 56 void 57 getOpndList(SmallVectorImpl<SDValue> &Ops, 58 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 59 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 60 CallLoweringInfo &CLI, SDValue Callee, 61 SDValue Chain) const override; 62 63 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 64 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 65 66 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi, 67 SelectionDAG &DAG) const; 68 69 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 70 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 71 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 72 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 73 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 74 /// \brief Lower VECTOR_SHUFFLE into one of a number of instructions 75 /// depending on the indices in the shuffle. 76 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 77 78 MachineBasicBlock *emitBPOSGE32(MachineInstr *MI, 79 MachineBasicBlock *BB) const; 80 MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI, 81 MachineBasicBlock *BB, 82 unsigned BranchOp) const; 83 /// \brief Emit the COPY_FW pseudo instruction 84 MachineBasicBlock *emitCOPY_FW(MachineInstr *MI, 85 MachineBasicBlock *BB) const; 86 /// \brief Emit the COPY_FD pseudo instruction 87 MachineBasicBlock *emitCOPY_FD(MachineInstr *MI, 88 MachineBasicBlock *BB) const; 89 /// \brief Emit the INSERT_FW pseudo instruction 90 MachineBasicBlock *emitINSERT_FW(MachineInstr *MI, 91 MachineBasicBlock *BB) const; 92 /// \brief Emit the INSERT_FD pseudo instruction 93 MachineBasicBlock *emitINSERT_FD(MachineInstr *MI, 94 MachineBasicBlock *BB) const; 95 /// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction 96 MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI, 97 MachineBasicBlock *BB, 98 unsigned EltSizeInBytes, 99 bool IsFP) const; 100 /// \brief Emit the FILL_FW pseudo instruction 101 MachineBasicBlock *emitFILL_FW(MachineInstr *MI, 102 MachineBasicBlock *BB) const; 103 /// \brief Emit the FILL_FD pseudo instruction 104 MachineBasicBlock *emitFILL_FD(MachineInstr *MI, 105 MachineBasicBlock *BB) const; 106 /// \brief Emit the FEXP2_W_1 pseudo instructions. 107 MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI, 108 MachineBasicBlock *BB) const; 109 /// \brief Emit the FEXP2_D_1 pseudo instructions. 110 MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI, 111 MachineBasicBlock *BB) const; 112 }; 113 } 114 115 #endif // MipsSEISELLOWERING_H 116
