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  /external/mesa3d/src/gallium/drivers/r300/compiler/
radeon_program.h 60 unsigned int WriteMask:4;
radeon_program_pair.h 74 unsigned int WriteMask:4;
radeon_dataflow.h 76 unsigned int WriteMask;
radeon_program_print.c 164 if (dst.WriteMask != RC_MASK_XYZW) {
166 rc_print_mask(f, dst.WriteMask);
389 if (inst->RGB.WriteMask)
391 (inst->RGB.WriteMask & 1) ? "x" : "",
392 (inst->RGB.WriteMask & 2) ? "y" : "",
393 (inst->RGB.WriteMask & 4) ? "z" : "");
428 if (inst->Alpha.WriteMask)
  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_cc.c 120 cc->cc1.stencil_write_mask = ctx->Stencil.WriteMask[0];
134 cc->cc2.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
140 if (ctx->Stencil.WriteMask[0] ||
141 (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
brw_wm_fp.c 139 reg.WriteMask = WRITEMASK_XYZW;
149 reg.WriteMask &= mask;
260 if (inst0->DstReg.WriteMask == 0)
263 dst_chan = ffs(inst0->DstReg.WriteMask) - 1;
266 inst->DstReg.WriteMask = 1 << dst_chan;
268 other_channel_mask = inst0->DstReg.WriteMask & ~(1 << dst_chan);
564 if (dst.WriteMask & WRITEMASK_Y) {
576 if (dst.WriteMask & WRITEMASK_XZ) {
592 if (dst.WriteMask & WRITEMASK_W) {
626 if (dst.WriteMask & WRITEMASK_YZ)
    [all...]
gen7_misc_state.c 115 dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);
195 ((stencil_mt != NULL && ctx->Stencil.WriteMask != 0) << 27) |
  /external/chromium_org/third_party/mesa/src/src/mesa/program/
programopt.c 93 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i);
165 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW;
177 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW;
192 newInst[3].DstReg.WriteMask = WRITEMASK_XYZW;
324 inst->DstReg.WriteMask = WRITEMASK_X;
345 inst->DstReg.WriteMask = WRITEMASK_X;
359 inst->DstReg.WriteMask = WRITEMASK_X;
372 inst->DstReg.WriteMask = WRITEMASK_X;
384 inst->DstReg.WriteMask = WRITEMASK_XYZ;
399 inst->DstReg.WriteMask = WRITEMASK_W
    [all...]
nvvertparse.c 603 dstReg->WriteMask = 0;
606 dstReg->WriteMask |= WRITEMASK_X;
610 dstReg->WriteMask |= WRITEMASK_Y;
614 dstReg->WriteMask |= WRITEMASK_Z;
618 dstReg->WriteMask |= WRITEMASK_W;
622 RETURN_ERROR1("Bad writemask character");
627 dstReg->WriteMask = WRITEMASK_XYZW;
982 inst->DstReg.WriteMask = WRITEMASK_X;
    [all...]
  /external/mesa3d/src/mesa/program/
programopt.c 93 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i);
165 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW;
177 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW;
192 newInst[3].DstReg.WriteMask = WRITEMASK_XYZW;
324 inst->DstReg.WriteMask = WRITEMASK_X;
345 inst->DstReg.WriteMask = WRITEMASK_X;
359 inst->DstReg.WriteMask = WRITEMASK_X;
372 inst->DstReg.WriteMask = WRITEMASK_X;
384 inst->DstReg.WriteMask = WRITEMASK_XYZ;
399 inst->DstReg.WriteMask = WRITEMASK_W
    [all...]
nvvertparse.c 603 dstReg->WriteMask = 0;
606 dstReg->WriteMask |= WRITEMASK_X;
610 dstReg->WriteMask |= WRITEMASK_Y;
614 dstReg->WriteMask |= WRITEMASK_Z;
618 dstReg->WriteMask |= WRITEMASK_W;
622 RETURN_ERROR1("Bad writemask character");
627 dstReg->WriteMask = WRITEMASK_XYZW;
982 inst->DstReg.WriteMask = WRITEMASK_X;
    [all...]
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
brw_wm_fp.c 139 reg.WriteMask = WRITEMASK_XYZW;
149 reg.WriteMask &= mask;
260 if (inst0->DstReg.WriteMask == 0)
263 dst_chan = ffs(inst0->DstReg.WriteMask) - 1;
266 inst->DstReg.WriteMask = 1 << dst_chan;
268 other_channel_mask = inst0->DstReg.WriteMask & ~(1 << dst_chan);
564 if (dst.WriteMask & WRITEMASK_Y) {
576 if (dst.WriteMask & WRITEMASK_XZ) {
592 if (dst.WriteMask & WRITEMASK_W) {
626 if (dst.WriteMask & WRITEMASK_YZ)
    [all...]
gen7_misc_state.c 115 dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);
195 ((stencil_mt != NULL && ctx->Stencil.WriteMask != 0) << 27) |
  /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/draw/
draw_pipe_aapoint.c 245 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XY;
259 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
276 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
288 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
301 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y;
334 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Z;
350 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Z;
363 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y;
379 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
395 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y
    [all...]
  /external/mesa3d/src/gallium/auxiliary/draw/
draw_pipe_aapoint.c 245 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XY;
259 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
276 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
288 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
301 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y;
334 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Z;
350 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Z;
363 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y;
379 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
395 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/
tgsi_exec.c 585 uint writemask = inst->Dst[0].Register.WriteMask; local
586 if (writemask == TGSI_WRITEMASK_X ||
587 writemask == TGSI_WRITEMASK_Y ||
588 writemask == TGSI_WRITEMASK_Z ||
589 writemask == TGSI_WRITEMASK_W ||
590 writemask == TGSI_WRITEMASK_NONE) {
606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
    [all...]
  /external/mesa3d/src/gallium/auxiliary/tgsi/
tgsi_exec.c 585 uint writemask = inst->Dst[0].Register.WriteMask; local
586 if (writemask == TGSI_WRITEMASK_X ||
587 writemask == TGSI_WRITEMASK_Y ||
588 writemask == TGSI_WRITEMASK_Z ||
589 writemask == TGSI_WRITEMASK_W ||
590 writemask == TGSI_WRITEMASK_NONE) {
606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
    [all...]
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/nouveau/
nv04_state_raster.c 173 if (ctx->Stencil.WriteMask[0])
182 ctx->Stencil.WriteMask[0] << 24;
  /external/chromium_org/third_party/mesa/src/src/mesa/state_tracker/
st_atom_depth.c 107 dsa->depth.writemask = ctx->Depth.Mask;
118 dsa->stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
129 dsa->stencil[1].writemask = ctx->Stencil.WriteMask[back] & 0xff;
  /external/mesa3d/src/mesa/drivers/dri/nouveau/
nv04_state_raster.c 173 if (ctx->Stencil.WriteMask[0])
182 ctx->Stencil.WriteMask[0] << 24;
  /external/mesa3d/src/mesa/state_tracker/
st_atom_depth.c 107 dsa->depth.writemask = ctx->Depth.Mask;
118 dsa->stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
129 dsa->stencil[1].writemask = ctx->Stencil.WriteMask[back] & 0xff;
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
radeon_dataflow.h 76 unsigned int WriteMask;
radeon_program_print.c 164 if (dst.WriteMask != RC_MASK_XYZW) {
166 rc_print_mask(f, dst.WriteMask);
389 if (inst->RGB.WriteMask)
391 (inst->RGB.WriteMask & 1) ? "x" : "",
392 (inst->RGB.WriteMask & 2) ? "y" : "",
393 (inst->RGB.WriteMask & 4) ? "z" : "");
428 if (inst->Alpha.WriteMask)
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
r200_vertprog.c 696 dst.WriteMask & WRITEMASK_X) {
712 t_dst_mask(dst.WriteMask));
741 t_dst_mask(dst.WriteMask));
758 t_dst_mask(dst.WriteMask));
777 t_dst_mask(dst.WriteMask));
803 t_dst_mask(dst.WriteMask));
826 t_dst_mask(dst.WriteMask));
841 t_dst_mask(dst.WriteMask));
856 t_dst_mask(dst.WriteMask));
875 t_dst_mask(dst.WriteMask));
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_vertprog.c 696 dst.WriteMask & WRITEMASK_X) {
712 t_dst_mask(dst.WriteMask));
741 t_dst_mask(dst.WriteMask));
758 t_dst_mask(dst.WriteMask));
777 t_dst_mask(dst.WriteMask));
803 t_dst_mask(dst.WriteMask));
826 t_dst_mask(dst.WriteMask));
841 t_dst_mask(dst.WriteMask));
856 t_dst_mask(dst.WriteMask));
875 t_dst_mask(dst.WriteMask));
    [all...]

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