| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 103 assert((MI->getOpcode() == Hexagon::ADJDYNALLOC) &&
140 unsigned RetOpcode = MBBI->getOpcode();
159 if (MBBI->getOpcode() == Hexagon::EH_RETURN_JMPR) {
169 MBBI->getOpcode() == Hexagon::JMPret && !DisableDeallocRet) {
175 BeforeJMPR->getOpcode() == Hexagon::RESTORE_DEALLOC_RET_JMP_V4) {
195 I->getOpcode() == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4)
333 if (MI.getOpcode() == Hexagon::ADJCALLSTACKDOWN) {
335 } else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) {
|
| HexagonISelDAGToDAG.cpp | 392 if (Const32->getOpcode() == HexagonISD::CONST32 &&
774 if ((Const32->getOpcode() == HexagonISD::CONST32) &&
777 if (Base.getOpcode() == ISD::TargetGlobalAddress) {
851 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
858 } else if (MulOp0.getOpcode() == ISD::LOAD) {
[all...] |
| HexagonCopyToCombine.cpp | 116 switch(MI->getOpcode()) {
161 return I->getOpcode() == Hexagon::TFRI &&
165 return I->getOpcode() == Hexagon::TFRI &&
174 assert((HighRegInst->getOpcode() == Hexagon::TFR ||
175 HighRegInst->getOpcode() == Hexagon::TFRI ||
176 HighRegInst->getOpcode() == Hexagon::TFRI_V4) &&
177 (LowRegInst->getOpcode() == Hexagon::TFR ||
178 LowRegInst->getOpcode() == Hexagon::TFRI ||
179 LowRegInst->getOpcode() == Hexagon::TFRI_V4) &&
190 return HighRegInst->getOpcode() == LowRegInst->getOpcode() &
[all...] |
| HexagonInstrInfo.cpp | 79 switch (MI->getOpcode()) {
104 switch (MI->getOpcode()) {
216 if (AllowModify && I->getOpcode() == Hexagon::JMP &&
245 int LastOpcode = LastInst->getOpcode();
273 int SecLastOpcode = SecondLastInst->getOpcode();
318 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
319 I->getOpcode() != BccOpcNot)
329 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot
[all...] |
| HexagonAsmPrinter.cpp | 185 if (MInst->getOpcode() == TargetOpcode::DBG_VALUE ||
186 MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) {
208 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| LiteralOpUpgrader.java | 96 Rop opcode = originalRopInsn.getOpcode();
113 RegOps.flippedIfOpcode(opcode.getOpcode()), null);
116 opcode.getOpcode(), null);
147 Rop opcode = originalRopInsn.getOpcode();
151 opcode.getOpcode() != RegOps.CONST) {
159 if (opcode.getOpcode() == RegOps.MOVE_RESULT_PSEUDO) {
|
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| LiteralOpUpgrader.java | 97 Rop opcode = originalRopInsn.getOpcode();
114 RegOps.flippedIfOpcode(opcode.getOpcode()), null);
117 opcode.getOpcode(), null);
148 Rop opcode = originalRopInsn.getOpcode();
152 opcode.getOpcode() != RegOps.CONST) {
160 if (opcode.getOpcode() == RegOps.MOVE_RESULT_PSEUDO) {
|
| /external/llvm/lib/Target/R600/ |
| R600ClauseMergePass.cpp | 34 switch (MI->getOpcode()) {
76 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm();
82 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::Enabled)).getImm();
114 if (RootCFAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
165 RootCFAlu->setDesc(TII->get(LatrCFAlu->getOpcode()));
179 TII->mustBeLastInClause(MI->getOpcode()))
|
| SIInsertWaits.cpp | 125 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags;
132 (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore()));
137 if (TII->isSMRD(MI.getOpcode())) {
170 if (MI.getOpcode() == AMDGPU::EXP)
221 ExpInstrTypesSeen |= MI.getOpcode() == AMDGPU::EXP ? 1 : 2;
249 if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM)
320 if (MI.getOpcode() == AMDGPU::S_SENDMSG)
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 47 if (MI->getOpcode() == SP::LDri ||
48 MI->getOpcode() == SP::LDXri ||
49 MI->getOpcode() == SP::LDFri ||
50 MI->getOpcode() == SP::LDDFri ||
51 MI->getOpcode() == SP::LDQFri) {
68 if (MI->getOpcode() == SP::STri ||
69 MI->getOpcode() == SP::STXri ||
70 MI->getOpcode() == SP::STFri ||
71 MI->getOpcode() == SP::STDFri ||
72 MI->getOpcode() == SP::STQFri)
[all...] |
| /external/llvm/include/llvm/IR/ |
| InstrTypes.h | 116 return I->getOpcode() == Instruction::Alloca ||
117 I->getOpcode() == Instruction::Load ||
118 I->getOpcode() == Instruction::VAArg ||
119 I->getOpcode() == Instruction::ExtractValue ||
120 (I->getOpcode() >= CastOpsBegin && I->getOpcode() < CastOpsEnd);
326 BinaryOps getOpcode() const {
327 return static_cast<BinaryOps>(Instruction::getOpcode());
608 Instruction::CastOps getOpcode() const {
609 return Instruction::CastOps(Instruction::getOpcode());
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 98 if (Addr.getOpcode() == ISD::ADD) {
119 switch (Op.getOpcode()) {
136 switch (N->getOpcode()) {
216 if (Chain->getOpcode() != ISD::TokenFactor)
238 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
268 if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper &&
269 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
|
| /external/llvm/lib/Transforms/Scalar/ |
| SeparateConstOffsetFromGEP.cpp | 320 if (BO->getOpcode() != Instruction::Add &&
321 BO->getOpcode() != Instruction::Sub &&
322 BO->getOpcode() != Instruction::Or) {
329 if (BO->getOpcode() == Instruction::Or && !NoCommonBits(LHS, RHS))
343 if (BO->getOpcode() == Instruction::Add && !ZeroExtended && NonNegative) {
364 if (BO->getOpcode() == Instruction::Add ||
365 BO->getOpcode() == Instruction::Sub) {
392 if (BO->getOpcode() == Instruction::Sub)
446 Current = ConstantExpr::getCast((*I)->getOpcode(), C, (*I)->getType());
497 NewBO = BinaryOperator::Create(BO->getOpcode(), NextInChain, TheOther
[all...] |
| /external/llvm/lib/Analysis/ |
| PHITransAddr.cpp | 34 if (Inst->getOpcode() == Instruction::Add &&
200 return AddAsInput(ConstantExpr::getCast(Cast->getOpcode(),
207 if (CastI->getOpcode() == Cast->getOpcode() &&
260 if (Inst->getOpcode() == Instruction::Add &&
272 if (BOp->getOpcode() == Instruction::Add)
300 if (BO->getOpcode() == Instruction::Add &&
388 CastInst *New = CastInst::Create(Cast->getOpcode(),
422 if (Inst->getOpcode() == Instruction::Add &&
|
| /external/llvm/lib/IR/ |
| Instruction.cpp | 269 assert(I1->getOpcode() == I2->getOpcode() &&
330 if (getOpcode() != I->getOpcode() ||
361 if (getOpcode() != I->getOpcode() ||
404 switch (getOpcode()) {
424 switch (getOpcode()) {
465 unsigned Opcode = getOpcode();
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 96 unsigned Opcode = MI.getOpcode();
296 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
297 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
310 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
311 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
|
| /dalvik/dx/src/com/android/dx/io/instructions/ |
| InstructionCodec.java | 109 out.write(codeUnit(insn.getOpcode(), insn.getA()));
126 out.write(codeUnit(insn.getOpcode(), relativeTarget));
162 codeUnit(insn.getOpcode(), insn.getLiteralByte()),
181 codeUnit(insn.getOpcode(), insn.getA()),
201 out.write(codeUnit(insn.getOpcode(), insn.getA()), relativeTarget);
219 codeUnit(insn.getOpcode(), insn.getA()),
246 int opcode = insn.getOpcode();
269 codeUnit(insn.getOpcode(), insn.getA()),
290 codeUnit(insn.getOpcode(), insn.getA()),
311 codeUnit(insn.getOpcode(), insn.getA())
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| SimpleConstraintManager.cpp | 32 switch (SIE->getOpcode()) {
53 if (BinaryOperator::isComparisonOp(SSE->getOpcode())) {
143 BinaryOperator::Opcode op = SE->getOpcode();
159 BinaryOperator::Opcode Op = SSE->getOpcode();
196 BinaryOperator::Opcode Op = SE->getOpcode();
|
| /external/dexmaker/src/dx/java/com/android/dx/io/instructions/ |
| InstructionCodec.java | 110 out.write(codeUnit(insn.getOpcode(), insn.getA()));
127 out.write(codeUnit(insn.getOpcode(), relativeTarget));
163 codeUnit(insn.getOpcode(), insn.getLiteralByte()),
182 codeUnit(insn.getOpcode(), insn.getA()),
202 out.write(codeUnit(insn.getOpcode(), insn.getA()), relativeTarget);
220 codeUnit(insn.getOpcode(), insn.getA()),
247 int opcode = insn.getOpcode();
270 codeUnit(insn.getOpcode(), insn.getA()),
291 codeUnit(insn.getOpcode(), insn.getA()),
312 codeUnit(insn.getOpcode(), insn.getA())
[all...] |
| /dalvik/dx/src/com/android/dx/rop/code/ |
| Insn.java | 124 public final Rop getOpcode() {
157 if (opcode.getOpcode() == RegOps.MARK_LOCAL) {
187 * is just a convenient wrapper for {@code getOpcode().canThrow()}.
279 return opcode == b.getOpcode()
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 152 if (isTexOp(MI.getOpcode())) {
154 } else if (isFCOp(MI.getOpcode())){
156 } else if (MI.getOpcode() == AMDGPU::RETURN ||
157 MI.getOpcode() == AMDGPU::BUNDLE ||
158 MI.getOpcode() == AMDGPU::KILL) {
161 switch(MI.getOpcode()) {
195 const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
204 if(MI.getOpcode() == AMDGPU::PRED_X)
333 const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
397 unsigned opcode = MI.getOpcode();
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| Insn.java | 124 public final Rop getOpcode() {
157 if (opcode.getOpcode() == RegOps.MARK_LOCAL) {
187 * is just a convenient wrapper for {@code getOpcode().canThrow()}.
279 return opcode == b.getOpcode()
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430BranchSelector.cpp | 106 if ((I->getOpcode() != MSP430::JCC || I->getOperand(0).isImm()) &&
107 I->getOpcode() != MSP430::JMP) {
145 if (I->getOpcode() == MSP430::JMP) {
|
| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| SparcInstPrinter.cpp | 56 switch (MI->getOpcode()) {
90 switch(MI->getOpcode()) {
153 switch (MI->getOpcode()) {
|
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 152 if (isTexOp(MI.getOpcode())) {
154 } else if (isFCOp(MI.getOpcode())){
156 } else if (MI.getOpcode() == AMDGPU::RETURN ||
157 MI.getOpcode() == AMDGPU::BUNDLE ||
158 MI.getOpcode() == AMDGPU::KILL) {
161 switch(MI.getOpcode()) {
195 const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
204 if(MI.getOpcode() == AMDGPU::PRED_X)
333 const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
397 unsigned opcode = MI.getOpcode();
[all...] |
