| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 567 switch (Op.getOpcode()) {
[all...] |
| AArch64ISelDAGToDAG.cpp | 211 return N->getOpcode() == Opc &&
290 switch (N.getOpcode()) {
343 if (N.getOpcode() == ISD::SIGN_EXTEND ||
344 N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
346 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
360 } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
361 N.getOpcode() == ISD::ANY_EXTEND) {
372 } else if (N.getOpcode() == ISD::AND) {
395 if (DL->getOpcode() != AArch64ISD::DUPLANE16 &&
396 DL->getOpcode() != AArch64ISD::DUPLANE32
[all...] |
| AArch64ConditionalCompares.cpp | 304 switch (I->getOpcode()) {
321 switch (I->getOpcode()) {
615 switch (CmpMI->getOpcode()) {
668 bool isNZ = CmpMI->getOpcode() == AArch64::CBNZW ||
669 CmpMI->getOpcode() == AArch64::CBNZX;
705 switch (CmpMI->getOpcode()) {
|
| AArch64CleanupLocalDynamicTLSPass.cpp | 64 switch (I->getOpcode()) {
|
| /external/llvm/include/llvm/IR/ |
| Instructions.h | 131 return (I->getOpcode() == Instruction::Alloca);
252 return I->getOpcode() == Instruction::Load;
374 return I->getOpcode() == Instruction::Store;
445 return I->getOpcode() == Instruction::Fence;
594 return I->getOpcode() == Instruction::AtomicCmpXchg;
738 return I->getOpcode() == Instruction::AtomicRMW;
[all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | 242 if (CE->getOpcode() == Instruction::PtrToInt ||
243 CE->getOpcode() == Instruction::BitCast)
382 if (CE->getOpcode() == Instruction::IntToPtr &&
535 if (CE->getOpcode() == Instruction::GetElementPtr) {
545 if (CE->getOpcode() == Instruction::BitCast)
750 if (CE && CE->getOpcode() == Instruction::Sub &&
795 if (CE->getOpcode() == Instruction::IntToPtr) {
[all...] |
| CaptureTracking.cpp | 104 switch (I->getOpcode()) {
|
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | 603 assert(CPEMI && CPEMI->getOpcode() == ARM::CONSTPOOL_ENTRY);
626 if (I->isBranch() && I->getOpcode() == ARM::t2BR_JT)
668 int Opc = I->getOpcode();
818 if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) {
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombinePHI.cpp | 29 unsigned Opc = FirstInst->getOpcode();
48 if (!I || I->getOpcode() != Opc || !I->hasOneUse() ||
116 CmpInst *NewCI = CmpInst::Create(CIOp->getOpcode(), CIOp->getPredicate(),
124 BinaryOperator::Create(BinOp->getOpcode(), LHSVal, RHSVal);
484 CastInst *NewCI = CastInst::Create(FirstCI->getOpcode(), PhiVal,
491 BinOp = BinaryOperator::Create(BinOp->getOpcode(), PhiVal, ConstantOp);
500 CmpInst *NewCI = CmpInst::Create(CIOp->getOpcode(), CIOp->getPredicate(),
669 if (UserI->getOpcode() != Instruction::LShr ||
798 cast<Instruction>(PN.getIncomingValue(0))->getOpcode() ==
799 cast<Instruction>(PN.getIncomingValue(1))->getOpcode() &
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 134 if (N.getOpcode() == ISD::TargetConstant ||
135 N.getOpcode() == ISD::TargetGlobalAddress) {
296 if (N->getOpcode() != ISD::Constant)
314 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
324 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
342 return N->getOpcode() == Opc
380 unsigned Opcode = N->getOpcode();
427 unsigned Op0Opc = Op0.getOpcode();
428 unsigned Op1Opc = Op1.getOpcode();
436 if (Op0.getOperand(0).getOpcode() == ISD::SHL |
[all...] |
| PPCHazardRecognizers.cpp | 125 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1)
333 unsigned Opcode = MI->getOpcode();
391 unsigned Opcode = MI->getOpcode();
|
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 194 switch (MI->getOpcode()) {
198 if (TII->isLDSRetInstr(MI->getOpcode())) {
199 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
206 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
269 unsigned EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
271 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
522 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
523 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
532 bool EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
535 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | [all...] |
| ScheduleDAGSDNodes.h | 68 if (Node->getOpcode() == ISD::EntryToken ||
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| OutputFinisher.java | 395 result[i] = insns.get(i).getOpcode();
534 guess.getOpcode() != Opcodes.CONST_STRING) {
553 Dop result = findOpcodeForInsn(insn.getLowRegVersion(), insn.getOpcode());
595 Dop originalOpcode = insn.getOpcode();
630 Dop originalOpcode = insn.getOpcode();
738 Dop opcode = insn.getOpcode();
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 66 switch (Inst.getOpcode()) {
87 int Opcode = InstIn.getOpcode();
155 switch (MI.getOpcode()) {
175 unsigned Opcode = TmpInst.getOpcode();
190 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
536 switch(MI.getOpcode())
|
| /external/llvm/lib/IR/ |
| Instructions.cpp | [all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| InsnFormat.java | 46 String op = insn.getOpcode().getName();
409 int opcode = insn.getOpcode().getOpcode();
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| ConstCollector.java | 174 if (insn == null || insn.getOpcode() == null) continue;
184 if (insn.getOpcode().getOpcode() == RegOps.MOVE_RESULT_PSEUDO) {
|
| SsaInsn.java | 178 abstract public Rop getOpcode();
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| TestAfterDivZeroChecker.cpp | 108 BinaryOperator::Opcode Op = BO->getOpcode();
204 BinaryOperator::Opcode Op = B->getOpcode();
233 if (U->getOpcode() == UO_LNot) {
|
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| ConstCollector.java | 174 if (insn == null || insn.getOpcode() == null) continue;
184 if (insn.getOpcode().getOpcode() == RegOps.MOVE_RESULT_PSEUDO) {
|
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 81 switch (MI->getOpcode()) {
116 switch (MI->getOpcode()) {
272 switch (MI.getOpcode()) {
|
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 265 switch (Inst.getOpcode()) {
346 OutMI.setOpcode(MI->getOpcode());
389 switch (OutMI.getOpcode()) {
422 switch (OutMI.getOpcode()) {
446 switch (OutMI.getOpcode()) {
462 unsigned Opcode = OutMI.getOpcode();
482 switch (OutMI.getOpcode()) {
610 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
611 MI.getOpcode() == X86::TLS_base_addr64;
613 bool needsPadding = MI.getOpcode() == X86::TLS_addr64
[all...] |
