| /external/llvm/test/Transforms/InstCombine/ |
| vector-type.ll | 6 define i32 @vselect1(i32 %a.coerce, i32 %b.coerce, i32 %c.coerce) {
8 %0 = bitcast i32 %a.coerce to <2 x i16>
9 %1 = bitcast i32 %b.coerce to <2 x i16>
10 %2 = bitcast i32 %c.coerce to <2 x i16>
|
| /external/llvm/test/CodeGen/Mips/ |
| dsp-patterns-cmp-vselect.ll | 7 define { i32 } @select_v2q15_eq_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
9 %0 = bitcast i32 %a0.coerce to <2 x i16>
10 %1 = bitcast i32 %a1.coerce to <2 x i16>
11 %2 = bitcast i32 %a2.coerce to <2 x i16>
12 %3 = bitcast i32 %a3.coerce to <2 x i16>
24 define { i32 } @select_v2q15_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce)
[all...] |
| dsp-r2.ll | 3 define i64 @test__builtin_mips_dpa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
7 %1 = bitcast i32 %a1.coerce to <2 x i16>
8 %2 = bitcast i32 %a2.coerce to <2 x i16>
15 define i64 @test__builtin_mips_dps_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
19 %1 = bitcast i32 %a1.coerce to <2 x i16>
20 %2 = bitcast i32 %a2.coerce to <2 x i16>
27 define i64 @test__builtin_mips_mulsa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone
[all...] |
| dsp-r1.ll | 111 define i64 @test__builtin_mips_dpau_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
115 %1 = bitcast i32 %a1.coerce to <4 x i8>
116 %2 = bitcast i32 %a2.coerce to <4 x i8>
123 define i64 @test__builtin_mips_dpau_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
127 %1 = bitcast i32 %a1.coerce to <4 x i8>
128 %2 = bitcast i32 %a2.coerce to <4 x i8>
135 define i64 @test__builtin_mips_dpsu_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone
[all...] |
| dsp-patterns.ll | 37 define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
39 %0 = bitcast i32 %a.coerce to <2 x i16>
40 %1 = bitcast i32 %b.coerce to <2 x i16>
50 define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
52 %0 = bitcast i32 %a.coerce to <2 x i16>
53 %1 = bitcast i32 %b.coerce to <2 x i16>
68 define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) {
[all...] |
| spill-copy-acreg.ll | 27 define { i32 } @test_ccond_spill(i32 %a.coerce, i32 %b.coerce) {
29 %0 = bitcast i32 %a.coerce to <2 x i16>
30 %1 = bitcast i32 %b.coerce to <2 x i16>
|
| /external/llvm/test/Transforms/SLPVectorizer/ARM/ |
| sroa.ll | 15 define void @SROAed(%class.Complex* noalias nocapture sret %agg.result, [4 x i32] %a.coerce, [4 x i32] %b.coerce) {
17 %a.coerce.fca.0.extract = extractvalue [4 x i32] %a.coerce, 0
18 %a.sroa.0.0.insert.ext = zext i32 %a.coerce.fca.0.extract to i64
19 %a.coerce.fca.1.extract = extractvalue [4 x i32] %a.coerce, 1
20 %a.sroa.0.4.insert.ext = zext i32 %a.coerce.fca.1.extract to i64
24 %a.coerce.fca.2.extract = extractvalue [4 x i32] %a.coerce,
[all...] |
| /external/clang/test/CodeGen/ |
| ppc64-struct-onevect.c | 12 // CHECK-LABEL: define <4 x float> @foo(<4 x float> inreg %a.coerce)
13 // CHECK: ret <4 x float> %a.coerce
|
| arm64-aapcs-arguments.c | 6 // CHECK: void @test1(i32 %x0, i128 %x2_x3, i128 %x4_x5, i128 %x6_x7, i128 %sp.coerce)
12 // CHECK: void @test2(i32 %x0, i128 %x2_x3.coerce, i32 %x4, i128 %x6_x7.coerce, i32 %sp, i128 %sp16.coerce)
16 // We coerce HFAs into a contiguous [N x double] type if they're going on the
20 // CHECK: void @test3(float %s0_s3.0, float %s0_s3.1, float %s0_s3.2, float %s0_s3.3, float %s4, [3 x float], [2 x double] %sp.coerce, [2 x double] %sp16.coerce)
27 // sufficient alignment to avoid holes on their own. We could coerce to [N x
|
| ppc64-vector.c | 12 // CHECK: define i32 @test_v2i16(i32 %x.coerce)
18 // CHECK: define i64 @test_v3i16(i64 %x.coerce)
24 // CHECK: define i64 @test_v4i16(i64 %x.coerce)
|
| incomplete-function-type-2.c | 5 // CHECK: define void @test10_foo({}* %p1.coerce) [[NUW:#[0-9]+]] {
|
| x86_32-arguments-nommx.c | 6 // CHECK-LABEL: define i32 @a(i64 %x.coerce)
|
| /external/llvm/test/CodeGen/PowerPC/ |
| varargs-struct-float.ll | 8 define void @foo(float inreg %s.coerce) nounwind {
11 %coerce.dive = getelementptr %struct.Sf1* %s, i32 0, i32 0
12 store float %s.coerce, float* %coerce.dive, align 1
13 %coerce.dive1 = getelementptr %struct.Sf1* %s, i32 0, i32 0
14 %0 = load float* %coerce.dive1, align 1
|
| /external/clang/test/CodeGenObjC/ |
| x86_64-struct-return-gc.m | 2 struct Coerce {
6 struct Coerce coerce_func(void);
10 struct Coerce c;
|
| /frameworks/rs/driver/runtime/ll32/ |
| allocation.ll | 4 declare i8* @rsOffset([1 x i32] %a.coerce, i32 %sizeOf, i32 %x, i32 %y, i32 %z)
5 declare i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z)
31 define void @rsSetElementAtImpl_char([1 x i32] %a.coerce, i8 signext %val, i32 %x, i32 %y, i32 %z) #1 {
32 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2
37 define signext i8 @rsGetElementAtImpl_char([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 {
38 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2
44 define void @rsSetElementAtImpl_char2([1 x i32] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #1 {
45 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2
51 define <2 x i8> @rsGetElementAtImpl_char2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 {
52 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-dagcombiner-convergence.ll | 8 define i64 @foo(i128 %Params.coerce, i128 %SelLocs.coerce) {
10 %tmp = lshr i128 %Params.coerce, 61
13 %tmp1 = lshr i128 %SelLocs.coerce, 62
|
| assertion-rc-mismatch.ll | 20 %coerce.val.pi56 = ptrtoint i8* %tmp to i64
21 ret i64 %coerce.val.pi56
|
| arm64-abi_align.ll | 35 define i32 @f38(i32 %i, i64 %s1.coerce, i64 %s2.coerce) #0 {
40 %s1.sroa.0.0.extract.trunc = trunc i64 %s1.coerce to i32
41 %s1.sroa.1.4.extract.shift = lshr i64 %s1.coerce, 32
42 %s2.sroa.0.0.extract.trunc = trunc i64 %s2.coerce to i32
43 %s2.sroa.1.4.extract.shift = lshr i64 %s2.coerce, 32
69 i32 %i7, i32 %i8, i32 %i9, i64 %s1.coerce, i64 %s2.coerce) #0
88 define i32 @f39(i32 %i, i128 %s1.coerce, i128 %s2.coerce) #0
[all...] |
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/test/ |
| test_compare.py | 8 class Coerce:
13 return '<Coerce %s>' % self.arg
16 if isinstance(other, Coerce):
32 set1 = [2, 2.0, 2L, 2+0j, Coerce(2), Cmp(2.0)]
|
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/test/ |
| test_compare.py | 8 class Coerce:
13 return '<Coerce %s>' % self.arg
16 if isinstance(other, Coerce):
32 set1 = [2, 2.0, 2L, 2+0j, Coerce(2), Cmp(2.0)]
|
| /external/llvm/test/Transforms/LoopUnswitch/ |
| 2010-11-18-LCSSA.ll | 5 define void @func_67(i32 %p_68.coerce) nounwind {
14 %tobool.i = icmp eq i32 %p_68.coerce, 1
15 %xor4.i = xor i32 %p_68.coerce, 1
|
| /external/llvm/test/CodeGen/X86/ |
| pmovext.ll | 25 define <4 x i32> @foo0(double %v.coerce) nounwind ssp {
29 %tmp = bitcast double %v.coerce to <4 x i16>
35 define <8 x i16> @foo1(double %v.coerce) nounwind ssp {
39 %tmp = bitcast double %v.coerce to <8 x i8>
|
| /external/llvm/test/CodeGen/ARM/ |
| dagcombine-concatvector.ll | 13 define void @test1(i8* %arg, [4 x i64] %vec.coerce) {
15 %tmp = extractvalue [4 x i64] %vec.coerce, 0
18 %tmp4 = extractvalue [4 x i64] %vec.coerce, 1
|
| ssp-data-layout.ll | 155 %coerce.dive = getelementptr %struct.struct_large_char* %a, i32 0, i32 0
156 %3 = bitcast [8 x i8]* %coerce.dive to i64*
158 %coerce.dive25 = getelementptr %struct.struct_small_char* %b, i32 0, i32 0
159 %5 = bitcast [2 x i8]* %coerce.dive25 to i16*
161 %coerce.dive26 = getelementptr %struct.struct_small_nonchar* %d, i32 0, i32 0
162 %7 = bitcast [2 x i16]* %coerce.dive26 to i32*
302 %coerce.dive = getelementptr %struct.struct_large_char* %a, i32 0, i32 0
303 %3 = bitcast [8 x i8]* %coerce.dive to i64*
305 %coerce.dive25 = getelementptr %struct.struct_small_char* %b, i32 0, i32 0
306 %5 = bitcast [2 x i8]* %coerce.dive25 to i16
[all...] |
| /external/clang/test/CodeGenCXX/ |
| blocks-cxx11.cpp | 53 // CHECK-NEXT: [[COERCE:%.*]] = bitcast
54 // CHECK-NEXT: [[CVAL:%.*]] = load i64* [[COERCE]]
79 // CHECK-NEXT: [[COERCE:%.*]] = bitcast { i32, i32 }* [[CSLOT]] to i64*
80 // CHECK-NEXT: [[CVAL:%.*]] = load i64* [[COERCE]],
|
