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    Searched full:uncached_cpsr (Results 1 - 5 of 5) sorted by null

  /external/qemu/target-arm/
helper.c 315 env->uncached_cpsr = ARM_CPU_MODE_USR;
325 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
329 env->uncached_cpsr &= ~CPSR_I;
524 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
555 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
559 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
714 old_mode = env->uncached_cpsr & CPSR_M;
862 env->uncached_cpsr &= ~CPSR_IT;
904 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
    [all...]
cpu.h 117 uint32_t uncached_cpsr; member in struct:CPUARMState
575 if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
810 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
818 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR;
892 privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
op_helper.c 298 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
313 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
machine.c 133 env->uncached_cpsr = val & CPSR_M;
  /external/qemu/
cpu-exec.c 459 && !(env->uncached_cpsr & CPSR_F)) {
475 || !(env->uncached_cpsr & CPSR_I))) {
    [all...]

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