1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_I915_DRM_H_ 20 #define _UAPI_I915_DRM_H_ 21 #include <drm/drm.h> 22 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define I915_ERROR_UEVENT "ERROR" 25 #define I915_RESET_UEVENT "RESET" 26 #define I915_NR_TEX_REGIONS 255 27 #define I915_LOG_MIN_TEX_REGION_SIZE 14 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 typedef struct _drm_i915_init { 30 enum { 31 I915_INIT_DMA = 0x01, 32 I915_CLEANUP_DMA = 0x02, 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 I915_RESUME_DMA = 0x03 35 } func; 36 unsigned int mmio_offset; 37 int sarea_priv_offset; 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 unsigned int ring_start; 40 unsigned int ring_end; 41 unsigned int ring_size; 42 unsigned int front_offset; 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 unsigned int back_offset; 45 unsigned int depth_offset; 46 unsigned int w; 47 unsigned int h; 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 unsigned int pitch; 50 unsigned int pitch_bits; 51 unsigned int back_pitch; 52 unsigned int depth_pitch; 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 unsigned int cpp; 55 unsigned int chipset; 56 } drm_i915_init_t; 57 typedef struct _drm_i915_sarea { 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 60 int last_upload; 61 int last_enqueue; 62 int last_dispatch; 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 int ctxOwner; 65 int texAge; 66 int pf_enabled; 67 int pf_active; 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 int pf_current_page; 70 int perf_boxes; 71 int width, height; 72 drm_handle_t front_handle; 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 int front_offset; 75 int front_size; 76 drm_handle_t back_handle; 77 int back_offset; 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 int back_size; 80 drm_handle_t depth_handle; 81 int depth_offset; 82 int depth_size; 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 drm_handle_t tex_handle; 85 int tex_offset; 86 int tex_size; 87 int log_tex_granularity; 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 int pitch; 90 int rotation; 91 int rotated_offset; 92 int rotated_size; 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 int rotated_pitch; 95 int virtualX, virtualY; 96 unsigned int front_tiled; 97 unsigned int back_tiled; 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 unsigned int depth_tiled; 100 unsigned int rotated_tiled; 101 unsigned int rotated2_tiled; 102 int pipeA_x; 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 int pipeA_y; 105 int pipeA_w; 106 int pipeA_h; 107 int pipeB_x; 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 int pipeB_y; 110 int pipeB_w; 111 int pipeB_h; 112 drm_handle_t unused_handle; 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 __u32 unused1, unused2, unused3; 115 __u32 front_bo_handle; 116 __u32 back_bo_handle; 117 __u32 unused_bo_handle; 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 __u32 depth_bo_handle; 120 } drm_i915_sarea_t; 121 #define planeA_x pipeA_x 122 #define planeA_y pipeA_y 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 #define planeA_w pipeA_w 125 #define planeA_h pipeA_h 126 #define planeB_x pipeB_x 127 #define planeB_y pipeB_y 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 #define planeB_w pipeB_w 130 #define planeB_h pipeB_h 131 #define I915_BOX_RING_EMPTY 0x1 132 #define I915_BOX_FLIP 0x2 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 #define I915_BOX_WAIT 0x4 135 #define I915_BOX_TEXTURE_LOAD 0x8 136 #define I915_BOX_LOST_CONTEXT 0x10 137 #define DRM_I915_INIT 0x00 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 #define DRM_I915_FLUSH 0x01 140 #define DRM_I915_FLIP 0x02 141 #define DRM_I915_BATCHBUFFER 0x03 142 #define DRM_I915_IRQ_EMIT 0x04 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 #define DRM_I915_IRQ_WAIT 0x05 145 #define DRM_I915_GETPARAM 0x06 146 #define DRM_I915_SETPARAM 0x07 147 #define DRM_I915_ALLOC 0x08 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 #define DRM_I915_FREE 0x09 150 #define DRM_I915_INIT_HEAP 0x0a 151 #define DRM_I915_CMDBUFFER 0x0b 152 #define DRM_I915_DESTROY_HEAP 0x0c 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 #define DRM_I915_SET_VBLANK_PIPE 0x0d 155 #define DRM_I915_GET_VBLANK_PIPE 0x0e 156 #define DRM_I915_VBLANK_SWAP 0x0f 157 #define DRM_I915_HWS_ADDR 0x11 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 #define DRM_I915_GEM_INIT 0x13 160 #define DRM_I915_GEM_EXECBUFFER 0x14 161 #define DRM_I915_GEM_PIN 0x15 162 #define DRM_I915_GEM_UNPIN 0x16 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 #define DRM_I915_GEM_BUSY 0x17 165 #define DRM_I915_GEM_THROTTLE 0x18 166 #define DRM_I915_GEM_ENTERVT 0x19 167 #define DRM_I915_GEM_LEAVEVT 0x1a 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 #define DRM_I915_GEM_CREATE 0x1b 170 #define DRM_I915_GEM_PREAD 0x1c 171 #define DRM_I915_GEM_PWRITE 0x1d 172 #define DRM_I915_GEM_MMAP 0x1e 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 #define DRM_I915_GEM_SET_DOMAIN 0x1f 175 #define DRM_I915_GEM_SW_FINISH 0x20 176 #define DRM_I915_GEM_SET_TILING 0x21 177 #define DRM_I915_GEM_GET_TILING 0x22 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 #define DRM_I915_GEM_GET_APERTURE 0x23 180 #define DRM_I915_GEM_MMAP_GTT 0x24 181 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 182 #define DRM_I915_GEM_MADVISE 0x26 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 185 #define DRM_I915_OVERLAY_ATTRS 0x28 186 #define DRM_I915_GEM_EXECBUFFER2 0x29 187 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 190 #define DRM_I915_GEM_WAIT 0x2c 191 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 192 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 #define DRM_I915_GEM_SET_CACHING 0x2f 195 #define DRM_I915_GEM_GET_CACHING 0x30 196 #define DRM_I915_REG_READ 0x31 197 #define DRM_I915_GET_RESET_STATS 0x32 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 200 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 201 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 202 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 205 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 206 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 207 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 210 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 211 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 212 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 215 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 216 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 217 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 220 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 221 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 222 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 225 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 226 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 227 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 230 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 231 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 232 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 235 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 236 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 237 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 240 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 241 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 242 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 245 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 246 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 247 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 250 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 251 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 252 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 255 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 256 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 257 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 260 typedef struct drm_i915_batchbuffer { 261 int start; 262 int used; 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 int DR1; 265 int DR4; 266 int num_cliprects; 267 struct drm_clip_rect __user *cliprects; 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 } drm_i915_batchbuffer_t; 270 typedef struct _drm_i915_cmdbuffer { 271 char __user *buf; 272 int sz; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 int DR1; 275 int DR4; 276 int num_cliprects; 277 struct drm_clip_rect __user *cliprects; 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 } drm_i915_cmdbuffer_t; 280 typedef struct drm_i915_irq_emit { 281 int __user *irq_seq; 282 } drm_i915_irq_emit_t; 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 typedef struct drm_i915_irq_wait { 285 int irq_seq; 286 } drm_i915_irq_wait_t; 287 #define I915_PARAM_IRQ_ACTIVE 1 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 #define I915_PARAM_ALLOW_BATCHBUFFER 2 290 #define I915_PARAM_LAST_DISPATCH 3 291 #define I915_PARAM_CHIPSET_ID 4 292 #define I915_PARAM_HAS_GEM 5 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 #define I915_PARAM_NUM_FENCES_AVAIL 6 295 #define I915_PARAM_HAS_OVERLAY 7 296 #define I915_PARAM_HAS_PAGEFLIPPING 8 297 #define I915_PARAM_HAS_EXECBUF2 9 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 #define I915_PARAM_HAS_BSD 10 300 #define I915_PARAM_HAS_BLT 11 301 #define I915_PARAM_HAS_RELAXED_FENCING 12 302 #define I915_PARAM_HAS_COHERENT_RINGS 13 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 305 #define I915_PARAM_HAS_RELAXED_DELTA 15 306 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 307 #define I915_PARAM_HAS_LLC 17 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 #define I915_PARAM_HAS_ALIASING_PPGTT 18 310 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 311 #define I915_PARAM_HAS_SEMAPHORES 20 312 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 #define I915_PARAM_HAS_VEBOX 22 315 #define I915_PARAM_HAS_SECURE_BATCHES 23 316 #define I915_PARAM_HAS_PINNED_BATCHES 24 317 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 320 #define I915_PARAM_HAS_WT 27 321 typedef struct drm_i915_getparam { 322 int param; 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 int __user *value; 325 } drm_i915_getparam_t; 326 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 327 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 330 #define I915_SETPARAM_NUM_USED_FENCES 4 331 typedef struct drm_i915_setparam { 332 int param; 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 int value; 335 } drm_i915_setparam_t; 336 #define I915_MEM_REGION_AGP 1 337 typedef struct drm_i915_mem_alloc { 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 int region; 340 int alignment; 341 int size; 342 int __user *region_offset; 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 } drm_i915_mem_alloc_t; 345 typedef struct drm_i915_mem_free { 346 int region; 347 int region_offset; 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 } drm_i915_mem_free_t; 350 typedef struct drm_i915_mem_init_heap { 351 int region; 352 int size; 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 int start; 355 } drm_i915_mem_init_heap_t; 356 typedef struct drm_i915_mem_destroy_heap { 357 int region; 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 } drm_i915_mem_destroy_heap_t; 360 #define DRM_I915_VBLANK_PIPE_A 1 361 #define DRM_I915_VBLANK_PIPE_B 2 362 typedef struct drm_i915_vblank_pipe { 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 int pipe; 365 } drm_i915_vblank_pipe_t; 366 typedef struct drm_i915_vblank_swap { 367 drm_drawable_t drawable; 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 enum drm_vblank_seq_type seqtype; 370 unsigned int sequence; 371 } drm_i915_vblank_swap_t; 372 typedef struct drm_i915_hws_addr { 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 __u64 addr; 375 } drm_i915_hws_addr_t; 376 struct drm_i915_gem_init { 377 __u64 gtt_start; 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 __u64 gtt_end; 380 }; 381 struct drm_i915_gem_create { 382 __u64 size; 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 __u32 handle; 385 __u32 pad; 386 }; 387 struct drm_i915_gem_pread { 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 __u32 handle; 390 __u32 pad; 391 __u64 offset; 392 __u64 size; 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 __u64 data_ptr; 395 }; 396 struct drm_i915_gem_pwrite { 397 __u32 handle; 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 __u32 pad; 400 __u64 offset; 401 __u64 size; 402 __u64 data_ptr; 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 }; 405 struct drm_i915_gem_mmap { 406 __u32 handle; 407 __u32 pad; 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 __u64 offset; 410 __u64 size; 411 __u64 addr_ptr; 412 }; 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 struct drm_i915_gem_mmap_gtt { 415 __u32 handle; 416 __u32 pad; 417 __u64 offset; 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 }; 420 struct drm_i915_gem_set_domain { 421 __u32 handle; 422 __u32 read_domains; 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 __u32 write_domain; 425 }; 426 struct drm_i915_gem_sw_finish { 427 __u32 handle; 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 }; 430 struct drm_i915_gem_relocation_entry { 431 __u32 target_handle; 432 __u32 delta; 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 __u64 offset; 435 __u64 presumed_offset; 436 __u32 read_domains; 437 __u32 write_domain; 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 }; 440 #define I915_GEM_DOMAIN_CPU 0x00000001 441 #define I915_GEM_DOMAIN_RENDER 0x00000002 442 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 #define I915_GEM_DOMAIN_COMMAND 0x00000008 445 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 446 #define I915_GEM_DOMAIN_VERTEX 0x00000020 447 #define I915_GEM_DOMAIN_GTT 0x00000040 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 struct drm_i915_gem_exec_object { 450 __u32 handle; 451 __u32 relocation_count; 452 __u64 relocs_ptr; 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 __u64 alignment; 455 __u64 offset; 456 }; 457 struct drm_i915_gem_execbuffer { 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 __u64 buffers_ptr; 460 __u32 buffer_count; 461 __u32 batch_start_offset; 462 __u32 batch_len; 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 __u32 DR1; 465 __u32 DR4; 466 __u32 num_cliprects; 467 __u64 cliprects_ptr; 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 }; 470 struct drm_i915_gem_exec_object2 { 471 __u32 handle; 472 __u32 relocation_count; 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 __u64 relocs_ptr; 475 __u64 alignment; 476 __u64 offset; 477 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 #define EXEC_OBJECT_NEEDS_GTT (1<<1) 480 #define EXEC_OBJECT_WRITE (1<<2) 481 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) 482 __u64 flags; 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 __u64 rsvd1; 485 __u64 rsvd2; 486 }; 487 struct drm_i915_gem_execbuffer2 { 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 __u64 buffers_ptr; 490 __u32 buffer_count; 491 __u32 batch_start_offset; 492 __u32 batch_len; 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 __u32 DR1; 495 __u32 DR4; 496 __u32 num_cliprects; 497 __u64 cliprects_ptr; 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 #define I915_EXEC_RING_MASK (7<<0) 500 #define I915_EXEC_DEFAULT (0<<0) 501 #define I915_EXEC_RENDER (1<<0) 502 #define I915_EXEC_BSD (2<<0) 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 #define I915_EXEC_BLT (3<<0) 505 #define I915_EXEC_VEBOX (4<<0) 506 #define I915_EXEC_CONSTANTS_MASK (3<<6) 507 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 510 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) 511 __u64 flags; 512 __u64 rsvd1; 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 __u64 rsvd2; 515 }; 516 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 517 #define I915_EXEC_SECURE (1<<9) 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 #define I915_EXEC_IS_PINNED (1<<10) 520 #define I915_EXEC_NO_RELOC (1<<11) 521 #define I915_EXEC_HANDLE_LUT (1<<12) 522 #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 525 #define i915_execbuffer2_set_context_id(eb2, context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 526 #define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 527 struct drm_i915_gem_pin { 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 __u32 handle; 530 __u32 pad; 531 __u64 alignment; 532 __u64 offset; 533 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 }; 535 struct drm_i915_gem_unpin { 536 __u32 handle; 537 __u32 pad; 538 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 }; 540 struct drm_i915_gem_busy { 541 __u32 handle; 542 __u32 busy; 543 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 }; 545 #define I915_CACHING_NONE 0 546 #define I915_CACHING_CACHED 1 547 #define I915_CACHING_DISPLAY 2 548 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 struct drm_i915_gem_caching { 550 __u32 handle; 551 __u32 caching; 552 }; 553 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 #define I915_TILING_NONE 0 555 #define I915_TILING_X 1 556 #define I915_TILING_Y 2 557 #define I915_BIT_6_SWIZZLE_NONE 0 558 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 #define I915_BIT_6_SWIZZLE_9 1 560 #define I915_BIT_6_SWIZZLE_9_10 2 561 #define I915_BIT_6_SWIZZLE_9_11 3 562 #define I915_BIT_6_SWIZZLE_9_10_11 4 563 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 565 #define I915_BIT_6_SWIZZLE_9_17 6 566 #define I915_BIT_6_SWIZZLE_9_10_17 7 567 struct drm_i915_gem_set_tiling { 568 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 __u32 handle; 570 __u32 tiling_mode; 571 __u32 stride; 572 __u32 swizzle_mode; 573 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 }; 575 struct drm_i915_gem_get_tiling { 576 __u32 handle; 577 __u32 tiling_mode; 578 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 __u32 swizzle_mode; 580 }; 581 struct drm_i915_gem_get_aperture { 582 __u64 aper_size; 583 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 __u64 aper_available_size; 585 }; 586 struct drm_i915_get_pipe_from_crtc_id { 587 __u32 crtc_id; 588 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 __u32 pipe; 590 }; 591 #define I915_MADV_WILLNEED 0 592 #define I915_MADV_DONTNEED 1 593 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 #define __I915_MADV_PURGED 2 595 struct drm_i915_gem_madvise { 596 __u32 handle; 597 __u32 madv; 598 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599 __u32 retained; 600 }; 601 #define I915_OVERLAY_TYPE_MASK 0xff 602 #define I915_OVERLAY_YUV_PLANAR 0x01 603 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 #define I915_OVERLAY_YUV_PACKED 0x02 605 #define I915_OVERLAY_RGB 0x03 606 #define I915_OVERLAY_DEPTH_MASK 0xff00 607 #define I915_OVERLAY_RGB24 0x1000 608 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609 #define I915_OVERLAY_RGB16 0x2000 610 #define I915_OVERLAY_RGB15 0x3000 611 #define I915_OVERLAY_YUV422 0x0100 612 #define I915_OVERLAY_YUV411 0x0200 613 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 #define I915_OVERLAY_YUV420 0x0300 615 #define I915_OVERLAY_YUV410 0x0400 616 #define I915_OVERLAY_SWAP_MASK 0xff0000 617 #define I915_OVERLAY_NO_SWAP 0x000000 618 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 #define I915_OVERLAY_UV_SWAP 0x010000 620 #define I915_OVERLAY_Y_SWAP 0x020000 621 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 622 #define I915_OVERLAY_FLAGS_MASK 0xff000000 623 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 #define I915_OVERLAY_ENABLE 0x01000000 625 struct drm_intel_overlay_put_image { 626 __u32 flags; 627 __u32 bo_handle; 628 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 __u16 stride_Y; 630 __u16 stride_UV; 631 __u32 offset_Y; 632 __u32 offset_U; 633 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 __u32 offset_V; 635 __u16 src_width; 636 __u16 src_height; 637 __u16 src_scan_width; 638 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639 __u16 src_scan_height; 640 __u32 crtc_id; 641 __u16 dst_x; 642 __u16 dst_y; 643 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644 __u16 dst_width; 645 __u16 dst_height; 646 }; 647 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 648 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 650 struct drm_intel_overlay_attrs { 651 __u32 flags; 652 __u32 color_key; 653 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654 __s32 brightness; 655 __u32 contrast; 656 __u32 saturation; 657 __u32 gamma0; 658 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659 __u32 gamma1; 660 __u32 gamma2; 661 __u32 gamma3; 662 __u32 gamma4; 663 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 __u32 gamma5; 665 }; 666 #define I915_SET_COLORKEY_NONE (1<<0) 667 #define I915_SET_COLORKEY_DESTINATION (1<<1) 668 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669 #define I915_SET_COLORKEY_SOURCE (1<<2) 670 struct drm_intel_sprite_colorkey { 671 __u32 plane_id; 672 __u32 min_value; 673 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 __u32 channel_mask; 675 __u32 max_value; 676 __u32 flags; 677 }; 678 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679 struct drm_i915_gem_wait { 680 __u32 bo_handle; 681 __u32 flags; 682 __s64 timeout_ns; 683 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684 }; 685 struct drm_i915_gem_context_create { 686 __u32 ctx_id; 687 __u32 pad; 688 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 }; 690 struct drm_i915_gem_context_destroy { 691 __u32 ctx_id; 692 __u32 pad; 693 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694 }; 695 struct drm_i915_reg_read { 696 __u64 offset; 697 __u64 val; 698 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 }; 700 struct drm_i915_reset_stats { 701 __u32 ctx_id; 702 __u32 flags; 703 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704 __u32 reset_count; 705 __u32 batch_active; 706 __u32 batch_pending; 707 __u32 pad; 708 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 }; 710 #endif 711
