1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 2 // All Rights Reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are 6 // met: 7 // 8 // - Redistributions of source code must retain the above copyright notice, 9 // this list of conditions and the following disclaimer. 10 // 11 // - Redistribution in binary form must reproduce the above copyright 12 // notice, this list of conditions and the following disclaimer in the 13 // documentation and/or other materials provided with the distribution. 14 // 15 // - Neither the name of Sun Microsystems or the names of contributors may 16 // be used to endorse or promote products derived from this software without 17 // specific prior written permission. 18 // 19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 31 // The original source code covered by the above license above has been 32 // modified significantly by Google Inc. 33 // Copyright 2011 the V8 project authors. All rights reserved. 34 35 // A light-weight IA32 Assembler. 36 37 #ifndef V8_IA32_ASSEMBLER_IA32_H_ 38 #define V8_IA32_ASSEMBLER_IA32_H_ 39 40 #include "src/isolate.h" 41 #include "src/serialize.h" 42 43 namespace v8 { 44 namespace internal { 45 46 // CPU Registers. 47 // 48 // 1) We would prefer to use an enum, but enum values are assignment- 49 // compatible with int, which has caused code-generation bugs. 50 // 51 // 2) We would prefer to use a class instead of a struct but we don't like 52 // the register initialization to depend on the particular initialization 53 // order (which appears to be different on OS X, Linux, and Windows for the 54 // installed versions of C++ we tried). Using a struct permits C-style 55 // "initialization". Also, the Register objects cannot be const as this 56 // forces initialization stubs in MSVC, making us dependent on initialization 57 // order. 58 // 59 // 3) By not using an enum, we are possibly preventing the compiler from 60 // doing certain constant folds, which may significantly reduce the 61 // code generated for some assembly instructions (because they boil down 62 // to a few constants). If this is a problem, we could change the code 63 // such that we use an enum in optimized mode, and the struct in debug 64 // mode. This way we get the compile-time error checking in debug mode 65 // and best performance in optimized code. 66 // 67 struct Register { 68 static const int kMaxNumAllocatableRegisters = 6; 69 static int NumAllocatableRegisters() { 70 return kMaxNumAllocatableRegisters; 71 } 72 static const int kNumRegisters = 8; 73 74 static inline const char* AllocationIndexToString(int index); 75 76 static inline int ToAllocationIndex(Register reg); 77 78 static inline Register FromAllocationIndex(int index); 79 80 static Register from_code(int code) { 81 ASSERT(code >= 0); 82 ASSERT(code < kNumRegisters); 83 Register r = { code }; 84 return r; 85 } 86 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; } 87 bool is(Register reg) const { return code_ == reg.code_; } 88 // eax, ebx, ecx and edx are byte registers, the rest are not. 89 bool is_byte_register() const { return code_ <= 3; } 90 int code() const { 91 ASSERT(is_valid()); 92 return code_; 93 } 94 int bit() const { 95 ASSERT(is_valid()); 96 return 1 << code_; 97 } 98 99 // Unfortunately we can't make this private in a struct. 100 int code_; 101 }; 102 103 const int kRegister_eax_Code = 0; 104 const int kRegister_ecx_Code = 1; 105 const int kRegister_edx_Code = 2; 106 const int kRegister_ebx_Code = 3; 107 const int kRegister_esp_Code = 4; 108 const int kRegister_ebp_Code = 5; 109 const int kRegister_esi_Code = 6; 110 const int kRegister_edi_Code = 7; 111 const int kRegister_no_reg_Code = -1; 112 113 const Register eax = { kRegister_eax_Code }; 114 const Register ecx = { kRegister_ecx_Code }; 115 const Register edx = { kRegister_edx_Code }; 116 const Register ebx = { kRegister_ebx_Code }; 117 const Register esp = { kRegister_esp_Code }; 118 const Register ebp = { kRegister_ebp_Code }; 119 const Register esi = { kRegister_esi_Code }; 120 const Register edi = { kRegister_edi_Code }; 121 const Register no_reg = { kRegister_no_reg_Code }; 122 123 124 inline const char* Register::AllocationIndexToString(int index) { 125 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 126 // This is the mapping of allocation indices to registers. 127 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" }; 128 return kNames[index]; 129 } 130 131 132 inline int Register::ToAllocationIndex(Register reg) { 133 ASSERT(reg.is_valid() && !reg.is(esp) && !reg.is(ebp)); 134 return (reg.code() >= 6) ? reg.code() - 2 : reg.code(); 135 } 136 137 138 inline Register Register::FromAllocationIndex(int index) { 139 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 140 return (index >= 4) ? from_code(index + 2) : from_code(index); 141 } 142 143 144 struct XMMRegister { 145 static const int kMaxNumAllocatableRegisters = 7; 146 static const int kMaxNumRegisters = 8; 147 static int NumAllocatableRegisters() { 148 return kMaxNumAllocatableRegisters; 149 } 150 151 static int ToAllocationIndex(XMMRegister reg) { 152 ASSERT(reg.code() != 0); 153 return reg.code() - 1; 154 } 155 156 static XMMRegister FromAllocationIndex(int index) { 157 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 158 return from_code(index + 1); 159 } 160 161 static XMMRegister from_code(int code) { 162 XMMRegister result = { code }; 163 return result; 164 } 165 166 bool is_valid() const { 167 return 0 <= code_ && code_ < kMaxNumRegisters; 168 } 169 170 int code() const { 171 ASSERT(is_valid()); 172 return code_; 173 } 174 175 bool is(XMMRegister reg) const { return code_ == reg.code_; } 176 177 static const char* AllocationIndexToString(int index) { 178 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 179 const char* const names[] = { 180 "xmm1", 181 "xmm2", 182 "xmm3", 183 "xmm4", 184 "xmm5", 185 "xmm6", 186 "xmm7" 187 }; 188 return names[index]; 189 } 190 191 int code_; 192 }; 193 194 195 typedef XMMRegister DoubleRegister; 196 197 198 const XMMRegister xmm0 = { 0 }; 199 const XMMRegister xmm1 = { 1 }; 200 const XMMRegister xmm2 = { 2 }; 201 const XMMRegister xmm3 = { 3 }; 202 const XMMRegister xmm4 = { 4 }; 203 const XMMRegister xmm5 = { 5 }; 204 const XMMRegister xmm6 = { 6 }; 205 const XMMRegister xmm7 = { 7 }; 206 const XMMRegister no_xmm_reg = { -1 }; 207 208 209 enum Condition { 210 // any value < 0 is considered no_condition 211 no_condition = -1, 212 213 overflow = 0, 214 no_overflow = 1, 215 below = 2, 216 above_equal = 3, 217 equal = 4, 218 not_equal = 5, 219 below_equal = 6, 220 above = 7, 221 negative = 8, 222 positive = 9, 223 parity_even = 10, 224 parity_odd = 11, 225 less = 12, 226 greater_equal = 13, 227 less_equal = 14, 228 greater = 15, 229 230 // aliases 231 carry = below, 232 not_carry = above_equal, 233 zero = equal, 234 not_zero = not_equal, 235 sign = negative, 236 not_sign = positive 237 }; 238 239 240 // Returns the equivalent of !cc. 241 // Negation of the default no_condition (-1) results in a non-default 242 // no_condition value (-2). As long as tests for no_condition check 243 // for condition < 0, this will work as expected. 244 inline Condition NegateCondition(Condition cc) { 245 return static_cast<Condition>(cc ^ 1); 246 } 247 248 249 // Commute a condition such that {a cond b == b cond' a}. 250 inline Condition CommuteCondition(Condition cc) { 251 switch (cc) { 252 case below: 253 return above; 254 case above: 255 return below; 256 case above_equal: 257 return below_equal; 258 case below_equal: 259 return above_equal; 260 case less: 261 return greater; 262 case greater: 263 return less; 264 case greater_equal: 265 return less_equal; 266 case less_equal: 267 return greater_equal; 268 default: 269 return cc; 270 } 271 } 272 273 274 // ----------------------------------------------------------------------------- 275 // Machine instruction Immediates 276 277 class Immediate BASE_EMBEDDED { 278 public: 279 inline explicit Immediate(int x); 280 inline explicit Immediate(const ExternalReference& ext); 281 inline explicit Immediate(Handle<Object> handle); 282 inline explicit Immediate(Smi* value); 283 inline explicit Immediate(Address addr); 284 285 static Immediate CodeRelativeOffset(Label* label) { 286 return Immediate(label); 287 } 288 289 bool is_zero() const { return x_ == 0 && RelocInfo::IsNone(rmode_); } 290 bool is_int8() const { 291 return -128 <= x_ && x_ < 128 && RelocInfo::IsNone(rmode_); 292 } 293 bool is_int16() const { 294 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_); 295 } 296 297 private: 298 inline explicit Immediate(Label* value); 299 300 int x_; 301 RelocInfo::Mode rmode_; 302 303 friend class Assembler; 304 friend class MacroAssembler; 305 }; 306 307 308 // ----------------------------------------------------------------------------- 309 // Machine instruction Operands 310 311 enum ScaleFactor { 312 times_1 = 0, 313 times_2 = 1, 314 times_4 = 2, 315 times_8 = 3, 316 times_int_size = times_4, 317 times_half_pointer_size = times_2, 318 times_pointer_size = times_4, 319 times_twice_pointer_size = times_8 320 }; 321 322 323 class Operand BASE_EMBEDDED { 324 public: 325 // XMM reg 326 INLINE(explicit Operand(XMMRegister xmm_reg)); 327 328 // [disp/r] 329 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode)); 330 // disp only must always be relocated 331 332 // [base + disp/r] 333 explicit Operand(Register base, int32_t disp, 334 RelocInfo::Mode rmode = RelocInfo::NONE32); 335 336 // [base + index*scale + disp/r] 337 explicit Operand(Register base, 338 Register index, 339 ScaleFactor scale, 340 int32_t disp, 341 RelocInfo::Mode rmode = RelocInfo::NONE32); 342 343 // [index*scale + disp/r] 344 explicit Operand(Register index, 345 ScaleFactor scale, 346 int32_t disp, 347 RelocInfo::Mode rmode = RelocInfo::NONE32); 348 349 static Operand StaticVariable(const ExternalReference& ext) { 350 return Operand(reinterpret_cast<int32_t>(ext.address()), 351 RelocInfo::EXTERNAL_REFERENCE); 352 } 353 354 static Operand StaticArray(Register index, 355 ScaleFactor scale, 356 const ExternalReference& arr) { 357 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()), 358 RelocInfo::EXTERNAL_REFERENCE); 359 } 360 361 static Operand ForCell(Handle<Cell> cell) { 362 AllowDeferredHandleDereference embedding_raw_address; 363 return Operand(reinterpret_cast<int32_t>(cell.location()), 364 RelocInfo::CELL); 365 } 366 367 // Returns true if this Operand is a wrapper for the specified register. 368 bool is_reg(Register reg) const; 369 370 // Returns true if this Operand is a wrapper for one register. 371 bool is_reg_only() const; 372 373 // Asserts that this Operand is a wrapper for one register and returns the 374 // register. 375 Register reg() const; 376 377 private: 378 // reg 379 INLINE(explicit Operand(Register reg)); 380 381 // Set the ModRM byte without an encoded 'reg' register. The 382 // register is encoded later as part of the emit_operand operation. 383 inline void set_modrm(int mod, Register rm); 384 385 inline void set_sib(ScaleFactor scale, Register index, Register base); 386 inline void set_disp8(int8_t disp); 387 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode); 388 389 byte buf_[6]; 390 // The number of bytes in buf_. 391 unsigned int len_; 392 // Only valid if len_ > 4. 393 RelocInfo::Mode rmode_; 394 395 friend class Assembler; 396 friend class MacroAssembler; 397 friend class LCodeGen; 398 }; 399 400 401 // ----------------------------------------------------------------------------- 402 // A Displacement describes the 32bit immediate field of an instruction which 403 // may be used together with a Label in order to refer to a yet unknown code 404 // position. Displacements stored in the instruction stream are used to describe 405 // the instruction and to chain a list of instructions using the same Label. 406 // A Displacement contains 2 different fields: 407 // 408 // next field: position of next displacement in the chain (0 = end of list) 409 // type field: instruction type 410 // 411 // A next value of null (0) indicates the end of a chain (note that there can 412 // be no displacement at position zero, because there is always at least one 413 // instruction byte before the displacement). 414 // 415 // Displacement _data field layout 416 // 417 // |31.....2|1......0| 418 // [ next | type | 419 420 class Displacement BASE_EMBEDDED { 421 public: 422 enum Type { 423 UNCONDITIONAL_JUMP, 424 CODE_RELATIVE, 425 OTHER 426 }; 427 428 int data() const { return data_; } 429 Type type() const { return TypeField::decode(data_); } 430 void next(Label* L) const { 431 int n = NextField::decode(data_); 432 n > 0 ? L->link_to(n) : L->Unuse(); 433 } 434 void link_to(Label* L) { init(L, type()); } 435 436 explicit Displacement(int data) { data_ = data; } 437 438 Displacement(Label* L, Type type) { init(L, type); } 439 440 void print() { 441 PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"), 442 NextField::decode(data_)); 443 } 444 445 private: 446 int data_; 447 448 class TypeField: public BitField<Type, 0, 2> {}; 449 class NextField: public BitField<int, 2, 32-2> {}; 450 451 void init(Label* L, Type type); 452 }; 453 454 455 class Assembler : public AssemblerBase { 456 private: 457 // We check before assembling an instruction that there is sufficient 458 // space to write an instruction and its relocation information. 459 // The relocation writer's position must be kGap bytes above the end of 460 // the generated instructions. This leaves enough space for the 461 // longest possible ia32 instruction, 15 bytes, and the longest possible 462 // relocation information encoding, RelocInfoWriter::kMaxLength == 16. 463 // (There is a 15 byte limit on ia32 instruction length that rules out some 464 // otherwise valid instructions.) 465 // This allows for a single, fast space check per instruction. 466 static const int kGap = 32; 467 468 public: 469 // Create an assembler. Instructions and relocation information are emitted 470 // into a buffer, with the instructions starting from the beginning and the 471 // relocation information starting from the end of the buffer. See CodeDesc 472 // for a detailed comment on the layout (globals.h). 473 // 474 // If the provided buffer is NULL, the assembler allocates and grows its own 475 // buffer, and buffer_size determines the initial buffer size. The buffer is 476 // owned by the assembler and deallocated upon destruction of the assembler. 477 // 478 // If the provided buffer is not NULL, the assembler uses the provided buffer 479 // for code generation and assumes its size to be buffer_size. If the buffer 480 // is too small, a fatal error occurs. No deallocation of the buffer is done 481 // upon destruction of the assembler. 482 // TODO(vitalyr): the assembler does not need an isolate. 483 Assembler(Isolate* isolate, void* buffer, int buffer_size); 484 virtual ~Assembler() { } 485 486 // GetCode emits any pending (non-emitted) code and fills the descriptor 487 // desc. GetCode() is idempotent; it returns the same result if no other 488 // Assembler functions are invoked in between GetCode() calls. 489 void GetCode(CodeDesc* desc); 490 491 // Read/Modify the code target in the branch/call instruction at pc. 492 inline static Address target_address_at(Address pc, 493 ConstantPoolArray* constant_pool); 494 inline static void set_target_address_at(Address pc, 495 ConstantPoolArray* constant_pool, 496 Address target, 497 ICacheFlushMode icache_flush_mode = 498 FLUSH_ICACHE_IF_NEEDED); 499 static inline Address target_address_at(Address pc, Code* code) { 500 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL; 501 return target_address_at(pc, constant_pool); 502 } 503 static inline void set_target_address_at(Address pc, 504 Code* code, 505 Address target, 506 ICacheFlushMode icache_flush_mode = 507 FLUSH_ICACHE_IF_NEEDED) { 508 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL; 509 set_target_address_at(pc, constant_pool, target); 510 } 511 512 // Return the code target address at a call site from the return address 513 // of that call in the instruction stream. 514 inline static Address target_address_from_return_address(Address pc); 515 516 // This sets the branch destination (which is in the instruction on x86). 517 // This is for calls and branches within generated code. 518 inline static void deserialization_set_special_target_at( 519 Address instruction_payload, Code* code, Address target) { 520 set_target_address_at(instruction_payload, code, target); 521 } 522 523 static const int kSpecialTargetSize = kPointerSize; 524 525 // Distance between the address of the code target in the call instruction 526 // and the return address 527 static const int kCallTargetAddressOffset = kPointerSize; 528 // Distance between start of patched return sequence and the emitted address 529 // to jump to. 530 static const int kPatchReturnSequenceAddressOffset = 1; // JMP imm32. 531 532 // Distance between start of patched debug break slot and the emitted address 533 // to jump to. 534 static const int kPatchDebugBreakSlotAddressOffset = 1; // JMP imm32. 535 536 static const int kCallInstructionLength = 5; 537 static const int kPatchDebugBreakSlotReturnOffset = kPointerSize; 538 static const int kJSReturnSequenceLength = 6; 539 540 // The debug break slot must be able to contain a call instruction. 541 static const int kDebugBreakSlotLength = kCallInstructionLength; 542 543 // One byte opcode for test al, 0xXX. 544 static const byte kTestAlByte = 0xA8; 545 // One byte opcode for nop. 546 static const byte kNopByte = 0x90; 547 548 // One byte opcode for a short unconditional jump. 549 static const byte kJmpShortOpcode = 0xEB; 550 // One byte prefix for a short conditional jump. 551 static const byte kJccShortPrefix = 0x70; 552 static const byte kJncShortOpcode = kJccShortPrefix | not_carry; 553 static const byte kJcShortOpcode = kJccShortPrefix | carry; 554 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero; 555 static const byte kJzShortOpcode = kJccShortPrefix | zero; 556 557 558 // --------------------------------------------------------------------------- 559 // Code generation 560 // 561 // - function names correspond one-to-one to ia32 instruction mnemonics 562 // - unless specified otherwise, instructions operate on 32bit operands 563 // - instructions on 8bit (byte) operands/registers have a trailing '_b' 564 // - instructions on 16bit (word) operands/registers have a trailing '_w' 565 // - naming conflicts with C++ keywords are resolved via a trailing '_' 566 567 // NOTE ON INTERFACE: Currently, the interface is not very consistent 568 // in the sense that some operations (e.g. mov()) can be called in more 569 // the one way to generate the same instruction: The Register argument 570 // can in some cases be replaced with an Operand(Register) argument. 571 // This should be cleaned up and made more orthogonal. The questions 572 // is: should we always use Operands instead of Registers where an 573 // Operand is possible, or should we have a Register (overloaded) form 574 // instead? We must be careful to make sure that the selected instruction 575 // is obvious from the parameters to avoid hard-to-find code generation 576 // bugs. 577 578 // Insert the smallest number of nop instructions 579 // possible to align the pc offset to a multiple 580 // of m. m must be a power of 2. 581 void Align(int m); 582 void Nop(int bytes = 1); 583 // Aligns code to something that's optimal for a jump target for the platform. 584 void CodeTargetAlign(); 585 586 // Stack 587 void pushad(); 588 void popad(); 589 590 void pushfd(); 591 void popfd(); 592 593 void push(const Immediate& x); 594 void push_imm32(int32_t imm32); 595 void push(Register src); 596 void push(const Operand& src); 597 598 void pop(Register dst); 599 void pop(const Operand& dst); 600 601 void enter(const Immediate& size); 602 void leave(); 603 604 // Moves 605 void mov_b(Register dst, Register src) { mov_b(dst, Operand(src)); } 606 void mov_b(Register dst, const Operand& src); 607 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); } 608 void mov_b(const Operand& dst, int8_t imm8); 609 void mov_b(const Operand& dst, Register src); 610 611 void mov_w(Register dst, const Operand& src); 612 void mov_w(const Operand& dst, Register src); 613 void mov_w(const Operand& dst, int16_t imm16); 614 615 void mov(Register dst, int32_t imm32); 616 void mov(Register dst, const Immediate& x); 617 void mov(Register dst, Handle<Object> handle); 618 void mov(Register dst, const Operand& src); 619 void mov(Register dst, Register src); 620 void mov(const Operand& dst, const Immediate& x); 621 void mov(const Operand& dst, Handle<Object> handle); 622 void mov(const Operand& dst, Register src); 623 624 void movsx_b(Register dst, Register src) { movsx_b(dst, Operand(src)); } 625 void movsx_b(Register dst, const Operand& src); 626 627 void movsx_w(Register dst, Register src) { movsx_w(dst, Operand(src)); } 628 void movsx_w(Register dst, const Operand& src); 629 630 void movzx_b(Register dst, Register src) { movzx_b(dst, Operand(src)); } 631 void movzx_b(Register dst, const Operand& src); 632 633 void movzx_w(Register dst, Register src) { movzx_w(dst, Operand(src)); } 634 void movzx_w(Register dst, const Operand& src); 635 636 // Conditional moves 637 void cmov(Condition cc, Register dst, Register src) { 638 cmov(cc, dst, Operand(src)); 639 } 640 void cmov(Condition cc, Register dst, const Operand& src); 641 642 // Flag management. 643 void cld(); 644 645 // Repetitive string instructions. 646 void rep_movs(); 647 void rep_stos(); 648 void stos(); 649 650 // Exchange two registers 651 void xchg(Register dst, Register src); 652 653 // Arithmetics 654 void adc(Register dst, int32_t imm32); 655 void adc(Register dst, const Operand& src); 656 657 void add(Register dst, Register src) { add(dst, Operand(src)); } 658 void add(Register dst, const Operand& src); 659 void add(const Operand& dst, Register src); 660 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); } 661 void add(const Operand& dst, const Immediate& x); 662 663 void and_(Register dst, int32_t imm32); 664 void and_(Register dst, const Immediate& x); 665 void and_(Register dst, Register src) { and_(dst, Operand(src)); } 666 void and_(Register dst, const Operand& src); 667 void and_(const Operand& dst, Register src); 668 void and_(const Operand& dst, const Immediate& x); 669 670 void cmpb(Register reg, int8_t imm8) { cmpb(Operand(reg), imm8); } 671 void cmpb(const Operand& op, int8_t imm8); 672 void cmpb(Register reg, const Operand& op); 673 void cmpb(const Operand& op, Register reg); 674 void cmpb_al(const Operand& op); 675 void cmpw_ax(const Operand& op); 676 void cmpw(const Operand& op, Immediate imm16); 677 void cmp(Register reg, int32_t imm32); 678 void cmp(Register reg, Handle<Object> handle); 679 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); } 680 void cmp(Register reg, const Operand& op); 681 void cmp(Register reg, const Immediate& imm) { cmp(Operand(reg), imm); } 682 void cmp(const Operand& op, const Immediate& imm); 683 void cmp(const Operand& op, Handle<Object> handle); 684 685 void dec_b(Register dst); 686 void dec_b(const Operand& dst); 687 688 void dec(Register dst); 689 void dec(const Operand& dst); 690 691 void cdq(); 692 693 void idiv(Register src); 694 695 // Signed multiply instructions. 696 void imul(Register src); // edx:eax = eax * src. 697 void imul(Register dst, Register src) { imul(dst, Operand(src)); } 698 void imul(Register dst, const Operand& src); // dst = dst * src. 699 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32. 700 701 void inc(Register dst); 702 void inc(const Operand& dst); 703 704 void lea(Register dst, const Operand& src); 705 706 // Unsigned multiply instruction. 707 void mul(Register src); // edx:eax = eax * reg. 708 709 void neg(Register dst); 710 711 void not_(Register dst); 712 713 void or_(Register dst, int32_t imm32); 714 void or_(Register dst, Register src) { or_(dst, Operand(src)); } 715 void or_(Register dst, const Operand& src); 716 void or_(const Operand& dst, Register src); 717 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); } 718 void or_(const Operand& dst, const Immediate& x); 719 720 void rcl(Register dst, uint8_t imm8); 721 void rcr(Register dst, uint8_t imm8); 722 void ror(Register dst, uint8_t imm8); 723 void ror_cl(Register dst); 724 725 void sar(Register dst, uint8_t imm8); 726 void sar_cl(Register dst); 727 728 void sbb(Register dst, const Operand& src); 729 730 void shld(Register dst, Register src) { shld(dst, Operand(src)); } 731 void shld(Register dst, const Operand& src); 732 733 void shl(Register dst, uint8_t imm8); 734 void shl_cl(Register dst); 735 736 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); } 737 void shrd(Register dst, const Operand& src); 738 739 void shr(Register dst, uint8_t imm8); 740 void shr_cl(Register dst); 741 742 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); } 743 void sub(const Operand& dst, const Immediate& x); 744 void sub(Register dst, Register src) { sub(dst, Operand(src)); } 745 void sub(Register dst, const Operand& src); 746 void sub(const Operand& dst, Register src); 747 748 void test(Register reg, const Immediate& imm); 749 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); } 750 void test(Register reg, const Operand& op); 751 void test_b(Register reg, const Operand& op); 752 void test(const Operand& op, const Immediate& imm); 753 void test_b(Register reg, uint8_t imm8); 754 void test_b(const Operand& op, uint8_t imm8); 755 756 void xor_(Register dst, int32_t imm32); 757 void xor_(Register dst, Register src) { xor_(dst, Operand(src)); } 758 void xor_(Register dst, const Operand& src); 759 void xor_(const Operand& dst, Register src); 760 void xor_(Register dst, const Immediate& imm) { xor_(Operand(dst), imm); } 761 void xor_(const Operand& dst, const Immediate& x); 762 763 // Bit operations. 764 void bt(const Operand& dst, Register src); 765 void bts(Register dst, Register src) { bts(Operand(dst), src); } 766 void bts(const Operand& dst, Register src); 767 void bsr(Register dst, Register src) { bsr(dst, Operand(src)); } 768 void bsr(Register dst, const Operand& src); 769 770 // Miscellaneous 771 void hlt(); 772 void int3(); 773 void nop(); 774 void ret(int imm16); 775 776 // Label operations & relative jumps (PPUM Appendix D) 777 // 778 // Takes a branch opcode (cc) and a label (L) and generates 779 // either a backward branch or a forward branch and links it 780 // to the label fixup chain. Usage: 781 // 782 // Label L; // unbound label 783 // j(cc, &L); // forward branch to unbound label 784 // bind(&L); // bind label to the current pc 785 // j(cc, &L); // backward branch to bound label 786 // bind(&L); // illegal: a label may be bound only once 787 // 788 // Note: The same Label can be used for forward and backward branches 789 // but it may be bound only once. 790 791 void bind(Label* L); // binds an unbound label L to the current code position 792 793 // Calls 794 void call(Label* L); 795 void call(byte* entry, RelocInfo::Mode rmode); 796 int CallSize(const Operand& adr); 797 void call(Register reg) { call(Operand(reg)); } 798 void call(const Operand& adr); 799 int CallSize(Handle<Code> code, RelocInfo::Mode mode); 800 void call(Handle<Code> code, 801 RelocInfo::Mode rmode, 802 TypeFeedbackId id = TypeFeedbackId::None()); 803 804 // Jumps 805 // unconditional jump to L 806 void jmp(Label* L, Label::Distance distance = Label::kFar); 807 void jmp(byte* entry, RelocInfo::Mode rmode); 808 void jmp(Register reg) { jmp(Operand(reg)); } 809 void jmp(const Operand& adr); 810 void jmp(Handle<Code> code, RelocInfo::Mode rmode); 811 812 // Conditional jumps 813 void j(Condition cc, 814 Label* L, 815 Label::Distance distance = Label::kFar); 816 void j(Condition cc, byte* entry, RelocInfo::Mode rmode); 817 void j(Condition cc, Handle<Code> code); 818 819 // Floating-point operations 820 void fld(int i); 821 void fstp(int i); 822 823 void fld1(); 824 void fldz(); 825 void fldpi(); 826 void fldln2(); 827 828 void fld_s(const Operand& adr); 829 void fld_d(const Operand& adr); 830 831 void fstp_s(const Operand& adr); 832 void fst_s(const Operand& adr); 833 void fstp_d(const Operand& adr); 834 void fst_d(const Operand& adr); 835 836 void fild_s(const Operand& adr); 837 void fild_d(const Operand& adr); 838 839 void fist_s(const Operand& adr); 840 841 void fistp_s(const Operand& adr); 842 void fistp_d(const Operand& adr); 843 844 // The fisttp instructions require SSE3. 845 void fisttp_s(const Operand& adr); 846 void fisttp_d(const Operand& adr); 847 848 void fabs(); 849 void fchs(); 850 void fcos(); 851 void fsin(); 852 void fptan(); 853 void fyl2x(); 854 void f2xm1(); 855 void fscale(); 856 void fninit(); 857 858 void fadd(int i); 859 void fadd_i(int i); 860 void fsub(int i); 861 void fsub_i(int i); 862 void fmul(int i); 863 void fmul_i(int i); 864 void fdiv(int i); 865 void fdiv_i(int i); 866 867 void fisub_s(const Operand& adr); 868 869 void faddp(int i = 1); 870 void fsubp(int i = 1); 871 void fsubrp(int i = 1); 872 void fmulp(int i = 1); 873 void fdivp(int i = 1); 874 void fprem(); 875 void fprem1(); 876 877 void fxch(int i = 1); 878 void fincstp(); 879 void ffree(int i = 0); 880 881 void ftst(); 882 void fucomp(int i); 883 void fucompp(); 884 void fucomi(int i); 885 void fucomip(); 886 void fcompp(); 887 void fnstsw_ax(); 888 void fwait(); 889 void fnclex(); 890 891 void frndint(); 892 893 void sahf(); 894 void setcc(Condition cc, Register reg); 895 896 void cpuid(); 897 898 // SSE instructions 899 void movaps(XMMRegister dst, XMMRegister src); 900 void shufps(XMMRegister dst, XMMRegister src, byte imm8); 901 902 void andps(XMMRegister dst, const Operand& src); 903 void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); } 904 void xorps(XMMRegister dst, const Operand& src); 905 void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); } 906 void orps(XMMRegister dst, const Operand& src); 907 void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); } 908 909 void addps(XMMRegister dst, const Operand& src); 910 void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); } 911 void subps(XMMRegister dst, const Operand& src); 912 void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); } 913 void mulps(XMMRegister dst, const Operand& src); 914 void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); } 915 void divps(XMMRegister dst, const Operand& src); 916 void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); } 917 918 // SSE2 instructions 919 void cvttss2si(Register dst, const Operand& src); 920 void cvttss2si(Register dst, XMMRegister src) { 921 cvttss2si(dst, Operand(src)); 922 } 923 void cvttsd2si(Register dst, const Operand& src); 924 void cvtsd2si(Register dst, XMMRegister src); 925 926 void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); } 927 void cvtsi2sd(XMMRegister dst, const Operand& src); 928 void cvtss2sd(XMMRegister dst, XMMRegister src); 929 void cvtsd2ss(XMMRegister dst, XMMRegister src); 930 931 void addsd(XMMRegister dst, XMMRegister src); 932 void addsd(XMMRegister dst, const Operand& src); 933 void subsd(XMMRegister dst, XMMRegister src); 934 void mulsd(XMMRegister dst, XMMRegister src); 935 void mulsd(XMMRegister dst, const Operand& src); 936 void divsd(XMMRegister dst, XMMRegister src); 937 void xorpd(XMMRegister dst, XMMRegister src); 938 void sqrtsd(XMMRegister dst, XMMRegister src); 939 void sqrtsd(XMMRegister dst, const Operand& src); 940 941 void andpd(XMMRegister dst, XMMRegister src); 942 void orpd(XMMRegister dst, XMMRegister src); 943 944 void ucomisd(XMMRegister dst, XMMRegister src) { ucomisd(dst, Operand(src)); } 945 void ucomisd(XMMRegister dst, const Operand& src); 946 947 enum RoundingMode { 948 kRoundToNearest = 0x0, 949 kRoundDown = 0x1, 950 kRoundUp = 0x2, 951 kRoundToZero = 0x3 952 }; 953 954 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode); 955 956 void movmskpd(Register dst, XMMRegister src); 957 void movmskps(Register dst, XMMRegister src); 958 959 void cmpltsd(XMMRegister dst, XMMRegister src); 960 void pcmpeqd(XMMRegister dst, XMMRegister src); 961 962 void movdqa(XMMRegister dst, const Operand& src); 963 void movdqa(const Operand& dst, XMMRegister src); 964 void movdqu(XMMRegister dst, const Operand& src); 965 void movdqu(const Operand& dst, XMMRegister src); 966 void movdq(bool aligned, XMMRegister dst, const Operand& src) { 967 if (aligned) { 968 movdqa(dst, src); 969 } else { 970 movdqu(dst, src); 971 } 972 } 973 974 void movd(XMMRegister dst, Register src) { movd(dst, Operand(src)); } 975 void movd(XMMRegister dst, const Operand& src); 976 void movd(Register dst, XMMRegister src) { movd(Operand(dst), src); } 977 void movd(const Operand& dst, XMMRegister src); 978 void movsd(XMMRegister dst, XMMRegister src) { movsd(dst, Operand(src)); } 979 void movsd(XMMRegister dst, const Operand& src); 980 void movsd(const Operand& dst, XMMRegister src); 981 982 983 void movss(XMMRegister dst, const Operand& src); 984 void movss(const Operand& dst, XMMRegister src); 985 void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); } 986 void extractps(Register dst, XMMRegister src, byte imm8); 987 988 void pand(XMMRegister dst, XMMRegister src); 989 void pxor(XMMRegister dst, XMMRegister src); 990 void por(XMMRegister dst, XMMRegister src); 991 void ptest(XMMRegister dst, XMMRegister src); 992 993 void psllq(XMMRegister reg, int8_t shift); 994 void psllq(XMMRegister dst, XMMRegister src); 995 void psrlq(XMMRegister reg, int8_t shift); 996 void psrlq(XMMRegister dst, XMMRegister src); 997 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle); 998 void pextrd(Register dst, XMMRegister src, int8_t offset) { 999 pextrd(Operand(dst), src, offset); 1000 } 1001 void pextrd(const Operand& dst, XMMRegister src, int8_t offset); 1002 void pinsrd(XMMRegister dst, Register src, int8_t offset) { 1003 pinsrd(dst, Operand(src), offset); 1004 } 1005 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset); 1006 1007 // Parallel XMM operations. 1008 void movntdqa(XMMRegister dst, const Operand& src); 1009 void movntdq(const Operand& dst, XMMRegister src); 1010 // Prefetch src position into cache level. 1011 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a 1012 // non-temporal 1013 void prefetch(const Operand& src, int level); 1014 // TODO(lrn): Need SFENCE for movnt? 1015 1016 // Debugging 1017 void Print(); 1018 1019 // Check the code size generated from label to here. 1020 int SizeOfCodeGeneratedSince(Label* label) { 1021 return pc_offset() - label->pos(); 1022 } 1023 1024 // Mark address of the ExitJSFrame code. 1025 void RecordJSReturn(); 1026 1027 // Mark address of a debug break slot. 1028 void RecordDebugBreakSlot(); 1029 1030 // Record a comment relocation entry that can be used by a disassembler. 1031 // Use --code-comments to enable, or provide "force = true" flag to always 1032 // write a comment. 1033 void RecordComment(const char* msg, bool force = false); 1034 1035 // Writes a single byte or word of data in the code stream. Used for 1036 // inline tables, e.g., jump-tables. 1037 void db(uint8_t data); 1038 void dd(uint32_t data); 1039 1040 // Check if there is less than kGap bytes available in the buffer. 1041 // If this is the case, we need to grow the buffer before emitting 1042 // an instruction or relocation information. 1043 inline bool buffer_overflow() const { 1044 return pc_ >= reloc_info_writer.pos() - kGap; 1045 } 1046 1047 // Get the number of bytes available in the buffer. 1048 inline int available_space() const { return reloc_info_writer.pos() - pc_; } 1049 1050 static bool IsNop(Address addr); 1051 1052 PositionsRecorder* positions_recorder() { return &positions_recorder_; } 1053 1054 int relocation_writer_size() { 1055 return (buffer_ + buffer_size_) - reloc_info_writer.pos(); 1056 } 1057 1058 // Avoid overflows for displacements etc. 1059 static const int kMaximalBufferSize = 512*MB; 1060 1061 byte byte_at(int pos) { return buffer_[pos]; } 1062 void set_byte_at(int pos, byte value) { buffer_[pos] = value; } 1063 1064 // Allocate a constant pool of the correct size for the generated code. 1065 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate); 1066 1067 // Generate the constant pool for the generated code. 1068 void PopulateConstantPool(ConstantPoolArray* constant_pool); 1069 1070 protected: 1071 void emit_sse_operand(XMMRegister reg, const Operand& adr); 1072 void emit_sse_operand(XMMRegister dst, XMMRegister src); 1073 void emit_sse_operand(Register dst, XMMRegister src); 1074 void emit_sse_operand(XMMRegister dst, Register src); 1075 1076 byte* addr_at(int pos) { return buffer_ + pos; } 1077 1078 1079 private: 1080 uint32_t long_at(int pos) { 1081 return *reinterpret_cast<uint32_t*>(addr_at(pos)); 1082 } 1083 void long_at_put(int pos, uint32_t x) { 1084 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x; 1085 } 1086 1087 // code emission 1088 void GrowBuffer(); 1089 inline void emit(uint32_t x); 1090 inline void emit(Handle<Object> handle); 1091 inline void emit(uint32_t x, 1092 RelocInfo::Mode rmode, 1093 TypeFeedbackId id = TypeFeedbackId::None()); 1094 inline void emit(Handle<Code> code, 1095 RelocInfo::Mode rmode, 1096 TypeFeedbackId id = TypeFeedbackId::None()); 1097 inline void emit(const Immediate& x); 1098 inline void emit_w(const Immediate& x); 1099 1100 // Emit the code-object-relative offset of the label's position 1101 inline void emit_code_relative_offset(Label* label); 1102 1103 // instruction generation 1104 void emit_arith_b(int op1, int op2, Register dst, int imm8); 1105 1106 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81) 1107 // with a given destination expression and an immediate operand. It attempts 1108 // to use the shortest encoding possible. 1109 // sel specifies the /n in the modrm byte (see the Intel PRM). 1110 void emit_arith(int sel, Operand dst, const Immediate& x); 1111 1112 void emit_operand(Register reg, const Operand& adr); 1113 1114 void emit_farith(int b1, int b2, int i); 1115 1116 // labels 1117 void print(Label* L); 1118 void bind_to(Label* L, int pos); 1119 1120 // displacements 1121 inline Displacement disp_at(Label* L); 1122 inline void disp_at_put(Label* L, Displacement disp); 1123 inline void emit_disp(Label* L, Displacement::Type type); 1124 inline void emit_near_disp(Label* L); 1125 1126 // record reloc info for current pc_ 1127 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1128 1129 friend class CodePatcher; 1130 friend class EnsureSpace; 1131 1132 // code generation 1133 RelocInfoWriter reloc_info_writer; 1134 1135 PositionsRecorder positions_recorder_; 1136 friend class PositionsRecorder; 1137 }; 1138 1139 1140 // Helper class that ensures that there is enough space for generating 1141 // instructions and relocation information. The constructor makes 1142 // sure that there is enough space and (in debug mode) the destructor 1143 // checks that we did not generate too much. 1144 class EnsureSpace BASE_EMBEDDED { 1145 public: 1146 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) { 1147 if (assembler_->buffer_overflow()) assembler_->GrowBuffer(); 1148 #ifdef DEBUG 1149 space_before_ = assembler_->available_space(); 1150 #endif 1151 } 1152 1153 #ifdef DEBUG 1154 ~EnsureSpace() { 1155 int bytes_generated = space_before_ - assembler_->available_space(); 1156 ASSERT(bytes_generated < assembler_->kGap); 1157 } 1158 #endif 1159 1160 private: 1161 Assembler* assembler_; 1162 #ifdef DEBUG 1163 int space_before_; 1164 #endif 1165 }; 1166 1167 } } // namespace v8::internal 1168 1169 #endif // V8_IA32_ASSEMBLER_IA32_H_ 1170