1 2 // Copyright (c) 1994-2006 Sun Microsystems Inc. 3 // All Rights Reserved. 4 // 5 // Redistribution and use in source and binary forms, with or without 6 // modification, are permitted provided that the following conditions are 7 // met: 8 // 9 // - Redistributions of source code must retain the above copyright notice, 10 // this list of conditions and the following disclaimer. 11 // 12 // - Redistribution in binary form must reproduce the above copyright 13 // notice, this list of conditions and the following disclaimer in the 14 // documentation and/or other materials provided with the distribution. 15 // 16 // - Neither the name of Sun Microsystems or the names of contributors may 17 // be used to endorse or promote products derived from this software without 18 // specific prior written permission. 19 // 20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 21 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 27 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 28 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 29 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 32 // The original source code covered by the above license above has been 33 // modified significantly by Google Inc. 34 // Copyright 2012 the V8 project authors. All rights reserved. 35 36 37 #ifndef V8_MIPS_ASSEMBLER_MIPS_INL_H_ 38 #define V8_MIPS_ASSEMBLER_MIPS_INL_H_ 39 40 #include "src/mips/assembler-mips.h" 41 42 #include "src/cpu.h" 43 #include "src/debug.h" 44 45 46 namespace v8 { 47 namespace internal { 48 49 50 bool CpuFeatures::SupportsCrankshaft() { return IsSupported(FPU); } 51 52 53 // ----------------------------------------------------------------------------- 54 // Operand and MemOperand. 55 56 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) { 57 rm_ = no_reg; 58 imm32_ = immediate; 59 rmode_ = rmode; 60 } 61 62 63 Operand::Operand(const ExternalReference& f) { 64 rm_ = no_reg; 65 imm32_ = reinterpret_cast<int32_t>(f.address()); 66 rmode_ = RelocInfo::EXTERNAL_REFERENCE; 67 } 68 69 70 Operand::Operand(Smi* value) { 71 rm_ = no_reg; 72 imm32_ = reinterpret_cast<intptr_t>(value); 73 rmode_ = RelocInfo::NONE32; 74 } 75 76 77 Operand::Operand(Register rm) { 78 rm_ = rm; 79 } 80 81 82 bool Operand::is_reg() const { 83 return rm_.is_valid(); 84 } 85 86 87 int Register::NumAllocatableRegisters() { 88 return kMaxNumAllocatableRegisters; 89 } 90 91 92 int DoubleRegister::NumRegisters() { 93 return FPURegister::kMaxNumRegisters; 94 } 95 96 97 int DoubleRegister::NumAllocatableRegisters() { 98 return FPURegister::kMaxNumAllocatableRegisters; 99 } 100 101 102 int FPURegister::ToAllocationIndex(FPURegister reg) { 103 ASSERT(reg.code() % 2 == 0); 104 ASSERT(reg.code() / 2 < kMaxNumAllocatableRegisters); 105 ASSERT(reg.is_valid()); 106 ASSERT(!reg.is(kDoubleRegZero)); 107 ASSERT(!reg.is(kLithiumScratchDouble)); 108 return (reg.code() / 2); 109 } 110 111 112 // ----------------------------------------------------------------------------- 113 // RelocInfo. 114 115 void RelocInfo::apply(intptr_t delta, ICacheFlushMode icache_flush_mode) { 116 if (IsCodeTarget(rmode_)) { 117 uint32_t scope1 = (uint32_t) target_address() & ~kImm28Mask; 118 uint32_t scope2 = reinterpret_cast<uint32_t>(pc_) & ~kImm28Mask; 119 120 if (scope1 != scope2) { 121 Assembler::JumpLabelToJumpRegister(pc_); 122 } 123 } 124 if (IsInternalReference(rmode_)) { 125 // Absolute code pointer inside code object moves with the code object. 126 byte* p = reinterpret_cast<byte*>(pc_); 127 int count = Assembler::RelocateInternalReference(p, delta); 128 CPU::FlushICache(p, count * sizeof(uint32_t)); 129 } 130 } 131 132 133 Address RelocInfo::target_address() { 134 ASSERT(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_)); 135 return Assembler::target_address_at(pc_, host_); 136 } 137 138 139 Address RelocInfo::target_address_address() { 140 ASSERT(IsCodeTarget(rmode_) || 141 IsRuntimeEntry(rmode_) || 142 rmode_ == EMBEDDED_OBJECT || 143 rmode_ == EXTERNAL_REFERENCE); 144 // Read the address of the word containing the target_address in an 145 // instruction stream. 146 // The only architecture-independent user of this function is the serializer. 147 // The serializer uses it to find out how many raw bytes of instruction to 148 // output before the next target. 149 // For an instruction like LUI/ORI where the target bits are mixed into the 150 // instruction bits, the size of the target will be zero, indicating that the 151 // serializer should not step forward in memory after a target is resolved 152 // and written. In this case the target_address_address function should 153 // return the end of the instructions to be patched, allowing the 154 // deserializer to deserialize the instructions as raw bytes and put them in 155 // place, ready to be patched with the target. After jump optimization, 156 // that is the address of the instruction that follows J/JAL/JR/JALR 157 // instruction. 158 return reinterpret_cast<Address>( 159 pc_ + Assembler::kInstructionsFor32BitConstant * Assembler::kInstrSize); 160 } 161 162 163 Address RelocInfo::constant_pool_entry_address() { 164 UNREACHABLE(); 165 return NULL; 166 } 167 168 169 int RelocInfo::target_address_size() { 170 return Assembler::kSpecialTargetSize; 171 } 172 173 174 void RelocInfo::set_target_address(Address target, 175 WriteBarrierMode write_barrier_mode, 176 ICacheFlushMode icache_flush_mode) { 177 ASSERT(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_)); 178 Assembler::set_target_address_at(pc_, host_, target, icache_flush_mode); 179 if (write_barrier_mode == UPDATE_WRITE_BARRIER && 180 host() != NULL && IsCodeTarget(rmode_)) { 181 Object* target_code = Code::GetCodeFromTargetAddress(target); 182 host()->GetHeap()->incremental_marking()->RecordWriteIntoCode( 183 host(), this, HeapObject::cast(target_code)); 184 } 185 } 186 187 188 Address Assembler::target_address_from_return_address(Address pc) { 189 return pc - kCallTargetAddressOffset; 190 } 191 192 193 Object* RelocInfo::target_object() { 194 ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); 195 return reinterpret_cast<Object*>(Assembler::target_address_at(pc_, host_)); 196 } 197 198 199 Handle<Object> RelocInfo::target_object_handle(Assembler* origin) { 200 ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); 201 return Handle<Object>(reinterpret_cast<Object**>( 202 Assembler::target_address_at(pc_, host_))); 203 } 204 205 206 void RelocInfo::set_target_object(Object* target, 207 WriteBarrierMode write_barrier_mode, 208 ICacheFlushMode icache_flush_mode) { 209 ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); 210 ASSERT(!target->IsConsString()); 211 Assembler::set_target_address_at(pc_, host_, 212 reinterpret_cast<Address>(target), 213 icache_flush_mode); 214 if (write_barrier_mode == UPDATE_WRITE_BARRIER && 215 host() != NULL && 216 target->IsHeapObject()) { 217 host()->GetHeap()->incremental_marking()->RecordWrite( 218 host(), &Memory::Object_at(pc_), HeapObject::cast(target)); 219 } 220 } 221 222 223 Address RelocInfo::target_reference() { 224 ASSERT(rmode_ == EXTERNAL_REFERENCE); 225 return Assembler::target_address_at(pc_, host_); 226 } 227 228 229 Address RelocInfo::target_runtime_entry(Assembler* origin) { 230 ASSERT(IsRuntimeEntry(rmode_)); 231 return target_address(); 232 } 233 234 235 void RelocInfo::set_target_runtime_entry(Address target, 236 WriteBarrierMode write_barrier_mode, 237 ICacheFlushMode icache_flush_mode) { 238 ASSERT(IsRuntimeEntry(rmode_)); 239 if (target_address() != target) 240 set_target_address(target, write_barrier_mode, icache_flush_mode); 241 } 242 243 244 Handle<Cell> RelocInfo::target_cell_handle() { 245 ASSERT(rmode_ == RelocInfo::CELL); 246 Address address = Memory::Address_at(pc_); 247 return Handle<Cell>(reinterpret_cast<Cell**>(address)); 248 } 249 250 251 Cell* RelocInfo::target_cell() { 252 ASSERT(rmode_ == RelocInfo::CELL); 253 return Cell::FromValueAddress(Memory::Address_at(pc_)); 254 } 255 256 257 void RelocInfo::set_target_cell(Cell* cell, 258 WriteBarrierMode write_barrier_mode, 259 ICacheFlushMode icache_flush_mode) { 260 ASSERT(rmode_ == RelocInfo::CELL); 261 Address address = cell->address() + Cell::kValueOffset; 262 Memory::Address_at(pc_) = address; 263 if (write_barrier_mode == UPDATE_WRITE_BARRIER && host() != NULL) { 264 // TODO(1550) We are passing NULL as a slot because cell can never be on 265 // evacuation candidate. 266 host()->GetHeap()->incremental_marking()->RecordWrite( 267 host(), NULL, cell); 268 } 269 } 270 271 272 static const int kNoCodeAgeSequenceLength = 7 * Assembler::kInstrSize; 273 274 275 Handle<Object> RelocInfo::code_age_stub_handle(Assembler* origin) { 276 UNREACHABLE(); // This should never be reached on Arm. 277 return Handle<Object>(); 278 } 279 280 281 Code* RelocInfo::code_age_stub() { 282 ASSERT(rmode_ == RelocInfo::CODE_AGE_SEQUENCE); 283 return Code::GetCodeFromTargetAddress( 284 Assembler::target_address_at(pc_ + Assembler::kInstrSize, host_)); 285 } 286 287 288 void RelocInfo::set_code_age_stub(Code* stub, 289 ICacheFlushMode icache_flush_mode) { 290 ASSERT(rmode_ == RelocInfo::CODE_AGE_SEQUENCE); 291 Assembler::set_target_address_at(pc_ + Assembler::kInstrSize, 292 host_, 293 stub->instruction_start()); 294 } 295 296 297 Address RelocInfo::call_address() { 298 ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || 299 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); 300 // The pc_ offset of 0 assumes mips patched return sequence per 301 // debug-mips.cc BreakLocationIterator::SetDebugBreakAtReturn(), or 302 // debug break slot per BreakLocationIterator::SetDebugBreakAtSlot(). 303 return Assembler::target_address_at(pc_, host_); 304 } 305 306 307 void RelocInfo::set_call_address(Address target) { 308 ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || 309 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); 310 // The pc_ offset of 0 assumes mips patched return sequence per 311 // debug-mips.cc BreakLocationIterator::SetDebugBreakAtReturn(), or 312 // debug break slot per BreakLocationIterator::SetDebugBreakAtSlot(). 313 Assembler::set_target_address_at(pc_, host_, target); 314 if (host() != NULL) { 315 Object* target_code = Code::GetCodeFromTargetAddress(target); 316 host()->GetHeap()->incremental_marking()->RecordWriteIntoCode( 317 host(), this, HeapObject::cast(target_code)); 318 } 319 } 320 321 322 Object* RelocInfo::call_object() { 323 return *call_object_address(); 324 } 325 326 327 Object** RelocInfo::call_object_address() { 328 ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || 329 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); 330 return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrSize); 331 } 332 333 334 void RelocInfo::set_call_object(Object* target) { 335 *call_object_address() = target; 336 } 337 338 339 void RelocInfo::WipeOut() { 340 ASSERT(IsEmbeddedObject(rmode_) || 341 IsCodeTarget(rmode_) || 342 IsRuntimeEntry(rmode_) || 343 IsExternalReference(rmode_)); 344 Assembler::set_target_address_at(pc_, host_, NULL); 345 } 346 347 348 bool RelocInfo::IsPatchedReturnSequence() { 349 Instr instr0 = Assembler::instr_at(pc_); 350 Instr instr1 = Assembler::instr_at(pc_ + 1 * Assembler::kInstrSize); 351 Instr instr2 = Assembler::instr_at(pc_ + 2 * Assembler::kInstrSize); 352 bool patched_return = ((instr0 & kOpcodeMask) == LUI && 353 (instr1 & kOpcodeMask) == ORI && 354 ((instr2 & kOpcodeMask) == JAL || 355 ((instr2 & kOpcodeMask) == SPECIAL && 356 (instr2 & kFunctionFieldMask) == JALR))); 357 return patched_return; 358 } 359 360 361 bool RelocInfo::IsPatchedDebugBreakSlotSequence() { 362 Instr current_instr = Assembler::instr_at(pc_); 363 return !Assembler::IsNop(current_instr, Assembler::DEBUG_BREAK_NOP); 364 } 365 366 367 void RelocInfo::Visit(Isolate* isolate, ObjectVisitor* visitor) { 368 RelocInfo::Mode mode = rmode(); 369 if (mode == RelocInfo::EMBEDDED_OBJECT) { 370 visitor->VisitEmbeddedPointer(this); 371 } else if (RelocInfo::IsCodeTarget(mode)) { 372 visitor->VisitCodeTarget(this); 373 } else if (mode == RelocInfo::CELL) { 374 visitor->VisitCell(this); 375 } else if (mode == RelocInfo::EXTERNAL_REFERENCE) { 376 visitor->VisitExternalReference(this); 377 } else if (RelocInfo::IsCodeAgeSequence(mode)) { 378 visitor->VisitCodeAgeSequence(this); 379 } else if (((RelocInfo::IsJSReturn(mode) && 380 IsPatchedReturnSequence()) || 381 (RelocInfo::IsDebugBreakSlot(mode) && 382 IsPatchedDebugBreakSlotSequence())) && 383 isolate->debug()->has_break_points()) { 384 visitor->VisitDebugTarget(this); 385 } else if (RelocInfo::IsRuntimeEntry(mode)) { 386 visitor->VisitRuntimeEntry(this); 387 } 388 } 389 390 391 template<typename StaticVisitor> 392 void RelocInfo::Visit(Heap* heap) { 393 RelocInfo::Mode mode = rmode(); 394 if (mode == RelocInfo::EMBEDDED_OBJECT) { 395 StaticVisitor::VisitEmbeddedPointer(heap, this); 396 } else if (RelocInfo::IsCodeTarget(mode)) { 397 StaticVisitor::VisitCodeTarget(heap, this); 398 } else if (mode == RelocInfo::CELL) { 399 StaticVisitor::VisitCell(heap, this); 400 } else if (mode == RelocInfo::EXTERNAL_REFERENCE) { 401 StaticVisitor::VisitExternalReference(this); 402 } else if (RelocInfo::IsCodeAgeSequence(mode)) { 403 StaticVisitor::VisitCodeAgeSequence(heap, this); 404 } else if (heap->isolate()->debug()->has_break_points() && 405 ((RelocInfo::IsJSReturn(mode) && 406 IsPatchedReturnSequence()) || 407 (RelocInfo::IsDebugBreakSlot(mode) && 408 IsPatchedDebugBreakSlotSequence()))) { 409 StaticVisitor::VisitDebugTarget(heap, this); 410 } else if (RelocInfo::IsRuntimeEntry(mode)) { 411 StaticVisitor::VisitRuntimeEntry(this); 412 } 413 } 414 415 416 // ----------------------------------------------------------------------------- 417 // Assembler. 418 419 420 void Assembler::CheckBuffer() { 421 if (buffer_space() <= kGap) { 422 GrowBuffer(); 423 } 424 } 425 426 427 void Assembler::CheckTrampolinePoolQuick() { 428 if (pc_offset() >= next_buffer_check_) { 429 CheckTrampolinePool(); 430 } 431 } 432 433 434 void Assembler::emit(Instr x) { 435 if (!is_buffer_growth_blocked()) { 436 CheckBuffer(); 437 } 438 *reinterpret_cast<Instr*>(pc_) = x; 439 pc_ += kInstrSize; 440 CheckTrampolinePoolQuick(); 441 } 442 443 444 } } // namespace v8::internal 445 446 #endif // V8_MIPS_ASSEMBLER_MIPS_INL_H_ 447