1 /* 2 * Performance events: 3 * 4 * Copyright (C) 2008-2009, Thomas Gleixner <tglx (at) linutronix.de> 5 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 7 * 8 * Data type definitions, declarations, prototypes. 9 * 10 * Started by: Thomas Gleixner and Ingo Molnar 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 #ifndef _UAPI_LINUX_PERF_EVENT_H 15 #define _UAPI_LINUX_PERF_EVENT_H 16 17 #include <linux/types.h> 18 #include <linux/ioctl.h> 19 #include <asm/byteorder.h> 20 21 /* 22 * User-space ABI bits: 23 */ 24 25 /* 26 * attr.type 27 */ 28 enum perf_type_id { 29 PERF_TYPE_HARDWARE = 0, 30 PERF_TYPE_SOFTWARE = 1, 31 PERF_TYPE_TRACEPOINT = 2, 32 PERF_TYPE_HW_CACHE = 3, 33 PERF_TYPE_RAW = 4, 34 PERF_TYPE_BREAKPOINT = 5, 35 36 PERF_TYPE_MAX, /* non-ABI */ 37 }; 38 39 /* 40 * Generalized performance event event_id types, used by the 41 * attr.event_id parameter of the sys_perf_event_open() 42 * syscall: 43 */ 44 enum perf_hw_id { 45 /* 46 * Common hardware events, generalized by the kernel: 47 */ 48 PERF_COUNT_HW_CPU_CYCLES = 0, 49 PERF_COUNT_HW_INSTRUCTIONS = 1, 50 PERF_COUNT_HW_CACHE_REFERENCES = 2, 51 PERF_COUNT_HW_CACHE_MISSES = 3, 52 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 53 PERF_COUNT_HW_BRANCH_MISSES = 5, 54 PERF_COUNT_HW_BUS_CYCLES = 6, 55 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 56 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 57 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 58 59 PERF_COUNT_HW_MAX, /* non-ABI */ 60 }; 61 62 /* 63 * Generalized hardware cache events: 64 * 65 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 66 * { read, write, prefetch } x 67 * { accesses, misses } 68 */ 69 enum perf_hw_cache_id { 70 PERF_COUNT_HW_CACHE_L1D = 0, 71 PERF_COUNT_HW_CACHE_L1I = 1, 72 PERF_COUNT_HW_CACHE_LL = 2, 73 PERF_COUNT_HW_CACHE_DTLB = 3, 74 PERF_COUNT_HW_CACHE_ITLB = 4, 75 PERF_COUNT_HW_CACHE_BPU = 5, 76 PERF_COUNT_HW_CACHE_NODE = 6, 77 78 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 79 }; 80 81 enum perf_hw_cache_op_id { 82 PERF_COUNT_HW_CACHE_OP_READ = 0, 83 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 84 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 85 86 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 87 }; 88 89 enum perf_hw_cache_op_result_id { 90 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 91 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 92 93 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 94 }; 95 96 /* 97 * Special "software" events provided by the kernel, even if the hardware 98 * does not support performance events. These events measure various 99 * physical and sw events of the kernel (and allow the profiling of them as 100 * well): 101 */ 102 enum perf_sw_ids { 103 PERF_COUNT_SW_CPU_CLOCK = 0, 104 PERF_COUNT_SW_TASK_CLOCK = 1, 105 PERF_COUNT_SW_PAGE_FAULTS = 2, 106 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 107 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 108 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 109 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 110 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 111 PERF_COUNT_SW_EMULATION_FAULTS = 8, 112 PERF_COUNT_SW_DUMMY = 9, 113 114 PERF_COUNT_SW_MAX, /* non-ABI */ 115 }; 116 117 /* 118 * Bits that can be set in attr.sample_type to request information 119 * in the overflow packets. 120 */ 121 enum perf_event_sample_format { 122 PERF_SAMPLE_IP = 1U << 0, 123 PERF_SAMPLE_TID = 1U << 1, 124 PERF_SAMPLE_TIME = 1U << 2, 125 PERF_SAMPLE_ADDR = 1U << 3, 126 PERF_SAMPLE_READ = 1U << 4, 127 PERF_SAMPLE_CALLCHAIN = 1U << 5, 128 PERF_SAMPLE_ID = 1U << 6, 129 PERF_SAMPLE_CPU = 1U << 7, 130 PERF_SAMPLE_PERIOD = 1U << 8, 131 PERF_SAMPLE_STREAM_ID = 1U << 9, 132 PERF_SAMPLE_RAW = 1U << 10, 133 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 134 PERF_SAMPLE_REGS_USER = 1U << 12, 135 PERF_SAMPLE_STACK_USER = 1U << 13, 136 PERF_SAMPLE_WEIGHT = 1U << 14, 137 PERF_SAMPLE_DATA_SRC = 1U << 15, 138 PERF_SAMPLE_IDENTIFIER = 1U << 16, 139 140 PERF_SAMPLE_MAX = 1U << 17, /* non-ABI */ 141 }; 142 143 /* 144 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 145 * 146 * If the user does not pass priv level information via branch_sample_type, 147 * the kernel uses the event's priv level. Branch and event priv levels do 148 * not have to match. Branch priv level is checked for permissions. 149 * 150 * The branch types can be combined, however BRANCH_ANY covers all types 151 * of branches and therefore it supersedes all the other types. 152 */ 153 enum perf_branch_sample_type { 154 PERF_SAMPLE_BRANCH_USER = 1U << 0, /* user branches */ 155 PERF_SAMPLE_BRANCH_KERNEL = 1U << 1, /* kernel branches */ 156 PERF_SAMPLE_BRANCH_HV = 1U << 2, /* hypervisor branches */ 157 158 PERF_SAMPLE_BRANCH_ANY = 1U << 3, /* any branch types */ 159 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << 4, /* any call branch */ 160 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << 5, /* any return branch */ 161 PERF_SAMPLE_BRANCH_IND_CALL = 1U << 6, /* indirect calls */ 162 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << 7, /* transaction aborts */ 163 PERF_SAMPLE_BRANCH_IN_TX = 1U << 8, /* in transaction */ 164 PERF_SAMPLE_BRANCH_NO_TX = 1U << 9, /* not in transaction */ 165 166 PERF_SAMPLE_BRANCH_MAX = 1U << 10, /* non-ABI */ 167 }; 168 169 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 170 (PERF_SAMPLE_BRANCH_USER|\ 171 PERF_SAMPLE_BRANCH_KERNEL|\ 172 PERF_SAMPLE_BRANCH_HV) 173 174 /* 175 * Values to determine ABI of the registers dump. 176 */ 177 enum perf_sample_regs_abi { 178 PERF_SAMPLE_REGS_ABI_NONE = 0, 179 PERF_SAMPLE_REGS_ABI_32 = 1, 180 PERF_SAMPLE_REGS_ABI_64 = 2, 181 }; 182 183 /* 184 * The format of the data returned by read() on a perf event fd, 185 * as specified by attr.read_format: 186 * 187 * struct read_format { 188 * { u64 value; 189 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 190 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 191 * { u64 id; } && PERF_FORMAT_ID 192 * } && !PERF_FORMAT_GROUP 193 * 194 * { u64 nr; 195 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 196 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 197 * { u64 value; 198 * { u64 id; } && PERF_FORMAT_ID 199 * } cntr[nr]; 200 * } && PERF_FORMAT_GROUP 201 * }; 202 */ 203 enum perf_event_read_format { 204 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 205 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 206 PERF_FORMAT_ID = 1U << 2, 207 PERF_FORMAT_GROUP = 1U << 3, 208 209 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ 210 }; 211 212 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 213 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 214 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 215 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 216 /* add: sample_stack_user */ 217 218 /* 219 * Hardware event_id to monitor via a performance monitoring event: 220 */ 221 struct perf_event_attr { 222 223 /* 224 * Major type: hardware/software/tracepoint/etc. 225 */ 226 __u32 type; 227 228 /* 229 * Size of the attr structure, for fwd/bwd compat. 230 */ 231 __u32 size; 232 233 /* 234 * Type specific configuration information. 235 */ 236 __u64 config; 237 238 union { 239 __u64 sample_period; 240 __u64 sample_freq; 241 }; 242 243 __u64 sample_type; 244 __u64 read_format; 245 246 __u64 disabled : 1, /* off by default */ 247 inherit : 1, /* children inherit it */ 248 pinned : 1, /* must always be on PMU */ 249 exclusive : 1, /* only group on PMU */ 250 exclude_user : 1, /* don't count user */ 251 exclude_kernel : 1, /* ditto kernel */ 252 exclude_hv : 1, /* ditto hypervisor */ 253 exclude_idle : 1, /* don't count when idle */ 254 mmap : 1, /* include mmap data */ 255 comm : 1, /* include comm data */ 256 freq : 1, /* use freq, not period */ 257 inherit_stat : 1, /* per task counts */ 258 enable_on_exec : 1, /* next exec enables */ 259 task : 1, /* trace fork/exit */ 260 watermark : 1, /* wakeup_watermark */ 261 /* 262 * precise_ip: 263 * 264 * 0 - SAMPLE_IP can have arbitrary skid 265 * 1 - SAMPLE_IP must have constant skid 266 * 2 - SAMPLE_IP requested to have 0 skid 267 * 3 - SAMPLE_IP must have 0 skid 268 * 269 * See also PERF_RECORD_MISC_EXACT_IP 270 */ 271 precise_ip : 2, /* skid constraint */ 272 mmap_data : 1, /* non-exec mmap data */ 273 sample_id_all : 1, /* sample_type all events */ 274 275 exclude_host : 1, /* don't count in host */ 276 exclude_guest : 1, /* don't count in guest */ 277 278 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 279 exclude_callchain_user : 1, /* exclude user callchains */ 280 mmap2 : 1, /* include mmap with inode data */ 281 282 __reserved_1 : 40; 283 284 union { 285 __u32 wakeup_events; /* wakeup every n events */ 286 __u32 wakeup_watermark; /* bytes before wakeup */ 287 }; 288 289 __u32 bp_type; 290 union { 291 __u64 bp_addr; 292 __u64 config1; /* extension of config */ 293 }; 294 union { 295 __u64 bp_len; 296 __u64 config2; /* extension of config1 */ 297 }; 298 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 299 300 /* 301 * Defines set of user regs to dump on samples. 302 * See asm/perf_regs.h for details. 303 */ 304 __u64 sample_regs_user; 305 306 /* 307 * Defines size of the user stack to dump on samples. 308 */ 309 __u32 sample_stack_user; 310 311 /* Align to u64. */ 312 __u32 __reserved_2; 313 }; 314 315 #define perf_flags(attr) (*(&(attr)->read_format + 1)) 316 317 /* 318 * Ioctls that can be done on a perf event fd: 319 */ 320 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 321 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 322 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 323 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 324 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 325 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 326 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 327 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 328 329 enum perf_event_ioc_flags { 330 PERF_IOC_FLAG_GROUP = 1U << 0, 331 }; 332 333 /* 334 * Structure of the page that can be mapped via mmap 335 */ 336 struct perf_event_mmap_page { 337 __u32 version; /* version number of this structure */ 338 __u32 compat_version; /* lowest version this is compat with */ 339 340 /* 341 * Bits needed to read the hw events in user-space. 342 * 343 * u32 seq, time_mult, time_shift, idx, width; 344 * u64 count, enabled, running; 345 * u64 cyc, time_offset; 346 * s64 pmc = 0; 347 * 348 * do { 349 * seq = pc->lock; 350 * barrier() 351 * 352 * enabled = pc->time_enabled; 353 * running = pc->time_running; 354 * 355 * if (pc->cap_usr_time && enabled != running) { 356 * cyc = rdtsc(); 357 * time_offset = pc->time_offset; 358 * time_mult = pc->time_mult; 359 * time_shift = pc->time_shift; 360 * } 361 * 362 * idx = pc->index; 363 * count = pc->offset; 364 * if (pc->cap_usr_rdpmc && idx) { 365 * width = pc->pmc_width; 366 * pmc = rdpmc(idx - 1); 367 * } 368 * 369 * barrier(); 370 * } while (pc->lock != seq); 371 * 372 * NOTE: for obvious reason this only works on self-monitoring 373 * processes. 374 */ 375 __u32 lock; /* seqlock for synchronization */ 376 __u32 index; /* hardware event identifier */ 377 __s64 offset; /* add to hardware event value */ 378 __u64 time_enabled; /* time event active */ 379 __u64 time_running; /* time event on cpu */ 380 union { 381 __u64 capabilities; 382 struct { 383 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 384 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 385 386 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 387 cap_user_time : 1, /* The time_* fields are used */ 388 cap_user_time_zero : 1, /* The time_zero field is used */ 389 cap_____res : 59; 390 }; 391 }; 392 393 /* 394 * If cap_usr_rdpmc this field provides the bit-width of the value 395 * read using the rdpmc() or equivalent instruction. This can be used 396 * to sign extend the result like: 397 * 398 * pmc <<= 64 - width; 399 * pmc >>= 64 - width; // signed shift right 400 * count += pmc; 401 */ 402 __u16 pmc_width; 403 404 /* 405 * If cap_usr_time the below fields can be used to compute the time 406 * delta since time_enabled (in ns) using rdtsc or similar. 407 * 408 * u64 quot, rem; 409 * u64 delta; 410 * 411 * quot = (cyc >> time_shift); 412 * rem = cyc & ((1 << time_shift) - 1); 413 * delta = time_offset + quot * time_mult + 414 * ((rem * time_mult) >> time_shift); 415 * 416 * Where time_offset,time_mult,time_shift and cyc are read in the 417 * seqcount loop described above. This delta can then be added to 418 * enabled and possible running (if idx), improving the scaling: 419 * 420 * enabled += delta; 421 * if (idx) 422 * running += delta; 423 * 424 * quot = count / running; 425 * rem = count % running; 426 * count = quot * enabled + (rem * enabled) / running; 427 */ 428 __u16 time_shift; 429 __u32 time_mult; 430 __u64 time_offset; 431 /* 432 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 433 * from sample timestamps. 434 * 435 * time = timestamp - time_zero; 436 * quot = time / time_mult; 437 * rem = time % time_mult; 438 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 439 * 440 * And vice versa: 441 * 442 * quot = cyc >> time_shift; 443 * rem = cyc & ((1 << time_shift) - 1); 444 * timestamp = time_zero + quot * time_mult + 445 * ((rem * time_mult) >> time_shift); 446 */ 447 __u64 time_zero; 448 __u32 size; /* Header size up to __reserved[] fields. */ 449 450 /* 451 * Hole for extension of the self monitor capabilities 452 */ 453 454 __u8 __reserved[118*8+4]; /* align to 1k. */ 455 456 /* 457 * Control data for the mmap() data buffer. 458 * 459 * User-space reading the @data_head value should issue an smp_rmb(), 460 * after reading this value. 461 * 462 * When the mapping is PROT_WRITE the @data_tail value should be 463 * written by userspace to reflect the last read data, after issueing 464 * an smp_mb() to separate the data read from the ->data_tail store. 465 * In this case the kernel will not over-write unread data. 466 * 467 * See perf_output_put_handle() for the data ordering. 468 */ 469 __u64 data_head; /* head in the data section */ 470 __u64 data_tail; /* user-space written tail */ 471 }; 472 473 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 474 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 475 #define PERF_RECORD_MISC_KERNEL (1 << 0) 476 #define PERF_RECORD_MISC_USER (2 << 0) 477 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 478 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 479 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 480 481 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 482 /* 483 * Indicates that the content of PERF_SAMPLE_IP points to 484 * the actual instruction that triggered the event. See also 485 * perf_event_attr::precise_ip. 486 */ 487 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 488 /* 489 * Reserve the last bit to indicate some extended misc field 490 */ 491 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 492 493 struct perf_event_header { 494 __u32 type; 495 __u16 misc; 496 __u16 size; 497 }; 498 499 enum perf_event_type { 500 501 /* 502 * If perf_event_attr.sample_id_all is set then all event types will 503 * have the sample_type selected fields related to where/when 504 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 505 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 506 * just after the perf_event_header and the fields already present for 507 * the existing fields, i.e. at the end of the payload. That way a newer 508 * perf.data file will be supported by older perf tools, with these new 509 * optional fields being ignored. 510 * 511 * struct sample_id { 512 * { u32 pid, tid; } && PERF_SAMPLE_TID 513 * { u64 time; } && PERF_SAMPLE_TIME 514 * { u64 id; } && PERF_SAMPLE_ID 515 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 516 * { u32 cpu, res; } && PERF_SAMPLE_CPU 517 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 518 * } && perf_event_attr::sample_id_all 519 * 520 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 521 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 522 * relative to header.size. 523 */ 524 525 /* 526 * The MMAP events record the PROT_EXEC mappings so that we can 527 * correlate userspace IPs to code. They have the following structure: 528 * 529 * struct { 530 * struct perf_event_header header; 531 * 532 * u32 pid, tid; 533 * u64 addr; 534 * u64 len; 535 * u64 pgoff; 536 * char filename[]; 537 * struct sample_id sample_id; 538 * }; 539 */ 540 PERF_RECORD_MMAP = 1, 541 542 /* 543 * struct { 544 * struct perf_event_header header; 545 * u64 id; 546 * u64 lost; 547 * struct sample_id sample_id; 548 * }; 549 */ 550 PERF_RECORD_LOST = 2, 551 552 /* 553 * struct { 554 * struct perf_event_header header; 555 * 556 * u32 pid, tid; 557 * char comm[]; 558 * struct sample_id sample_id; 559 * }; 560 */ 561 PERF_RECORD_COMM = 3, 562 563 /* 564 * struct { 565 * struct perf_event_header header; 566 * u32 pid, ppid; 567 * u32 tid, ptid; 568 * u64 time; 569 * struct sample_id sample_id; 570 * }; 571 */ 572 PERF_RECORD_EXIT = 4, 573 574 /* 575 * struct { 576 * struct perf_event_header header; 577 * u64 time; 578 * u64 id; 579 * u64 stream_id; 580 * struct sample_id sample_id; 581 * }; 582 */ 583 PERF_RECORD_THROTTLE = 5, 584 PERF_RECORD_UNTHROTTLE = 6, 585 586 /* 587 * struct { 588 * struct perf_event_header header; 589 * u32 pid, ppid; 590 * u32 tid, ptid; 591 * u64 time; 592 * struct sample_id sample_id; 593 * }; 594 */ 595 PERF_RECORD_FORK = 7, 596 597 /* 598 * struct { 599 * struct perf_event_header header; 600 * u32 pid, tid; 601 * 602 * struct read_format values; 603 * struct sample_id sample_id; 604 * }; 605 */ 606 PERF_RECORD_READ = 8, 607 608 /* 609 * struct { 610 * struct perf_event_header header; 611 * 612 * # 613 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 614 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 615 * # is fixed relative to header. 616 * # 617 * 618 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 619 * { u64 ip; } && PERF_SAMPLE_IP 620 * { u32 pid, tid; } && PERF_SAMPLE_TID 621 * { u64 time; } && PERF_SAMPLE_TIME 622 * { u64 addr; } && PERF_SAMPLE_ADDR 623 * { u64 id; } && PERF_SAMPLE_ID 624 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 625 * { u32 cpu, res; } && PERF_SAMPLE_CPU 626 * { u64 period; } && PERF_SAMPLE_PERIOD 627 * 628 * { struct read_format values; } && PERF_SAMPLE_READ 629 * 630 * { u64 nr, 631 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 632 * 633 * # 634 * # The RAW record below is opaque data wrt the ABI 635 * # 636 * # That is, the ABI doesn't make any promises wrt to 637 * # the stability of its content, it may vary depending 638 * # on event, hardware, kernel version and phase of 639 * # the moon. 640 * # 641 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 642 * # 643 * 644 * { u32 size; 645 * char data[size];}&& PERF_SAMPLE_RAW 646 * 647 * { u64 nr; 648 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK 649 * 650 * { u64 abi; # enum perf_sample_regs_abi 651 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 652 * 653 * { u64 size; 654 * char data[size]; 655 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 656 * 657 * { u64 weight; } && PERF_SAMPLE_WEIGHT 658 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 659 * }; 660 */ 661 PERF_RECORD_SAMPLE = 9, 662 663 /* 664 * The MMAP2 records are an augmented version of MMAP, they add 665 * maj, min, ino numbers to be used to uniquely identify each mapping 666 * 667 * struct { 668 * struct perf_event_header header; 669 * 670 * u32 pid, tid; 671 * u64 addr; 672 * u64 len; 673 * u64 pgoff; 674 * u32 maj; 675 * u32 min; 676 * u64 ino; 677 * u64 ino_generation; 678 * char filename[]; 679 * struct sample_id sample_id; 680 * }; 681 */ 682 PERF_RECORD_MMAP2 = 10, 683 684 PERF_RECORD_MAX, /* non-ABI */ 685 }; 686 687 #define PERF_MAX_STACK_DEPTH 127 688 689 enum perf_callchain_context { 690 PERF_CONTEXT_HV = (__u64)-32, 691 PERF_CONTEXT_KERNEL = (__u64)-128, 692 PERF_CONTEXT_USER = (__u64)-512, 693 694 PERF_CONTEXT_GUEST = (__u64)-2048, 695 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 696 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 697 698 PERF_CONTEXT_MAX = (__u64)-4095, 699 }; 700 701 #define PERF_FLAG_FD_NO_GROUP (1U << 0) 702 #define PERF_FLAG_FD_OUTPUT (1U << 1) 703 #define PERF_FLAG_PID_CGROUP (1U << 2) /* pid=cgroup id, per-cpu mode only */ 704 705 union perf_mem_data_src { 706 __u64 val; 707 struct { 708 __u64 mem_op:5, /* type of opcode */ 709 mem_lvl:14, /* memory hierarchy level */ 710 mem_snoop:5, /* snoop mode */ 711 mem_lock:2, /* lock instr */ 712 mem_dtlb:7, /* tlb access */ 713 mem_rsvd:31; 714 }; 715 }; 716 717 /* type of opcode (load/store/prefetch,code) */ 718 #define PERF_MEM_OP_NA 0x01 /* not available */ 719 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 720 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 721 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 722 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 723 #define PERF_MEM_OP_SHIFT 0 724 725 /* memory hierarchy (memory level, hit or miss) */ 726 #define PERF_MEM_LVL_NA 0x01 /* not available */ 727 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 728 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 729 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 730 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 731 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 732 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 733 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 734 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 735 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 736 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 737 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 738 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 739 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 740 #define PERF_MEM_LVL_SHIFT 5 741 742 /* snoop mode */ 743 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 744 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 745 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 746 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 747 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 748 #define PERF_MEM_SNOOP_SHIFT 19 749 750 /* locked instruction */ 751 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 752 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 753 #define PERF_MEM_LOCK_SHIFT 24 754 755 /* TLB access */ 756 #define PERF_MEM_TLB_NA 0x01 /* not available */ 757 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 758 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 759 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 760 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 761 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 762 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 763 #define PERF_MEM_TLB_SHIFT 26 764 765 #define PERF_MEM_S(a, s) \ 766 (((u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 767 768 /* 769 * single taken branch record layout: 770 * 771 * from: source instruction (may not always be a branch insn) 772 * to: branch target 773 * mispred: branch target was mispredicted 774 * predicted: branch target was predicted 775 * 776 * support for mispred, predicted is optional. In case it 777 * is not supported mispred = predicted = 0. 778 * 779 * in_tx: running in a hardware transaction 780 * abort: aborting a hardware transaction 781 */ 782 struct perf_branch_entry { 783 __u64 from; 784 __u64 to; 785 __u64 mispred:1, /* target mispredicted */ 786 predicted:1,/* target predicted */ 787 in_tx:1, /* in transaction */ 788 abort:1, /* transaction abort */ 789 reserved:60; 790 }; 791 792 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 793
