1 //===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 def HasMSA : Predicate<"Subtarget->hasMSA()">, 11 AssemblerPredicate<"FeatureMSA">; 12 13 class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { 14 let Predicates = [HasMSA]; 15 let Inst{31-26} = 0b011110; 16 } 17 18 class MSA64Inst : MSAInst { 19 let Predicates = [HasMSA, HasMips64]; 20 } 21 22 class MSACBranch : MSAInst { 23 let Inst{31-26} = 0b010001; 24 } 25 26 class MSASpecial : MSAInst { 27 let Inst{31-26} = 0b000000; 28 } 29 30 class MSA64Special : MSA64Inst { 31 let Inst{31-26} = 0b000000; 32 } 33 34 class MSAPseudo<dag outs, dag ins, list<dag> pattern, 35 InstrItinClass itin = IIPseudo>: 36 MipsPseudo<outs, ins, pattern, itin> { 37 let Predicates = [HasMSA]; 38 } 39 40 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst { 41 bits<5> ws; 42 bits<5> wd; 43 bits<3> m; 44 45 let Inst{25-23} = major; 46 let Inst{22-19} = 0b1110; 47 let Inst{18-16} = m; 48 let Inst{15-11} = ws; 49 let Inst{10-6} = wd; 50 let Inst{5-0} = minor; 51 } 52 53 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst { 54 bits<5> ws; 55 bits<5> wd; 56 bits<4> m; 57 58 let Inst{25-23} = major; 59 let Inst{22-20} = 0b110; 60 let Inst{19-16} = m; 61 let Inst{15-11} = ws; 62 let Inst{10-6} = wd; 63 let Inst{5-0} = minor; 64 } 65 66 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst { 67 bits<5> ws; 68 bits<5> wd; 69 bits<5> m; 70 71 let Inst{25-23} = major; 72 let Inst{22-21} = 0b10; 73 let Inst{20-16} = m; 74 let Inst{15-11} = ws; 75 let Inst{10-6} = wd; 76 let Inst{5-0} = minor; 77 } 78 79 class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst { 80 bits<5> ws; 81 bits<5> wd; 82 bits<6> m; 83 84 let Inst{25-23} = major; 85 let Inst{22} = 0b0; 86 let Inst{21-16} = m; 87 let Inst{15-11} = ws; 88 let Inst{10-6} = wd; 89 let Inst{5-0} = minor; 90 } 91 92 class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst { 93 bits<5> rs; 94 bits<5> wd; 95 96 let Inst{25-18} = major; 97 let Inst{17-16} = df; 98 let Inst{15-11} = rs; 99 let Inst{10-6} = wd; 100 let Inst{5-0} = minor; 101 } 102 103 class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSA64Inst { 104 bits<5> rs; 105 bits<5> wd; 106 107 let Inst{25-18} = major; 108 let Inst{17-16} = df; 109 let Inst{15-11} = rs; 110 let Inst{10-6} = wd; 111 let Inst{5-0} = minor; 112 } 113 114 class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst { 115 bits<5> ws; 116 bits<5> wd; 117 118 let Inst{25-18} = major; 119 let Inst{17-16} = df; 120 let Inst{15-11} = ws; 121 let Inst{10-6} = wd; 122 let Inst{5-0} = minor; 123 } 124 125 class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst { 126 bits<5> ws; 127 bits<5> wd; 128 129 let Inst{25-17} = major; 130 let Inst{16} = df; 131 let Inst{15-11} = ws; 132 let Inst{10-6} = wd; 133 let Inst{5-0} = minor; 134 } 135 136 class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst { 137 bits<5> wt; 138 bits<5> ws; 139 bits<5> wd; 140 141 let Inst{25-23} = major; 142 let Inst{22-21} = df; 143 let Inst{20-16} = wt; 144 let Inst{15-11} = ws; 145 let Inst{10-6} = wd; 146 let Inst{5-0} = minor; 147 } 148 149 class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst { 150 bits<5> wt; 151 bits<5> ws; 152 bits<5> wd; 153 154 let Inst{25-22} = major; 155 let Inst{21} = df; 156 let Inst{20-16} = wt; 157 let Inst{15-11} = ws; 158 let Inst{10-6} = wd; 159 let Inst{5-0} = minor; 160 } 161 162 class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst { 163 bits<5> rt; 164 bits<5> ws; 165 bits<5> wd; 166 167 let Inst{25-23} = major; 168 let Inst{22-21} = df; 169 let Inst{20-16} = rt; 170 let Inst{15-11} = ws; 171 let Inst{10-6} = wd; 172 let Inst{5-0} = minor; 173 } 174 175 class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst { 176 bits<5> ws; 177 bits<5> wd; 178 179 let Inst{25-16} = major; 180 let Inst{15-11} = ws; 181 let Inst{10-6} = wd; 182 let Inst{5-0} = minor; 183 } 184 185 class MSA_ELM_CFCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst { 186 bits<5> rd; 187 bits<5> cs; 188 189 let Inst{25-16} = major; 190 let Inst{15-11} = cs; 191 let Inst{10-6} = rd; 192 let Inst{5-0} = minor; 193 } 194 195 class MSA_ELM_CTCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst { 196 bits<5> rs; 197 bits<5> cd; 198 199 let Inst{25-16} = major; 200 let Inst{15-11} = rs; 201 let Inst{10-6} = cd; 202 let Inst{5-0} = minor; 203 } 204 205 class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst { 206 bits<4> n; 207 bits<5> ws; 208 bits<5> wd; 209 210 let Inst{25-22} = major; 211 let Inst{21-20} = 0b00; 212 let Inst{19-16} = n{3-0}; 213 let Inst{15-11} = ws; 214 let Inst{10-6} = wd; 215 let Inst{5-0} = minor; 216 } 217 218 class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst { 219 bits<4> n; 220 bits<5> ws; 221 bits<5> wd; 222 223 let Inst{25-22} = major; 224 let Inst{21-19} = 0b100; 225 let Inst{18-16} = n{2-0}; 226 let Inst{15-11} = ws; 227 let Inst{10-6} = wd; 228 let Inst{5-0} = minor; 229 } 230 231 class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst { 232 bits<4> n; 233 bits<5> ws; 234 bits<5> wd; 235 236 let Inst{25-22} = major; 237 let Inst{21-18} = 0b1100; 238 let Inst{17-16} = n{1-0}; 239 let Inst{15-11} = ws; 240 let Inst{10-6} = wd; 241 let Inst{5-0} = minor; 242 } 243 244 class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst { 245 bits<4> n; 246 bits<5> ws; 247 bits<5> wd; 248 249 let Inst{25-22} = major; 250 let Inst{21-17} = 0b11100; 251 let Inst{16} = n{0}; 252 let Inst{15-11} = ws; 253 let Inst{10-6} = wd; 254 let Inst{5-0} = minor; 255 } 256 257 class MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst { 258 bits<4> n; 259 bits<5> ws; 260 bits<5> rd; 261 262 let Inst{25-22} = major; 263 let Inst{21-20} = 0b00; 264 let Inst{19-16} = n{3-0}; 265 let Inst{15-11} = ws; 266 let Inst{10-6} = rd; 267 let Inst{5-0} = minor; 268 } 269 270 class MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst { 271 bits<4> n; 272 bits<5> ws; 273 bits<5> rd; 274 275 let Inst{25-22} = major; 276 let Inst{21-19} = 0b100; 277 let Inst{18-16} = n{2-0}; 278 let Inst{15-11} = ws; 279 let Inst{10-6} = rd; 280 let Inst{5-0} = minor; 281 } 282 283 class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst { 284 bits<4> n; 285 bits<5> ws; 286 bits<5> rd; 287 288 let Inst{25-22} = major; 289 let Inst{21-18} = 0b1100; 290 let Inst{17-16} = n{1-0}; 291 let Inst{15-11} = ws; 292 let Inst{10-6} = rd; 293 let Inst{5-0} = minor; 294 } 295 296 class MSA_ELM_COPY_D_FMT<bits<4> major, bits<6> minor>: MSA64Inst { 297 bits<4> n; 298 bits<5> ws; 299 bits<5> rd; 300 301 let Inst{25-22} = major; 302 let Inst{21-17} = 0b11100; 303 let Inst{16} = n{0}; 304 let Inst{15-11} = ws; 305 let Inst{10-6} = rd; 306 let Inst{5-0} = minor; 307 } 308 309 class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst { 310 bits<6> n; 311 bits<5> rs; 312 bits<5> wd; 313 314 let Inst{25-22} = major; 315 let Inst{21-20} = 0b00; 316 let Inst{19-16} = n{3-0}; 317 let Inst{15-11} = rs; 318 let Inst{10-6} = wd; 319 let Inst{5-0} = minor; 320 } 321 322 class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst { 323 bits<6> n; 324 bits<5> rs; 325 bits<5> wd; 326 327 let Inst{25-22} = major; 328 let Inst{21-19} = 0b100; 329 let Inst{18-16} = n{2-0}; 330 let Inst{15-11} = rs; 331 let Inst{10-6} = wd; 332 let Inst{5-0} = minor; 333 } 334 335 class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst { 336 bits<6> n; 337 bits<5> rs; 338 bits<5> wd; 339 340 let Inst{25-22} = major; 341 let Inst{21-18} = 0b1100; 342 let Inst{17-16} = n{1-0}; 343 let Inst{15-11} = rs; 344 let Inst{10-6} = wd; 345 let Inst{5-0} = minor; 346 } 347 348 class MSA_ELM_INSERT_D_FMT<bits<4> major, bits<6> minor>: MSA64Inst { 349 bits<6> n; 350 bits<5> rs; 351 bits<5> wd; 352 353 let Inst{25-22} = major; 354 let Inst{21-17} = 0b11100; 355 let Inst{16} = n{0}; 356 let Inst{15-11} = rs; 357 let Inst{10-6} = wd; 358 let Inst{5-0} = minor; 359 } 360 361 class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst { 362 bits<5> imm; 363 bits<5> ws; 364 bits<5> wd; 365 366 let Inst{25-23} = major; 367 let Inst{22-21} = df; 368 let Inst{20-16} = imm; 369 let Inst{15-11} = ws; 370 let Inst{10-6} = wd; 371 let Inst{5-0} = minor; 372 } 373 374 class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst { 375 bits<8> u8; 376 bits<5> ws; 377 bits<5> wd; 378 379 let Inst{25-24} = major; 380 let Inst{23-16} = u8; 381 let Inst{15-11} = ws; 382 let Inst{10-6} = wd; 383 let Inst{5-0} = minor; 384 } 385 386 class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst { 387 bits<10> s10; 388 bits<5> wd; 389 390 let Inst{25-23} = major; 391 let Inst{22-21} = df; 392 let Inst{20-11} = s10; 393 let Inst{10-6} = wd; 394 let Inst{5-0} = minor; 395 } 396 397 class MSA_MI10_FMT<bits<2> df, bits<4> minor>: MSAInst { 398 bits<21> addr; 399 bits<5> wd; 400 401 let Inst{25-16} = addr{9-0}; 402 let Inst{15-11} = addr{20-16}; 403 let Inst{10-6} = wd; 404 let Inst{5-2} = minor; 405 let Inst{1-0} = df; 406 } 407 408 class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst { 409 bits<5> wt; 410 bits<5> ws; 411 bits<5> wd; 412 413 let Inst{25-21} = major; 414 let Inst{20-16} = wt; 415 let Inst{15-11} = ws; 416 let Inst{10-6} = wd; 417 let Inst{5-0} = minor; 418 } 419 420 class MSA_CBRANCH_FMT<bits<3> major, bits<2> df>: MSACBranch { 421 bits<16> offset; 422 bits<5> wt; 423 424 let Inst{25-23} = major; 425 let Inst{22-21} = df; 426 let Inst{20-16} = wt; 427 let Inst{15-0} = offset; 428 } 429 430 class MSA_CBRANCH_V_FMT<bits<5> major>: MSACBranch { 431 bits<16> offset; 432 bits<5> wt; 433 434 let Inst{25-21} = major; 435 let Inst{20-16} = wt; 436 let Inst{15-0} = offset; 437 } 438 439 class SPECIAL_LSA_FMT<bits<6> minor>: MSASpecial { 440 bits<5> rs; 441 bits<5> rt; 442 bits<5> rd; 443 bits<2> sa; 444 445 let Inst{25-21} = rs; 446 let Inst{20-16} = rt; 447 let Inst{15-11} = rd; 448 let Inst{10-8} = 0b000; 449 let Inst{7-6} = sa; 450 let Inst{5-0} = minor; 451 } 452 453 class SPECIAL_DLSA_FMT<bits<6> minor>: MSA64Special { 454 bits<5> rs; 455 bits<5> rt; 456 bits<5> rd; 457 bits<2> sa; 458 459 let Inst{25-21} = rs; 460 let Inst{20-16} = rt; 461 let Inst{15-11} = rd; 462 let Inst{10-8} = 0b000; 463 let Inst{7-6} = sa; 464 let Inst{5-0} = minor; 465 } 466
