1 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Altivec extension to the PowerPC instruction set. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Altivec transformation functions and pattern fragments. 16 // 17 18 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 19 // of that type. 20 def vnot_ppc : PatFrag<(ops node:$in), 21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 22 23 def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 24 (vector_shuffle node:$lhs, node:$rhs), [{ 25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false, 26 *CurDAG); 27 }]>; 28 def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 29 (vector_shuffle node:$lhs, node:$rhs), [{ 30 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false, 31 *CurDAG); 32 }]>; 33 def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 34 (vector_shuffle node:$lhs, node:$rhs), [{ 35 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true, 36 *CurDAG); 37 }]>; 38 def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 39 (vector_shuffle node:$lhs, node:$rhs), [{ 40 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true, 41 *CurDAG); 42 }]>; 43 44 45 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 47 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false, 48 *CurDAG); 49 }]>; 50 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 51 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 52 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false, 53 *CurDAG); 54 }]>; 55 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 56 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 57 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false, 58 *CurDAG); 59 }]>; 60 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 61 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 62 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false, 63 *CurDAG); 64 }]>; 65 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 66 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 67 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false, 68 *CurDAG); 69 }]>; 70 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 71 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 72 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false, 73 *CurDAG); 74 }]>; 75 76 77 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 78 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 79 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true, 80 *CurDAG); 81 }]>; 82 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 83 (vector_shuffle node:$lhs, node:$rhs), [{ 84 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true, 85 *CurDAG); 86 }]>; 87 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 88 (vector_shuffle node:$lhs, node:$rhs), [{ 89 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true, 90 *CurDAG); 91 }]>; 92 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 93 (vector_shuffle node:$lhs, node:$rhs), [{ 94 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true, 95 *CurDAG); 96 }]>; 97 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 98 (vector_shuffle node:$lhs, node:$rhs), [{ 99 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true, 100 *CurDAG); 101 }]>; 102 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 103 (vector_shuffle node:$lhs, node:$rhs), [{ 104 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true, 105 *CurDAG); 106 }]>; 107 108 109 def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 110 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false, *CurDAG)); 111 }]>; 112 def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 113 (vector_shuffle node:$lhs, node:$rhs), [{ 114 return PPC::isVSLDOIShuffleMask(N, false, *CurDAG) != -1; 115 }], VSLDOI_get_imm>; 116 117 118 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 119 /// vector_shuffle(X,undef,mask) by the dag combiner. 120 def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 121 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true, *CurDAG)); 122 }]>; 123 def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 124 (vector_shuffle node:$lhs, node:$rhs), [{ 125 return PPC::isVSLDOIShuffleMask(N, true, *CurDAG) != -1; 126 }], VSLDOI_unary_get_imm>; 127 128 129 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 130 def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 131 return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG)); 132 }]>; 133 def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 134 (vector_shuffle node:$lhs, node:$rhs), [{ 135 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 136 }], VSPLTB_get_imm>; 137 def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 138 return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG)); 139 }]>; 140 def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 141 (vector_shuffle node:$lhs, node:$rhs), [{ 142 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 143 }], VSPLTH_get_imm>; 144 def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 145 return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG)); 146 }]>; 147 def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 148 (vector_shuffle node:$lhs, node:$rhs), [{ 149 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 150 }], VSPLTW_get_imm>; 151 152 153 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 154 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 155 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 156 }]>; 157 def vecspltisb : PatLeaf<(build_vector), [{ 158 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 159 }], VSPLTISB_get_imm>; 160 161 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 162 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 163 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 164 }]>; 165 def vecspltish : PatLeaf<(build_vector), [{ 166 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 167 }], VSPLTISH_get_imm>; 168 169 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 170 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 171 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 172 }]>; 173 def vecspltisw : PatLeaf<(build_vector), [{ 174 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 175 }], VSPLTISW_get_imm>; 176 177 //===----------------------------------------------------------------------===// 178 // Helpers for defining instructions that directly correspond to intrinsics. 179 180 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 181 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 182 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 183 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 184 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 185 186 // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 187 // inputs doesn't match the type of the output. 188 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 189 ValueType InTy> 190 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 191 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 192 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 193 194 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 195 // input types and an output type. 196 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 197 ValueType In1Ty, ValueType In2Ty> 198 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 199 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 200 [(set OutTy:$vD, 201 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 202 203 // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 204 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 205 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 206 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 207 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 208 209 // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 210 // inputs doesn't match the type of the output. 211 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 212 ValueType InTy> 213 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 214 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 215 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 216 217 // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 218 // input types and an output type. 219 class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 220 ValueType In1Ty, ValueType In2Ty> 221 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 222 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 223 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 224 225 // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 226 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 227 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 228 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 229 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 230 231 // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 232 // inputs doesn't match the type of the output. 233 class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 234 ValueType InTy> 235 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 236 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 237 [(set OutTy:$vD, (IntID InTy:$vB))]>; 238 239 //===----------------------------------------------------------------------===// 240 // Instruction Definitions. 241 242 def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">; 243 let Predicates = [HasAltivec] in { 244 245 let isCodeGenOnly = 1 in { 246 def DSS : DSS_Form<822, (outs), 247 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), 248 "dss $STRM", IIC_LdStLoad /*FIXME*/, []>, 249 Deprecated<DeprecatedDST>; 250 def DSSALL : DSS_Form<822, (outs), 251 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), 252 "dssall", IIC_LdStLoad /*FIXME*/, []>, 253 Deprecated<DeprecatedDST>; 254 def DST : DSS_Form<342, (outs), 255 (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), 256 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 257 Deprecated<DeprecatedDST>; 258 def DSTT : DSS_Form<342, (outs), 259 (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), 260 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 261 Deprecated<DeprecatedDST>; 262 def DSTST : DSS_Form<374, (outs), 263 (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), 264 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 265 Deprecated<DeprecatedDST>; 266 def DSTSTT : DSS_Form<374, (outs), 267 (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), 268 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 269 Deprecated<DeprecatedDST>; 270 271 def DST64 : DSS_Form<342, (outs), 272 (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), 273 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 274 Deprecated<DeprecatedDST>; 275 def DSTT64 : DSS_Form<342, (outs), 276 (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), 277 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 278 Deprecated<DeprecatedDST>; 279 def DSTST64 : DSS_Form<374, (outs), 280 (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), 281 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 282 Deprecated<DeprecatedDST>; 283 def DSTSTT64 : DSS_Form<374, (outs), 284 (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), 285 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 286 Deprecated<DeprecatedDST>; 287 } 288 289 def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), 290 "mfvscr $vD", IIC_LdStStore, 291 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 292 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), 293 "mtvscr $vB", IIC_LdStLoad, 294 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 295 296 let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. 297 def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src), 298 "lvebx $vD, $src", IIC_LdStLoad, 299 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 300 def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src), 301 "lvehx $vD, $src", IIC_LdStLoad, 302 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 303 def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src), 304 "lvewx $vD, $src", IIC_LdStLoad, 305 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 306 def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src), 307 "lvx $vD, $src", IIC_LdStLoad, 308 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 309 def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src), 310 "lvxl $vD, $src", IIC_LdStLoad, 311 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 312 } 313 314 def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src), 315 "lvsl $vD, $src", IIC_LdStLoad, 316 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 317 PPC970_Unit_LSU; 318 def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src), 319 "lvsr $vD, $src", IIC_LdStLoad, 320 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 321 PPC970_Unit_LSU; 322 323 let PPC970_Unit = 2 in { // Stores. 324 def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), 325 "stvebx $rS, $dst", IIC_LdStStore, 326 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 327 def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), 328 "stvehx $rS, $dst", IIC_LdStStore, 329 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 330 def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), 331 "stvewx $rS, $dst", IIC_LdStStore, 332 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 333 def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), 334 "stvx $rS, $dst", IIC_LdStStore, 335 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 336 def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), 337 "stvxl $rS, $dst", IIC_LdStStore, 338 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 339 } 340 341 let PPC970_Unit = 5 in { // VALU Operations. 342 // VA-Form instructions. 3-input AltiVec ops. 343 let isCommutable = 1 in { 344 def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 345 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP, 346 [(set v4f32:$vD, 347 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 348 349 // FIXME: The fma+fneg pattern won't match because fneg is not legal. 350 def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 351 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP, 352 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 353 (fneg v4f32:$vB))))]>; 354 355 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 356 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 357 v8i16>; 358 def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 359 } // isCommutable 360 361 def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 362 v4i32, v4i32, v16i8>; 363 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 364 365 // Shuffles. 366 def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH), 367 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP, 368 [(set v16i8:$vD, 369 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>; 370 371 // VX-Form instructions. AltiVec arithmetic ops. 372 let isCommutable = 1 in { 373 def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 374 "vaddfp $vD, $vA, $vB", IIC_VecFP, 375 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 376 377 def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 378 "vaddubm $vD, $vA, $vB", IIC_VecGeneral, 379 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 380 def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 381 "vadduhm $vD, $vA, $vB", IIC_VecGeneral, 382 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 383 def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 384 "vadduwm $vD, $vA, $vB", IIC_VecGeneral, 385 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 386 387 def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 388 def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 389 def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 390 def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 391 def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 392 def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 393 def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 394 } // isCommutable 395 396 let isCommutable = 1 in 397 def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 398 "vand $vD, $vA, $vB", IIC_VecFP, 399 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 400 def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 401 "vandc $vD, $vA, $vB", IIC_VecFP, 402 [(set v4i32:$vD, (and v4i32:$vA, 403 (vnot_ppc v4i32:$vB)))]>; 404 405 def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 406 "vcfsx $vD, $vB, $UIMM", IIC_VecFP, 407 [(set v4f32:$vD, 408 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>; 409 def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 410 "vcfux $vD, $vB, $UIMM", IIC_VecFP, 411 [(set v4f32:$vD, 412 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>; 413 def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 414 "vctsxs $vD, $vB, $UIMM", IIC_VecFP, 415 [(set v4i32:$vD, 416 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>; 417 def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 418 "vctuxs $vD, $vB, $UIMM", IIC_VecFP, 419 [(set v4i32:$vD, 420 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>; 421 422 // Defines with the UIM field set to 0 for floating-point 423 // to integer (fp_to_sint/fp_to_uint) conversions and integer 424 // to floating-point (sint_to_fp/uint_to_fp) conversions. 425 let isCodeGenOnly = 1, VA = 0 in { 426 def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), 427 "vcfsx $vD, $vB, 0", IIC_VecFP, 428 [(set v4f32:$vD, 429 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 430 def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), 431 "vctuxs $vD, $vB, 0", IIC_VecFP, 432 [(set v4i32:$vD, 433 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 434 def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), 435 "vcfux $vD, $vB, 0", IIC_VecFP, 436 [(set v4f32:$vD, 437 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 438 def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), 439 "vctsxs $vD, $vB, 0", IIC_VecFP, 440 [(set v4i32:$vD, 441 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 442 } 443 def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 444 def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 445 446 let isCommutable = 1 in { 447 def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 448 def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 449 def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 450 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 451 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 452 def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 453 454 def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 455 def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 456 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 457 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 458 def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 459 def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 460 def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 461 def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 462 def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 463 def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 464 def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 465 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 466 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 467 def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 468 } // isCommutable 469 470 def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 471 "vmrghb $vD, $vA, $vB", IIC_VecFP, 472 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 473 def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 474 "vmrghh $vD, $vA, $vB", IIC_VecFP, 475 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 476 def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 477 "vmrghw $vD, $vA, $vB", IIC_VecFP, 478 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 479 def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 480 "vmrglb $vD, $vA, $vB", IIC_VecFP, 481 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 482 def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 483 "vmrglh $vD, $vA, $vB", IIC_VecFP, 484 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 485 def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 486 "vmrglw $vD, $vA, $vB", IIC_VecFP, 487 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 488 489 def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 490 v4i32, v16i8, v4i32>; 491 def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 492 v4i32, v8i16, v4i32>; 493 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 494 v4i32, v8i16, v4i32>; 495 def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 496 v4i32, v16i8, v4i32>; 497 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 498 v4i32, v8i16, v4i32>; 499 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 500 v4i32, v8i16, v4i32>; 501 502 let isCommutable = 1 in { 503 def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 504 v8i16, v16i8>; 505 def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 506 v4i32, v8i16>; 507 def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 508 v8i16, v16i8>; 509 def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 510 v4i32, v8i16>; 511 def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 512 v8i16, v16i8>; 513 def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 514 v4i32, v8i16>; 515 def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 516 v8i16, v16i8>; 517 def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 518 v4i32, v8i16>; 519 } // isCommutable 520 521 def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 522 def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 523 def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 524 def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 525 def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 526 def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 527 528 def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 529 530 def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 531 "vsubfp $vD, $vA, $vB", IIC_VecGeneral, 532 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 533 def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 534 "vsububm $vD, $vA, $vB", IIC_VecGeneral, 535 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 536 def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 537 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral, 538 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 539 def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 540 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral, 541 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 542 543 def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 544 def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 545 def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 546 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 547 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 548 def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 549 550 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 551 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 552 553 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, 554 v4i32, v16i8, v4i32>; 555 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 556 v4i32, v8i16, v4i32>; 557 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 558 v4i32, v16i8, v4i32>; 559 560 def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 561 "vnor $vD, $vA, $vB", IIC_VecFP, 562 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, 563 v4i32:$vB)))]>; 564 let isCommutable = 1 in { 565 def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 566 "vor $vD, $vA, $vB", IIC_VecFP, 567 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 568 def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 569 "vxor $vD, $vA, $vB", IIC_VecFP, 570 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 571 } // isCommutable 572 573 def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 574 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 575 def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 576 577 def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 578 def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 579 580 def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 581 def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 582 def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 583 584 def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 585 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, 586 [(set v16i8:$vD, 587 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 588 def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 589 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, 590 [(set v16i8:$vD, 591 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 592 def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 593 "vspltw $vD, $vB, $UIMM", IIC_VecPerm, 594 [(set v16i8:$vD, 595 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 596 597 def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 598 def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 599 600 def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 601 def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 602 def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 603 def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 604 def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 605 def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 606 607 608 def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), 609 "vspltisb $vD, $SIMM", IIC_VecPerm, 610 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 611 def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), 612 "vspltish $vD, $SIMM", IIC_VecPerm, 613 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 614 def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), 615 "vspltisw $vD, $SIMM", IIC_VecPerm, 616 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 617 618 // Vector Pack. 619 def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 620 v8i16, v4i32>; 621 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 622 v16i8, v8i16>; 623 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 624 v16i8, v8i16>; 625 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 626 v16i8, v4i32>; 627 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 628 v8i16, v4i32>; 629 def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 630 "vpkuhum $vD, $vA, $vB", IIC_VecFP, 631 [(set v16i8:$vD, 632 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 633 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 634 v16i8, v8i16>; 635 def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 636 "vpkuwum $vD, $vA, $vB", IIC_VecFP, 637 [(set v16i8:$vD, 638 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 639 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 640 v8i16, v4i32>; 641 642 // Vector Unpack. 643 def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 644 v4i32, v8i16>; 645 def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 646 v8i16, v16i8>; 647 def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 648 v4i32, v8i16>; 649 def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 650 v4i32, v8i16>; 651 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 652 v8i16, v16i8>; 653 def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 654 v4i32, v8i16>; 655 656 657 // Altivec Comparisons. 658 659 class VCMP<bits<10> xo, string asmstr, ValueType Ty> 660 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 661 IIC_VecFPCompare, 662 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 663 class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 664 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 665 IIC_VecFPCompare, 666 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { 667 let Defs = [CR6]; 668 let RC = 1; 669 } 670 671 // f32 element comparisons.0 672 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 673 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 674 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 675 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 676 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 677 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 678 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 679 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 680 681 // i8 element comparisons. 682 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 683 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 684 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 685 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 686 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 687 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 688 689 // i16 element comparisons. 690 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 691 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 692 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 693 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 694 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 695 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 696 697 // i32 element comparisons. 698 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 699 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 700 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 701 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 702 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 703 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 704 705 let isCodeGenOnly = 1 in { 706 def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 707 "vxor $vD, $vD, $vD", IIC_VecFP, 708 [(set v16i8:$vD, (v16i8 immAllZerosV))]>; 709 def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 710 "vxor $vD, $vD, $vD", IIC_VecFP, 711 [(set v8i16:$vD, (v8i16 immAllZerosV))]>; 712 def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 713 "vxor $vD, $vD, $vD", IIC_VecFP, 714 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 715 716 let IMM=-1 in { 717 def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), 718 "vspltisw $vD, -1", IIC_VecFP, 719 [(set v16i8:$vD, (v16i8 immAllOnesV))]>; 720 def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), 721 "vspltisw $vD, -1", IIC_VecFP, 722 [(set v8i16:$vD, (v8i16 immAllOnesV))]>; 723 def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), 724 "vspltisw $vD, -1", IIC_VecFP, 725 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 726 } 727 } 728 } // VALU Operations. 729 730 //===----------------------------------------------------------------------===// 731 // Additional Altivec Patterns 732 // 733 734 // DS* intrinsics 735 def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; 736 def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; 737 738 // * 32-bit 739 def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM), 740 (DST 0, imm:$STRM, $rA, $rB)>; 741 def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM), 742 (DSTT 1, imm:$STRM, $rA, $rB)>; 743 def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM), 744 (DSTST 0, imm:$STRM, $rA, $rB)>; 745 def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM), 746 (DSTSTT 1, imm:$STRM, $rA, $rB)>; 747 748 // * 64-bit 749 def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM), 750 (DST64 0, imm:$STRM, $rA, $rB)>; 751 def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM), 752 (DSTT64 1, imm:$STRM, $rA, $rB)>; 753 def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM), 754 (DSTST64 0, imm:$STRM, $rA, $rB)>; 755 def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM), 756 (DSTSTT64 1, imm:$STRM, $rA, $rB)>; 757 758 // Loads. 759 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 760 761 // Stores. 762 def : Pat<(store v4i32:$rS, xoaddr:$dst), 763 (STVX $rS, xoaddr:$dst)>; 764 765 // Bit conversions. 766 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 767 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 768 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 769 770 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 771 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 772 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 773 774 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 775 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 776 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 777 778 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 779 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 780 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 781 782 // Shuffles. 783 784 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 785 def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 786 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 787 def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 788 (VPKUWUM $vA, $vA)>; 789 def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 790 (VPKUHUM $vA, $vA)>; 791 792 // Match vmrg*(x,x) 793 def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 794 (VMRGLB $vA, $vA)>; 795 def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 796 (VMRGLH $vA, $vA)>; 797 def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 798 (VMRGLW $vA, $vA)>; 799 def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 800 (VMRGHB $vA, $vA)>; 801 def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 802 (VMRGHH $vA, $vA)>; 803 def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 804 (VMRGHW $vA, $vA)>; 805 806 // Logical Operations 807 def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; 808 809 def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), 810 (VNOR $A, $B)>; 811 def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), 812 (VANDC $A, $B)>; 813 814 def : Pat<(fmul v4f32:$vA, v4f32:$vB), 815 (VMADDFP $vA, $vB, 816 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>; 817 818 // Fused multiply add and multiply sub for packed float. These are represented 819 // separately from the real instructions above, for operations that must have 820 // the additional precision, such as Newton-Rhapson (used by divide, sqrt) 821 def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 822 (VMADDFP $A, $B, $C)>; 823 def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 824 (VNMSUBFP $A, $B, $C)>; 825 826 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 827 (VMADDFP $A, $B, $C)>; 828 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 829 (VNMSUBFP $A, $B, $C)>; 830 831 def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 832 (VPERM $vA, $vB, $vC)>; 833 834 def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 835 def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 836 837 // Vector shifts 838 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 839 (v16i8 (VSLB $vA, $vB))>; 840 def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 841 (v8i16 (VSLH $vA, $vB))>; 842 def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 843 (v4i32 (VSLW $vA, $vB))>; 844 845 def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 846 (v16i8 (VSRB $vA, $vB))>; 847 def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 848 (v8i16 (VSRH $vA, $vB))>; 849 def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 850 (v4i32 (VSRW $vA, $vB))>; 851 852 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 853 (v16i8 (VSRAB $vA, $vB))>; 854 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 855 (v8i16 (VSRAH $vA, $vB))>; 856 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 857 (v4i32 (VSRAW $vA, $vB))>; 858 859 // Float to integer and integer to float conversions 860 def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 861 (VCTSXS_0 $vA)>; 862 def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 863 (VCTUXS_0 $vA)>; 864 def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 865 (VCFSX_0 $vA)>; 866 def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 867 (VCFUX_0 $vA)>; 868 869 // Floating-point rounding 870 def : Pat<(v4f32 (ffloor v4f32:$vA)), 871 (VRFIM $vA)>; 872 def : Pat<(v4f32 (fceil v4f32:$vA)), 873 (VRFIP $vA)>; 874 def : Pat<(v4f32 (ftrunc v4f32:$vA)), 875 (VRFIZ $vA)>; 876 def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 877 (VRFIN $vA)>; 878 879 } // end HasAltivec 880 881
