1 //===-- PPCTargetMachine.h - Define TargetMachine for PowerPC ---*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the PowerPC specific subclass of TargetMachine. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef PPC_TARGETMACHINE_H 15 #define PPC_TARGETMACHINE_H 16 17 #include "PPCInstrInfo.h" 18 #include "PPCSubtarget.h" 19 #include "llvm/IR/DataLayout.h" 20 #include "llvm/Target/TargetMachine.h" 21 22 namespace llvm { 23 24 /// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets. 25 /// 26 class PPCTargetMachine : public LLVMTargetMachine { 27 PPCSubtarget Subtarget; 28 29 public: 30 PPCTargetMachine(const Target &T, StringRef TT, 31 StringRef CPU, StringRef FS, const TargetOptions &Options, 32 Reloc::Model RM, CodeModel::Model CM, 33 CodeGenOpt::Level OL, bool is64Bit); 34 35 const PPCInstrInfo *getInstrInfo() const override { 36 return getSubtargetImpl()->getInstrInfo(); 37 } 38 const PPCFrameLowering *getFrameLowering() const override { 39 return getSubtargetImpl()->getFrameLowering(); 40 } 41 PPCJITInfo *getJITInfo() override { return Subtarget.getJITInfo(); } 42 const PPCTargetLowering *getTargetLowering() const override { 43 return getSubtargetImpl()->getTargetLowering(); 44 } 45 const PPCSelectionDAGInfo* getSelectionDAGInfo() const override { 46 return getSubtargetImpl()->getSelectionDAGInfo(); 47 } 48 const PPCRegisterInfo *getRegisterInfo() const override { 49 return &getInstrInfo()->getRegisterInfo(); 50 } 51 52 const DataLayout *getDataLayout() const override { 53 return getSubtargetImpl()->getDataLayout(); 54 } 55 const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; } 56 const InstrItineraryData *getInstrItineraryData() const override { 57 return &getSubtargetImpl()->getInstrItineraryData(); 58 } 59 60 // Pass Pipeline Configuration 61 TargetPassConfig *createPassConfig(PassManagerBase &PM) override; 62 bool addCodeEmitter(PassManagerBase &PM, 63 JITCodeEmitter &JCE) override; 64 65 /// \brief Register PPC analysis passes with a pass manager. 66 void addAnalysisPasses(PassManagerBase &PM) override; 67 }; 68 69 /// PPC32TargetMachine - PowerPC 32-bit target machine. 70 /// 71 class PPC32TargetMachine : public PPCTargetMachine { 72 virtual void anchor(); 73 public: 74 PPC32TargetMachine(const Target &T, StringRef TT, 75 StringRef CPU, StringRef FS, const TargetOptions &Options, 76 Reloc::Model RM, CodeModel::Model CM, 77 CodeGenOpt::Level OL); 78 }; 79 80 /// PPC64TargetMachine - PowerPC 64-bit target machine. 81 /// 82 class PPC64TargetMachine : public PPCTargetMachine { 83 virtual void anchor(); 84 public: 85 PPC64TargetMachine(const Target &T, StringRef TT, 86 StringRef CPU, StringRef FS, const TargetOptions &Options, 87 Reloc::Model RM, CodeModel::Model CM, 88 CodeGenOpt::Level OL); 89 }; 90 91 } // end namespace llvm 92 93 #endif 94
