Home | History | Annotate | Download | only in R600 
      1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //==-----------------------------------------------------------------------===//
      9 
     10 include "llvm/Target/Target.td"
     11 
     12 //===----------------------------------------------------------------------===//
     13 // Subtarget Features
     14 //===----------------------------------------------------------------------===//
     15 
     16 // Debugging Features
     17 
     18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
     19         "DumpCode",
     20         "true",
     21         "Dump MachineInstrs in the CodeEmitter">;
     22 
     23 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
     24         "EnableIRStructurizer",
     25         "false",
     26         "Disable IR Structurizer">;
     27 
     28 // Target features
     29 
     30 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
     31         "EnableIfCvt",
     32         "false",
     33         "Disable the if conversion pass">;
     34 
     35 def FeatureFP64 : SubtargetFeature<"fp64",
     36         "FP64",
     37         "true",
     38         "Enable double precision operations">;
     39 
     40 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
     41         "Is64bit",
     42         "true",
     43         "Specify if 64-bit addressing should be used">;
     44 
     45 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
     46         "R600ALUInst",
     47         "false",
     48         "Older version of ALU instructions encoding">;
     49 
     50 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
     51         "HasVertexCache",
     52         "true",
     53         "Specify use of dedicated vertex cache">;
     54 
     55 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
     56         "CaymanISA",
     57         "true",
     58         "Use Cayman ISA">;
     59 
     60 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
     61         "CFALUBug",
     62         "true",
     63         "GPU has CF_ALU bug">;
     64 
     65 class SubtargetFeatureFetchLimit <string Value> :
     66                           SubtargetFeature <"fetch"#Value,
     67         "TexVTXClauseSize",
     68         Value,
     69         "Limit the maximum number of fetches in a clause to "#Value>;
     70 
     71 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
     72 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
     73 
     74 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
     75         "wavefrontsize"#Value,
     76         "WavefrontSize",
     77         !cast<string>(Value),
     78         "The number of threads per wavefront">;
     79 
     80 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
     81 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
     82 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
     83 
     84 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
     85         "localmemorysize"#Value,
     86         "LocalMemorySize",
     87         !cast<string>(Value),
     88         "The size of local memory in bytes">;
     89 
     90 class SubtargetFeatureGeneration <string Value,
     91                                   list<SubtargetFeature> Implies> :
     92         SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
     93                           Value#" GPU generation", Implies>;
     94 
     95 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
     96 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
     97 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
     98 
     99 def FeatureR600 : SubtargetFeatureGeneration<"R600",
    100         [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
    101 
    102 def FeatureR700 : SubtargetFeatureGeneration<"R700",
    103         [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
    104 
    105 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
    106         [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
    107 
    108 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
    109         [FeatureFetchLimit16, FeatureWavefrontSize64,
    110          FeatureLocalMemorySize32768]
    111 >;
    112 
    113 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
    114         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768]>;
    115 
    116 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
    117         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536]>;
    118 //===----------------------------------------------------------------------===//
    119 
    120 def AMDGPUInstrInfo : InstrInfo {
    121   let guessInstructionProperties = 1;
    122 }
    123 
    124 def AMDGPU : Target {
    125   // Pull in Instruction Info:
    126   let InstructionSet = AMDGPUInstrInfo;
    127 }
    128 
    129 // Dummy Instruction itineraries for pseudo instructions
    130 def ALU_NULL : FuncUnit;
    131 def NullALU : InstrItinClass;
    132 
    133 //===----------------------------------------------------------------------===//
    134 // Predicate helper class
    135 //===----------------------------------------------------------------------===//
    136 
    137 class PredicateControl {
    138   Predicate SubtargetPredicate;
    139   list<Predicate> OtherPredicates = [];
    140   list<Predicate> Predicates = !listconcat([SubtargetPredicate],
    141                                             OtherPredicates);
    142 }
    143 
    144 // Include AMDGPU TD files
    145 include "R600Schedule.td"
    146 include "SISchedule.td"
    147 include "Processors.td"
    148 include "AMDGPUInstrInfo.td"
    149 include "AMDGPUIntrinsics.td"
    150 include "AMDGPURegisterInfo.td"
    151 include "AMDGPUInstructions.td"
    152 include "AMDGPUCallingConv.td"
    153