1 //===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // R600 Instruction format definitions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 class InstR600 <dag outs, dag ins, string asm, list<dag> pattern, 15 InstrItinClass itin> 16 : AMDGPUInst <outs, ins, asm, pattern> { 17 18 field bits<64> Inst; 19 bit Trig = 0; 20 bit Op3 = 0; 21 bit isVector = 0; 22 bits<2> FlagOperandIdx = 0; 23 bit Op1 = 0; 24 bit Op2 = 0; 25 bit LDS_1A = 0; 26 bit LDS_1A1D = 0; 27 bit HasNativeOperands = 0; 28 bit VTXInst = 0; 29 bit TEXInst = 0; 30 bit ALUInst = 0; 31 bit IsExport = 0; 32 bit LDS_1A2D = 0; 33 34 let Namespace = "AMDGPU"; 35 let OutOperandList = outs; 36 let InOperandList = ins; 37 let AsmString = asm; 38 let Pattern = pattern; 39 let Itinerary = itin; 40 41 let TSFlags{4} = Trig; 42 let TSFlags{5} = Op3; 43 44 // Vector instructions are instructions that must fill all slots in an 45 // instruction group 46 let TSFlags{6} = isVector; 47 let TSFlags{8-7} = FlagOperandIdx; 48 let TSFlags{9} = HasNativeOperands; 49 let TSFlags{10} = Op1; 50 let TSFlags{11} = Op2; 51 let TSFlags{12} = VTXInst; 52 let TSFlags{13} = TEXInst; 53 let TSFlags{14} = ALUInst; 54 let TSFlags{15} = LDS_1A; 55 let TSFlags{16} = LDS_1A1D; 56 let TSFlags{17} = IsExport; 57 let TSFlags{18} = LDS_1A2D; 58 } 59 60 //===----------------------------------------------------------------------===// 61 // ALU instructions 62 //===----------------------------------------------------------------------===// 63 64 class R600_ALU_LDS_Word0 { 65 field bits<32> Word0; 66 67 bits<11> src0; 68 bits<1> src0_rel; 69 bits<11> src1; 70 bits<1> src1_rel; 71 bits<3> index_mode = 0; 72 bits<2> pred_sel; 73 bits<1> last; 74 75 bits<9> src0_sel = src0{8-0}; 76 bits<2> src0_chan = src0{10-9}; 77 bits<9> src1_sel = src1{8-0}; 78 bits<2> src1_chan = src1{10-9}; 79 80 let Word0{8-0} = src0_sel; 81 let Word0{9} = src0_rel; 82 let Word0{11-10} = src0_chan; 83 let Word0{21-13} = src1_sel; 84 let Word0{22} = src1_rel; 85 let Word0{24-23} = src1_chan; 86 let Word0{28-26} = index_mode; 87 let Word0{30-29} = pred_sel; 88 let Word0{31} = last; 89 } 90 91 class R600ALU_Word0 : R600_ALU_LDS_Word0 { 92 93 bits<1> src0_neg; 94 bits<1> src1_neg; 95 96 let Word0{12} = src0_neg; 97 let Word0{25} = src1_neg; 98 } 99 100 class R600ALU_Word1 { 101 field bits<32> Word1; 102 103 bits<11> dst; 104 bits<3> bank_swizzle; 105 bits<1> dst_rel; 106 bits<1> clamp; 107 108 bits<7> dst_sel = dst{6-0}; 109 bits<2> dst_chan = dst{10-9}; 110 111 let Word1{20-18} = bank_swizzle; 112 let Word1{27-21} = dst_sel; 113 let Word1{28} = dst_rel; 114 let Word1{30-29} = dst_chan; 115 let Word1{31} = clamp; 116 } 117 118 class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{ 119 120 bits<1> src0_abs; 121 bits<1> src1_abs; 122 bits<1> update_exec_mask; 123 bits<1> update_pred; 124 bits<1> write; 125 bits<2> omod; 126 127 let Word1{0} = src0_abs; 128 let Word1{1} = src1_abs; 129 let Word1{2} = update_exec_mask; 130 let Word1{3} = update_pred; 131 let Word1{4} = write; 132 let Word1{6-5} = omod; 133 let Word1{17-7} = alu_inst; 134 } 135 136 class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{ 137 138 bits<11> src2; 139 bits<1> src2_rel; 140 bits<1> src2_neg; 141 142 bits<9> src2_sel = src2{8-0}; 143 bits<2> src2_chan = src2{10-9}; 144 145 let Word1{8-0} = src2_sel; 146 let Word1{9} = src2_rel; 147 let Word1{11-10} = src2_chan; 148 let Word1{12} = src2_neg; 149 let Word1{17-13} = alu_inst; 150 } 151 152 class R600LDS_Word1 { 153 field bits<32> Word1; 154 155 bits<11> src2; 156 bits<9> src2_sel = src2{8-0}; 157 bits<2> src2_chan = src2{10-9}; 158 bits<1> src2_rel; 159 // offset specifies the stride offset to the second set of data to be read 160 // from. This is a dword offset. 161 bits<5> alu_inst = 17; // OP3_INST_LDS_IDX_OP 162 bits<3> bank_swizzle; 163 bits<6> lds_op; 164 bits<2> dst_chan = 0; 165 166 let Word1{8-0} = src2_sel; 167 let Word1{9} = src2_rel; 168 let Word1{11-10} = src2_chan; 169 let Word1{17-13} = alu_inst; 170 let Word1{20-18} = bank_swizzle; 171 let Word1{26-21} = lds_op; 172 let Word1{30-29} = dst_chan; 173 } 174 175 176 /* 177 XXX: R600 subtarget uses a slightly different encoding than the other 178 subtargets. We currently handle this in R600MCCodeEmitter, but we may 179 want to use these instruction classes in the future. 180 181 class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 { 182 183 bits<1> fog_merge; 184 bits<10> alu_inst; 185 186 let Inst{37} = fog_merge; 187 let Inst{39-38} = omod; 188 let Inst{49-40} = alu_inst; 189 } 190 191 class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 { 192 193 bits<11> alu_inst; 194 195 let Inst{38-37} = omod; 196 let Inst{49-39} = alu_inst; 197 } 198 */ 199 200 //===----------------------------------------------------------------------===// 201 // Vertex Fetch instructions 202 //===----------------------------------------------------------------------===// 203 204 class VTX_WORD0 { 205 field bits<32> Word0; 206 bits<7> src_gpr; 207 bits<5> VC_INST; 208 bits<2> FETCH_TYPE; 209 bits<1> FETCH_WHOLE_QUAD; 210 bits<8> BUFFER_ID; 211 bits<1> SRC_REL; 212 bits<2> SRC_SEL_X; 213 214 let Word0{4-0} = VC_INST; 215 let Word0{6-5} = FETCH_TYPE; 216 let Word0{7} = FETCH_WHOLE_QUAD; 217 let Word0{15-8} = BUFFER_ID; 218 let Word0{22-16} = src_gpr; 219 let Word0{23} = SRC_REL; 220 let Word0{25-24} = SRC_SEL_X; 221 } 222 223 class VTX_WORD0_eg : VTX_WORD0 { 224 225 bits<6> MEGA_FETCH_COUNT; 226 227 let Word0{31-26} = MEGA_FETCH_COUNT; 228 } 229 230 class VTX_WORD0_cm : VTX_WORD0 { 231 232 bits<2> SRC_SEL_Y; 233 bits<2> STRUCTURED_READ; 234 bits<1> LDS_REQ; 235 bits<1> COALESCED_READ; 236 237 let Word0{27-26} = SRC_SEL_Y; 238 let Word0{29-28} = STRUCTURED_READ; 239 let Word0{30} = LDS_REQ; 240 let Word0{31} = COALESCED_READ; 241 } 242 243 class VTX_WORD1_GPR { 244 field bits<32> Word1; 245 bits<7> dst_gpr; 246 bits<1> DST_REL; 247 bits<3> DST_SEL_X; 248 bits<3> DST_SEL_Y; 249 bits<3> DST_SEL_Z; 250 bits<3> DST_SEL_W; 251 bits<1> USE_CONST_FIELDS; 252 bits<6> DATA_FORMAT; 253 bits<2> NUM_FORMAT_ALL; 254 bits<1> FORMAT_COMP_ALL; 255 bits<1> SRF_MODE_ALL; 256 257 let Word1{6-0} = dst_gpr; 258 let Word1{7} = DST_REL; 259 let Word1{8} = 0; // Reserved 260 let Word1{11-9} = DST_SEL_X; 261 let Word1{14-12} = DST_SEL_Y; 262 let Word1{17-15} = DST_SEL_Z; 263 let Word1{20-18} = DST_SEL_W; 264 let Word1{21} = USE_CONST_FIELDS; 265 let Word1{27-22} = DATA_FORMAT; 266 let Word1{29-28} = NUM_FORMAT_ALL; 267 let Word1{30} = FORMAT_COMP_ALL; 268 let Word1{31} = SRF_MODE_ALL; 269 } 270 271 //===----------------------------------------------------------------------===// 272 // Texture fetch instructions 273 //===----------------------------------------------------------------------===// 274 275 class TEX_WORD0 { 276 field bits<32> Word0; 277 278 bits<5> TEX_INST; 279 bits<2> INST_MOD; 280 bits<1> FETCH_WHOLE_QUAD; 281 bits<8> RESOURCE_ID; 282 bits<7> SRC_GPR; 283 bits<1> SRC_REL; 284 bits<1> ALT_CONST; 285 bits<2> RESOURCE_INDEX_MODE; 286 bits<2> SAMPLER_INDEX_MODE; 287 288 let Word0{4-0} = TEX_INST; 289 let Word0{6-5} = INST_MOD; 290 let Word0{7} = FETCH_WHOLE_QUAD; 291 let Word0{15-8} = RESOURCE_ID; 292 let Word0{22-16} = SRC_GPR; 293 let Word0{23} = SRC_REL; 294 let Word0{24} = ALT_CONST; 295 let Word0{26-25} = RESOURCE_INDEX_MODE; 296 let Word0{28-27} = SAMPLER_INDEX_MODE; 297 } 298 299 class TEX_WORD1 { 300 field bits<32> Word1; 301 302 bits<7> DST_GPR; 303 bits<1> DST_REL; 304 bits<3> DST_SEL_X; 305 bits<3> DST_SEL_Y; 306 bits<3> DST_SEL_Z; 307 bits<3> DST_SEL_W; 308 bits<7> LOD_BIAS; 309 bits<1> COORD_TYPE_X; 310 bits<1> COORD_TYPE_Y; 311 bits<1> COORD_TYPE_Z; 312 bits<1> COORD_TYPE_W; 313 314 let Word1{6-0} = DST_GPR; 315 let Word1{7} = DST_REL; 316 let Word1{11-9} = DST_SEL_X; 317 let Word1{14-12} = DST_SEL_Y; 318 let Word1{17-15} = DST_SEL_Z; 319 let Word1{20-18} = DST_SEL_W; 320 let Word1{27-21} = LOD_BIAS; 321 let Word1{28} = COORD_TYPE_X; 322 let Word1{29} = COORD_TYPE_Y; 323 let Word1{30} = COORD_TYPE_Z; 324 let Word1{31} = COORD_TYPE_W; 325 } 326 327 class TEX_WORD2 { 328 field bits<32> Word2; 329 330 bits<5> OFFSET_X; 331 bits<5> OFFSET_Y; 332 bits<5> OFFSET_Z; 333 bits<5> SAMPLER_ID; 334 bits<3> SRC_SEL_X; 335 bits<3> SRC_SEL_Y; 336 bits<3> SRC_SEL_Z; 337 bits<3> SRC_SEL_W; 338 339 let Word2{4-0} = OFFSET_X; 340 let Word2{9-5} = OFFSET_Y; 341 let Word2{14-10} = OFFSET_Z; 342 let Word2{19-15} = SAMPLER_ID; 343 let Word2{22-20} = SRC_SEL_X; 344 let Word2{25-23} = SRC_SEL_Y; 345 let Word2{28-26} = SRC_SEL_Z; 346 let Word2{31-29} = SRC_SEL_W; 347 } 348 349 //===----------------------------------------------------------------------===// 350 // Control Flow Instructions 351 //===----------------------------------------------------------------------===// 352 353 class CF_WORD1_R600 { 354 field bits<32> Word1; 355 356 bits<3> POP_COUNT; 357 bits<5> CF_CONST; 358 bits<2> COND; 359 bits<3> COUNT; 360 bits<6> CALL_COUNT; 361 bits<1> COUNT_3; 362 bits<1> END_OF_PROGRAM; 363 bits<1> VALID_PIXEL_MODE; 364 bits<7> CF_INST; 365 bits<1> WHOLE_QUAD_MODE; 366 bits<1> BARRIER; 367 368 let Word1{2-0} = POP_COUNT; 369 let Word1{7-3} = CF_CONST; 370 let Word1{9-8} = COND; 371 let Word1{12-10} = COUNT; 372 let Word1{18-13} = CALL_COUNT; 373 let Word1{19} = COUNT_3; 374 let Word1{21} = END_OF_PROGRAM; 375 let Word1{22} = VALID_PIXEL_MODE; 376 let Word1{29-23} = CF_INST; 377 let Word1{30} = WHOLE_QUAD_MODE; 378 let Word1{31} = BARRIER; 379 } 380 381 class CF_WORD0_EG { 382 field bits<32> Word0; 383 384 bits<24> ADDR; 385 bits<3> JUMPTABLE_SEL; 386 387 let Word0{23-0} = ADDR; 388 let Word0{26-24} = JUMPTABLE_SEL; 389 } 390 391 class CF_WORD1_EG { 392 field bits<32> Word1; 393 394 bits<3> POP_COUNT; 395 bits<5> CF_CONST; 396 bits<2> COND; 397 bits<6> COUNT; 398 bits<1> VALID_PIXEL_MODE; 399 bits<1> END_OF_PROGRAM; 400 bits<8> CF_INST; 401 bits<1> BARRIER; 402 403 let Word1{2-0} = POP_COUNT; 404 let Word1{7-3} = CF_CONST; 405 let Word1{9-8} = COND; 406 let Word1{15-10} = COUNT; 407 let Word1{20} = VALID_PIXEL_MODE; 408 let Word1{21} = END_OF_PROGRAM; 409 let Word1{29-22} = CF_INST; 410 let Word1{31} = BARRIER; 411 } 412 413 class CF_ALU_WORD0 { 414 field bits<32> Word0; 415 416 bits<22> ADDR; 417 bits<4> KCACHE_BANK0; 418 bits<4> KCACHE_BANK1; 419 bits<2> KCACHE_MODE0; 420 421 let Word0{21-0} = ADDR; 422 let Word0{25-22} = KCACHE_BANK0; 423 let Word0{29-26} = KCACHE_BANK1; 424 let Word0{31-30} = KCACHE_MODE0; 425 } 426 427 class CF_ALU_WORD1 { 428 field bits<32> Word1; 429 430 bits<2> KCACHE_MODE1; 431 bits<8> KCACHE_ADDR0; 432 bits<8> KCACHE_ADDR1; 433 bits<7> COUNT; 434 bits<1> ALT_CONST; 435 bits<4> CF_INST; 436 bits<1> WHOLE_QUAD_MODE; 437 bits<1> BARRIER; 438 439 let Word1{1-0} = KCACHE_MODE1; 440 let Word1{9-2} = KCACHE_ADDR0; 441 let Word1{17-10} = KCACHE_ADDR1; 442 let Word1{24-18} = COUNT; 443 let Word1{25} = ALT_CONST; 444 let Word1{29-26} = CF_INST; 445 let Word1{30} = WHOLE_QUAD_MODE; 446 let Word1{31} = BARRIER; 447 } 448 449 class CF_ALLOC_EXPORT_WORD0_RAT { 450 field bits<32> Word0; 451 452 bits<4> rat_id; 453 bits<6> rat_inst; 454 bits<2> rim; 455 bits<2> type; 456 bits<7> rw_gpr; 457 bits<1> rw_rel; 458 bits<7> index_gpr; 459 bits<2> elem_size; 460 461 let Word0{3-0} = rat_id; 462 let Word0{9-4} = rat_inst; 463 let Word0{10} = 0; // Reserved 464 let Word0{12-11} = rim; 465 let Word0{14-13} = type; 466 let Word0{21-15} = rw_gpr; 467 let Word0{22} = rw_rel; 468 let Word0{29-23} = index_gpr; 469 let Word0{31-30} = elem_size; 470 } 471 472 class CF_ALLOC_EXPORT_WORD1_BUF { 473 field bits<32> Word1; 474 475 bits<12> array_size; 476 bits<4> comp_mask; 477 bits<4> burst_count; 478 bits<1> vpm; 479 bits<1> eop; 480 bits<8> cf_inst; 481 bits<1> mark; 482 bits<1> barrier; 483 484 let Word1{11-0} = array_size; 485 let Word1{15-12} = comp_mask; 486 let Word1{19-16} = burst_count; 487 let Word1{20} = vpm; 488 let Word1{21} = eop; 489 let Word1{29-22} = cf_inst; 490 let Word1{30} = mark; 491 let Word1{31} = barrier; 492 } 493
