1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This is a target description file for the Intel i386 architecture, referred 11 // to here as the "X86" architecture. 12 // 13 //===----------------------------------------------------------------------===// 14 15 // Get the target-independent interfaces which we are implementing... 16 // 17 include "llvm/Target/Target.td" 18 19 //===----------------------------------------------------------------------===// 20 // X86 Subtarget state 21 // 22 23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", 24 "64-bit mode (x86_64)">; 25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true", 26 "32-bit mode (80386)">; 27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true", 28 "16-bit mode (i8086)">; 29 30 //===----------------------------------------------------------------------===// 31 // X86 Subtarget features 32 //===----------------------------------------------------------------------===// 33 34 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", 35 "Enable conditional move instructions">; 36 37 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", 38 "Support POPCNT instruction">; 39 40 41 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", 42 "Enable MMX instructions">; 43 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", 44 "Enable SSE instructions", 45 // SSE codegen depends on cmovs, and all 46 // SSE1+ processors support them. 47 [FeatureMMX, FeatureCMOV]>; 48 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", 49 "Enable SSE2 instructions", 50 [FeatureSSE1]>; 51 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", 52 "Enable SSE3 instructions", 53 [FeatureSSE2]>; 54 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", 55 "Enable SSSE3 instructions", 56 [FeatureSSE3]>; 57 def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41", 58 "Enable SSE 4.1 instructions", 59 [FeatureSSSE3]>; 60 def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42", 61 "Enable SSE 4.2 instructions", 62 [FeatureSSE41]>; 63 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", 64 "Enable 3DNow! instructions", 65 [FeatureMMX]>; 66 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", 67 "Enable 3DNow! Athlon instructions", 68 [Feature3DNow]>; 69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied 70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels) 71 // without disabling 64-bit mode. 72 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", 73 "Support 64-bit instructions", 74 [FeatureCMOV]>; 75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true", 76 "64-bit with cmpxchg16b", 77 [Feature64Bit]>; 78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true", 79 "Bit testing of memory is slow">; 80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true", 81 "SHLD instruction is slow">; 82 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem", 83 "IsUAMemFast", "true", 84 "Fast unaligned memory access">; 85 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", 86 "Support SSE 4a instructions", 87 [FeatureSSE3]>; 88 89 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", 90 "Enable AVX instructions", 91 [FeatureSSE42]>; 92 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", 93 "Enable AVX2 instructions", 94 [FeatureAVX]>; 95 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F", 96 "Enable AVX-512 instructions", 97 [FeatureAVX2]>; 98 def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true", 99 "Enable AVX-512 Exponential and Reciprocal Instructions", 100 [FeatureAVX512]>; 101 def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true", 102 "Enable AVX-512 Conflict Detection Instructions", 103 [FeatureAVX512]>; 104 def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true", 105 "Enable AVX-512 PreFetch Instructions", 106 [FeatureAVX512]>; 107 108 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", 109 "Enable packed carry-less multiplication instructions", 110 [FeatureSSE2]>; 111 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", 112 "Enable three-operand fused multiple-add", 113 [FeatureAVX]>; 114 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", 115 "Enable four-operand fused multiple-add", 116 [FeatureAVX, FeatureSSE4A]>; 117 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", 118 "Enable XOP instructions", 119 [FeatureFMA4]>; 120 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", 121 "HasVectorUAMem", "true", 122 "Allow unaligned memory operands on vector/SIMD instructions">; 123 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 124 "Enable AES instructions", 125 [FeatureSSE2]>; 126 def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", 127 "Enable TBM instructions">; 128 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", 129 "Support MOVBE instruction">; 130 def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", 131 "Support RDRAND instruction">; 132 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", 133 "Support 16-bit floating point conversion instructions", 134 [FeatureAVX]>; 135 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true", 136 "Support FS/GS Base instructions">; 137 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true", 138 "Support LZCNT instruction">; 139 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true", 140 "Support BMI instructions">; 141 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true", 142 "Support BMI2 instructions">; 143 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true", 144 "Support RTM instructions">; 145 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true", 146 "Support HLE">; 147 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true", 148 "Support ADX instructions">; 149 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true", 150 "Enable SHA instructions", 151 [FeatureSSE2]>; 152 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", 153 "Support PRFCHW instructions">; 154 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", 155 "Support RDSEED instruction">; 156 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", 157 "Use LEA for adjusting the stack pointer">; 158 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb", 159 "HasSlowDivide", "true", 160 "Use small divide for positive values less than 256">; 161 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", 162 "PadShortFunctions", "true", 163 "Pad short functions">; 164 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect", 165 "CallRegIndirect", "true", 166 "Call register indirect">; 167 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", 168 "LEA instruction needs inputs at AG stage">; 169 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", 170 "LEA instruction with certain arguments is slow">; 171 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true", 172 "INC and DEC instructions are slower than ADD and SUB">; 173 174 //===----------------------------------------------------------------------===// 175 // X86 processors supported. 176 //===----------------------------------------------------------------------===// 177 178 include "X86Schedule.td" 179 180 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom", 181 "Intel Atom processors">; 182 def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM", 183 "Intel Silvermont processors">; 184 185 class Proc<string Name, list<SubtargetFeature> Features> 186 : ProcessorModel<Name, GenericModel, Features>; 187 188 def : Proc<"generic", []>; 189 def : Proc<"i386", []>; 190 def : Proc<"i486", []>; 191 def : Proc<"i586", []>; 192 def : Proc<"pentium", []>; 193 def : Proc<"pentium-mmx", [FeatureMMX]>; 194 def : Proc<"i686", []>; 195 def : Proc<"pentiumpro", [FeatureCMOV]>; 196 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>; 197 def : Proc<"pentium3", [FeatureSSE1]>; 198 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>; 199 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>; 200 def : Proc<"pentium4", [FeatureSSE2]>; 201 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>; 202 203 // Intel Core Duo. 204 def : ProcessorModel<"yonah", SandyBridgeModel, 205 [FeatureSSE3, FeatureSlowBTMem]>; 206 207 // NetBurst. 208 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>; 209 def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>; 210 211 // Intel Core 2 Solo/Duo. 212 def : ProcessorModel<"core2", SandyBridgeModel, 213 [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>; 214 def : ProcessorModel<"penryn", SandyBridgeModel, 215 [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>; 216 217 // Atom. 218 def : ProcessorModel<"atom", AtomModel, 219 [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B, 220 FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP, 221 FeatureSlowDivide, 222 FeatureCallRegIndirect, 223 FeatureLEAUsesAG, 224 FeaturePadShortFunctions]>; 225 226 // Atom Silvermont. 227 def : ProcessorModel<"slm", SLMModel, [ProcIntelSLM, 228 FeatureSSE42, FeatureCMPXCHG16B, 229 FeatureMOVBE, FeaturePOPCNT, 230 FeaturePCLMUL, FeatureAES, 231 FeatureCallRegIndirect, 232 FeaturePRFCHW, 233 FeatureSlowLEA, FeatureSlowIncDec, 234 FeatureSlowBTMem, FeatureFastUAMem]>; 235 // "Arrandale" along with corei3 and corei5 236 def : ProcessorModel<"corei7", SandyBridgeModel, 237 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem, 238 FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>; 239 240 def : ProcessorModel<"nehalem", SandyBridgeModel, 241 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem, 242 FeatureFastUAMem, FeaturePOPCNT]>; 243 // Westmere is a similar machine to nehalem with some additional features. 244 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge 245 def : ProcessorModel<"westmere", SandyBridgeModel, 246 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem, 247 FeatureFastUAMem, FeaturePOPCNT, FeatureAES, 248 FeaturePCLMUL]>; 249 // Sandy Bridge 250 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE, 251 // rather than a superset. 252 def : ProcessorModel<"corei7-avx", SandyBridgeModel, 253 [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem, 254 FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>; 255 // Ivy Bridge 256 def : ProcessorModel<"core-avx-i", SandyBridgeModel, 257 [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem, 258 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND, 259 FeatureF16C, FeatureFSGSBase]>; 260 261 // Haswell 262 def : ProcessorModel<"core-avx2", HaswellModel, 263 [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem, 264 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND, 265 FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, 266 FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM, 267 FeatureHLE]>; 268 269 // KNL 270 // FIXME: define KNL model 271 def : ProcessorModel<"knl", HaswellModel, 272 [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI, 273 FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT, 274 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C, 275 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI, 276 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE, 277 FeatureSlowIncDec]>; 278 279 def : Proc<"k6", [FeatureMMX]>; 280 def : Proc<"k6-2", [Feature3DNow]>; 281 def : Proc<"k6-3", [Feature3DNow]>; 282 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem, 283 FeatureSlowSHLD]>; 284 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem, 285 FeatureSlowSHLD]>; 286 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem, 287 FeatureSlowSHLD]>; 288 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem, 289 FeatureSlowSHLD]>; 290 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem, 291 FeatureSlowSHLD]>; 292 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit, 293 FeatureSlowBTMem, FeatureSlowSHLD]>; 294 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit, 295 FeatureSlowBTMem, FeatureSlowSHLD]>; 296 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit, 297 FeatureSlowBTMem, FeatureSlowSHLD]>; 298 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit, 299 FeatureSlowBTMem, FeatureSlowSHLD]>; 300 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B, 301 FeatureSlowBTMem, FeatureSlowSHLD]>; 302 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B, 303 FeatureSlowBTMem, FeatureSlowSHLD]>; 304 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B, 305 FeatureSlowBTMem, FeatureSlowSHLD]>; 306 def : Proc<"amdfam10", [FeatureSSE4A, 307 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT, 308 FeaturePOPCNT, FeatureSlowBTMem, 309 FeatureSlowSHLD]>; 310 // Bobcat 311 def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B, 312 FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT, 313 FeatureSlowSHLD]>; 314 // Jaguar 315 def : Proc<"btver2", [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B, 316 FeaturePRFCHW, FeatureAES, FeaturePCLMUL, 317 FeatureBMI, FeatureF16C, FeatureMOVBE, 318 FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD]>; 319 // Bulldozer 320 def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, 321 FeatureAES, FeaturePRFCHW, FeaturePCLMUL, 322 FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD]>; 323 // Piledriver 324 def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, 325 FeatureAES, FeaturePRFCHW, FeaturePCLMUL, 326 FeatureF16C, FeatureLZCNT, 327 FeaturePOPCNT, FeatureBMI, FeatureTBM, 328 FeatureFMA, FeatureSlowSHLD]>; 329 330 // Steamroller 331 def : Proc<"bdver3", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, 332 FeatureAES, FeaturePRFCHW, FeaturePCLMUL, 333 FeatureF16C, FeatureLZCNT, 334 FeaturePOPCNT, FeatureBMI, FeatureTBM, 335 FeatureFMA, FeatureFSGSBase]>; 336 337 // Excavator 338 def : Proc<"bdver4", [FeatureAVX2, FeatureXOP, FeatureFMA4, 339 FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW, 340 FeaturePCLMUL, FeatureF16C, FeatureLZCNT, 341 FeaturePOPCNT, FeatureBMI, FeatureBMI2, 342 FeatureTBM, FeatureFMA, FeatureFSGSBase]>; 343 344 def : Proc<"geode", [Feature3DNowA]>; 345 346 def : Proc<"winchip-c6", [FeatureMMX]>; 347 def : Proc<"winchip2", [Feature3DNow]>; 348 def : Proc<"c3", [Feature3DNow]>; 349 def : Proc<"c3-2", [FeatureSSE1]>; 350 351 // We also provide a generic 64-bit specific x86 processor model which tries to 352 // be good for modern chips without enabling instruction set encodings past the 353 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and 354 // modern 64-bit x86 chip, and enables features that are generally beneficial. 355 // 356 // We currently use the Sandy Bridge model as the default scheduling model as 357 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which 358 // covers a huge swath of x86 processors. If there are specific scheduling 359 // knobs which need to be tuned differently for AMD chips, we might consider 360 // forming a common base for them. 361 def : ProcessorModel<"x86-64", SandyBridgeModel, 362 [FeatureSSE2, Feature64Bit, FeatureSlowBTMem, 363 FeatureFastUAMem]>; 364 365 //===----------------------------------------------------------------------===// 366 // Register File Description 367 //===----------------------------------------------------------------------===// 368 369 include "X86RegisterInfo.td" 370 371 //===----------------------------------------------------------------------===// 372 // Instruction Descriptions 373 //===----------------------------------------------------------------------===// 374 375 include "X86InstrInfo.td" 376 377 def X86InstrInfo : InstrInfo; 378 379 //===----------------------------------------------------------------------===// 380 // Calling Conventions 381 //===----------------------------------------------------------------------===// 382 383 include "X86CallingConv.td" 384 385 386 //===----------------------------------------------------------------------===// 387 // Assembly Parser 388 //===----------------------------------------------------------------------===// 389 390 def ATTAsmParser : AsmParser { 391 string AsmParserClassName = "AsmParser"; 392 } 393 394 def ATTAsmParserVariant : AsmParserVariant { 395 int Variant = 0; 396 397 // Variant name. 398 string Name = "att"; 399 400 // Discard comments in assembly strings. 401 string CommentDelimiter = "#"; 402 403 // Recognize hard coded registers. 404 string RegisterPrefix = "%"; 405 } 406 407 def IntelAsmParserVariant : AsmParserVariant { 408 int Variant = 1; 409 410 // Variant name. 411 string Name = "intel"; 412 413 // Discard comments in assembly strings. 414 string CommentDelimiter = ";"; 415 416 // Recognize hard coded registers. 417 string RegisterPrefix = ""; 418 } 419 420 //===----------------------------------------------------------------------===// 421 // Assembly Printers 422 //===----------------------------------------------------------------------===// 423 424 // The X86 target supports two different syntaxes for emitting machine code. 425 // This is controlled by the -x86-asm-syntax={att|intel} 426 def ATTAsmWriter : AsmWriter { 427 string AsmWriterClassName = "ATTInstPrinter"; 428 int Variant = 0; 429 } 430 def IntelAsmWriter : AsmWriter { 431 string AsmWriterClassName = "IntelInstPrinter"; 432 int Variant = 1; 433 } 434 435 def X86 : Target { 436 // Information about the instructions... 437 let InstructionSet = X86InstrInfo; 438 let AssemblyParsers = [ATTAsmParser]; 439 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant]; 440 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; 441 } 442
