1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // X86 Instruction Format Definitions. 12 // 13 14 // Format specifies the encoding used by the instruction. This is part of the 15 // ad-hoc solution used to emit machine instruction encodings by our machine 16 // code emitter. 17 class Format<bits<7> val> { 18 bits<7> Value = val; 19 } 20 21 def Pseudo : Format<0>; def RawFrm : Format<1>; 22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; 23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; 24 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>; 25 def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>; 26 def RawFrmDstSrc: Format<10>; 27 def RawFrmImm8 : Format<11>; 28 def RawFrmImm16 : Format<12>; 29 def MRMXr : Format<14>; def MRMXm : Format<15>; 30 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; 31 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; 32 def MRM6r : Format<22>; def MRM7r : Format<23>; 33 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; 34 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; 35 def MRM6m : Format<30>; def MRM7m : Format<31>; 36 def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>; 37 def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>; 38 def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>; 39 def MRM_D0 : Format<41>; def MRM_D1 : Format<42>; def MRM_D4 : Format<43>; 40 def MRM_D5 : Format<44>; def MRM_D6 : Format<45>; def MRM_D8 : Format<46>; 41 def MRM_D9 : Format<47>; def MRM_DA : Format<48>; def MRM_DB : Format<49>; 42 def MRM_DC : Format<50>; def MRM_DD : Format<51>; def MRM_DE : Format<52>; 43 def MRM_DF : Format<53>; def MRM_E0 : Format<54>; def MRM_E1 : Format<55>; 44 def MRM_E2 : Format<56>; def MRM_E3 : Format<57>; def MRM_E4 : Format<58>; 45 def MRM_E5 : Format<59>; def MRM_E8 : Format<60>; def MRM_E9 : Format<61>; 46 def MRM_EA : Format<62>; def MRM_EB : Format<63>; def MRM_EC : Format<64>; 47 def MRM_ED : Format<65>; def MRM_EE : Format<66>; def MRM_F0 : Format<67>; 48 def MRM_F1 : Format<68>; def MRM_F2 : Format<69>; def MRM_F3 : Format<70>; 49 def MRM_F4 : Format<71>; def MRM_F5 : Format<72>; def MRM_F6 : Format<73>; 50 def MRM_F7 : Format<74>; def MRM_F8 : Format<75>; def MRM_F9 : Format<76>; 51 def MRM_FA : Format<77>; def MRM_FB : Format<78>; def MRM_FC : Format<79>; 52 def MRM_FD : Format<80>; def MRM_FE : Format<81>; def MRM_FF : Format<82>; 53 54 // ImmType - This specifies the immediate type used by an instruction. This is 55 // part of the ad-hoc solution used to emit machine instruction encodings by our 56 // machine code emitter. 57 class ImmType<bits<4> val> { 58 bits<4> Value = val; 59 } 60 def NoImm : ImmType<0>; 61 def Imm8 : ImmType<1>; 62 def Imm8PCRel : ImmType<2>; 63 def Imm16 : ImmType<3>; 64 def Imm16PCRel : ImmType<4>; 65 def Imm32 : ImmType<5>; 66 def Imm32PCRel : ImmType<6>; 67 def Imm32S : ImmType<7>; 68 def Imm64 : ImmType<8>; 69 70 // FPFormat - This specifies what form this FP instruction has. This is used by 71 // the Floating-Point stackifier pass. 72 class FPFormat<bits<3> val> { 73 bits<3> Value = val; 74 } 75 def NotFP : FPFormat<0>; 76 def ZeroArgFP : FPFormat<1>; 77 def OneArgFP : FPFormat<2>; 78 def OneArgFPRW : FPFormat<3>; 79 def TwoArgFP : FPFormat<4>; 80 def CompareFP : FPFormat<5>; 81 def CondMovFP : FPFormat<6>; 82 def SpecialFP : FPFormat<7>; 83 84 // Class specifying the SSE execution domain, used by the SSEDomainFix pass. 85 // Keep in sync with tables in X86InstrInfo.cpp. 86 class Domain<bits<2> val> { 87 bits<2> Value = val; 88 } 89 def GenericDomain : Domain<0>; 90 def SSEPackedSingle : Domain<1>; 91 def SSEPackedDouble : Domain<2>; 92 def SSEPackedInt : Domain<3>; 93 94 // Class specifying the vector form of the decompressed 95 // displacement of 8-bit. 96 class CD8VForm<bits<3> val> { 97 bits<3> Value = val; 98 } 99 def CD8VF : CD8VForm<0>; // v := VL 100 def CD8VH : CD8VForm<1>; // v := VL/2 101 def CD8VQ : CD8VForm<2>; // v := VL/4 102 def CD8VO : CD8VForm<3>; // v := VL/8 103 def CD8VT1 : CD8VForm<4>; // v := 1 104 def CD8VT2 : CD8VForm<5>; // v := 2 105 def CD8VT4 : CD8VForm<6>; // v := 4 106 def CD8VT8 : CD8VForm<7>; // v := 8 107 108 // Class specifying the prefix used an opcode extension. 109 class Prefix<bits<3> val> { 110 bits<3> Value = val; 111 } 112 def NoPrfx : Prefix<0>; 113 def PS : Prefix<1>; 114 def PD : Prefix<2>; 115 def XS : Prefix<3>; 116 def XD : Prefix<4>; 117 118 // Class specifying the opcode map. 119 class Map<bits<3> val> { 120 bits<3> Value = val; 121 } 122 def OB : Map<0>; 123 def TB : Map<1>; 124 def T8 : Map<2>; 125 def TA : Map<3>; 126 def XOP8 : Map<4>; 127 def XOP9 : Map<5>; 128 def XOPA : Map<6>; 129 130 // Class specifying the encoding 131 class Encoding<bits<2> val> { 132 bits<2> Value = val; 133 } 134 def EncNormal : Encoding<0>; 135 def EncVEX : Encoding<1>; 136 def EncXOP : Encoding<2>; 137 def EncEVEX : Encoding<3>; 138 139 // Operand size for encodings that change based on mode. 140 class OperandSize<bits<2> val> { 141 bits<2> Value = val; 142 } 143 def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix. 144 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode. 145 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode. 146 147 // Prefix byte classes which are used to indicate to the ad-hoc machine code 148 // emitter that various prefix bytes are required. 149 class OpSize16 { OperandSize OpSize = OpSize16; } 150 class OpSize32 { OperandSize OpSize = OpSize32; } 151 class AdSize { bit hasAdSizePrefix = 1; } 152 class REX_W { bit hasREX_WPrefix = 1; } 153 class LOCK { bit hasLockPrefix = 1; } 154 class REP { bit hasREPPrefix = 1; } 155 class TB { Map OpMap = TB; } 156 class T8 { Map OpMap = T8; } 157 class TA { Map OpMap = TA; } 158 class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; } 159 class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; } 160 class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; } 161 class OBXS { Prefix OpPrefix = XS; } 162 class PS : TB { Prefix OpPrefix = PS; } 163 class PD : TB { Prefix OpPrefix = PD; } 164 class XD : TB { Prefix OpPrefix = XD; } 165 class XS : TB { Prefix OpPrefix = XS; } 166 class T8PS : T8 { Prefix OpPrefix = PS; } 167 class T8PD : T8 { Prefix OpPrefix = PD; } 168 class T8XD : T8 { Prefix OpPrefix = XD; } 169 class T8XS : T8 { Prefix OpPrefix = XS; } 170 class TAPS : TA { Prefix OpPrefix = PS; } 171 class TAPD : TA { Prefix OpPrefix = PD; } 172 class TAXD : TA { Prefix OpPrefix = XD; } 173 class VEX { Encoding OpEnc = EncVEX; } 174 class VEX_W { bit hasVEX_WPrefix = 1; } 175 class VEX_4V : VEX { bit hasVEX_4V = 1; } 176 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3 = 1; } 177 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; } 178 class VEX_L { bit hasVEX_L = 1; } 179 class VEX_LIG { bit ignoresVEX_L = 1; } 180 class EVEX : VEX { Encoding OpEnc = EncEVEX; } 181 class EVEX_4V : VEX_4V { Encoding OpEnc = EncEVEX; } 182 class EVEX_K { bit hasEVEX_K = 1; } 183 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; } 184 class EVEX_B { bit hasEVEX_B = 1; } 185 class EVEX_RC { bit hasEVEX_RC = 1; } 186 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; } 187 class EVEX_CD8<int esize, CD8VForm form> { 188 bits<2> EVEX_CD8E = !if(!eq(esize, 8), 0b00, 189 !if(!eq(esize, 16), 0b01, 190 !if(!eq(esize, 32), 0b10, 191 !if(!eq(esize, 64), 0b11, ?)))); 192 bits<3> EVEX_CD8V = form.Value; 193 } 194 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; } 195 class MemOp4 { bit hasMemOp4Prefix = 1; } 196 class XOP { Encoding OpEnc = EncXOP; } 197 class XOP_4V : XOP { bit hasVEX_4V = 1; } 198 class XOP_4VOp3 : XOP { bit hasVEX_4VOp3 = 1; } 199 200 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, 201 string AsmStr, 202 InstrItinClass itin, 203 Domain d = GenericDomain> 204 : Instruction { 205 let Namespace = "X86"; 206 207 bits<8> Opcode = opcod; 208 Format Form = f; 209 bits<7> FormBits = Form.Value; 210 ImmType ImmT = i; 211 212 dag OutOperandList = outs; 213 dag InOperandList = ins; 214 string AsmString = AsmStr; 215 216 // If this is a pseudo instruction, mark it isCodeGenOnly. 217 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 218 219 let Itinerary = itin; 220 221 // 222 // Attributes specific to X86 instructions... 223 // 224 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's 225 // isCodeGenonly. Needed to hide an ambiguous 226 // AsmString from the parser, but still disassemble. 227 228 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change 229 // based on operand size of the mode 230 bits<2> OpSizeBits = OpSize.Value; 231 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix? 232 233 Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have? 234 bits<3> OpPrefixBits = OpPrefix.Value; 235 Map OpMap = OB; // Which opcode map does this inst have? 236 bits<3> OpMapBits = OpMap.Value; 237 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix? 238 FPFormat FPForm = NotFP; // What flavor of FP instruction is this? 239 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? 240 Domain ExeDomain = d; 241 bit hasREPPrefix = 0; // Does this inst have a REP prefix? 242 Encoding OpEnc = EncNormal; // Encoding used by this instruction 243 bits<2> OpEncBits = OpEnc.Value; 244 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field? 245 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field? 246 bit hasVEX_4VOp3 = 0; // Does this inst require the VEX.VVVV field to 247 // encode the third operand? 248 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register 249 // to be encoded in a immediate field? 250 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers? 251 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit 252 bit hasEVEX_K = 0; // Does this inst require masking? 253 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field? 254 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field? 255 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field? 256 bits<2> EVEX_CD8E = 0; // Compressed disp8 form - element-size. 257 bits<3> EVEX_CD8V = 0; // Compressed disp8 form - vector-width. 258 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding? 259 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands 260 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction. 261 262 // TSFlags layout should be kept in sync with X86InstrInfo.h. 263 let TSFlags{6-0} = FormBits; 264 let TSFlags{8-7} = OpSizeBits; 265 let TSFlags{9} = hasAdSizePrefix; 266 let TSFlags{12-10} = OpPrefixBits; 267 let TSFlags{15-13} = OpMapBits; 268 let TSFlags{16} = hasREX_WPrefix; 269 let TSFlags{20-17} = ImmT.Value; 270 let TSFlags{23-21} = FPForm.Value; 271 let TSFlags{24} = hasLockPrefix; 272 let TSFlags{25} = hasREPPrefix; 273 let TSFlags{27-26} = ExeDomain.Value; 274 let TSFlags{29-28} = OpEncBits; 275 let TSFlags{37-30} = Opcode; 276 let TSFlags{38} = hasVEX_WPrefix; 277 let TSFlags{39} = hasVEX_4V; 278 let TSFlags{40} = hasVEX_4VOp3; 279 let TSFlags{41} = hasVEX_i8ImmReg; 280 let TSFlags{42} = hasVEX_L; 281 let TSFlags{43} = ignoresVEX_L; 282 let TSFlags{44} = hasEVEX_K; 283 let TSFlags{45} = hasEVEX_Z; 284 let TSFlags{46} = hasEVEX_L2; 285 let TSFlags{47} = hasEVEX_B; 286 let TSFlags{49-48} = EVEX_CD8E; 287 let TSFlags{52-50} = EVEX_CD8V; 288 let TSFlags{53} = has3DNow0F0FOpcode; 289 let TSFlags{54} = hasMemOp4Prefix; 290 let TSFlags{55} = hasEVEX_RC; 291 } 292 293 class PseudoI<dag oops, dag iops, list<dag> pattern> 294 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> { 295 let Pattern = pattern; 296 } 297 298 class I<bits<8> o, Format f, dag outs, dag ins, string asm, 299 list<dag> pattern, InstrItinClass itin = NoItinerary, 300 Domain d = GenericDomain> 301 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> { 302 let Pattern = pattern; 303 let CodeSize = 3; 304 } 305 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm, 306 list<dag> pattern, InstrItinClass itin = NoItinerary, 307 Domain d = GenericDomain> 308 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> { 309 let Pattern = pattern; 310 let CodeSize = 3; 311 } 312 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 313 list<dag> pattern, InstrItinClass itin = NoItinerary> 314 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> { 315 let Pattern = pattern; 316 let CodeSize = 3; 317 } 318 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, 319 list<dag> pattern, InstrItinClass itin = NoItinerary> 320 : X86Inst<o, f, Imm16, outs, ins, asm, itin> { 321 let Pattern = pattern; 322 let CodeSize = 3; 323 } 324 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, 325 list<dag> pattern, InstrItinClass itin = NoItinerary> 326 : X86Inst<o, f, Imm32, outs, ins, asm, itin> { 327 let Pattern = pattern; 328 let CodeSize = 3; 329 } 330 class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm, 331 list<dag> pattern, InstrItinClass itin = NoItinerary> 332 : X86Inst<o, f, Imm32S, outs, ins, asm, itin> { 333 let Pattern = pattern; 334 let CodeSize = 3; 335 } 336 337 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 338 list<dag> pattern, InstrItinClass itin = NoItinerary> 339 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> { 340 let Pattern = pattern; 341 let CodeSize = 3; 342 } 343 344 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 345 list<dag> pattern, InstrItinClass itin = NoItinerary> 346 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> { 347 let Pattern = pattern; 348 let CodeSize = 3; 349 } 350 351 // FPStack Instruction Templates: 352 // FPI - Floating Point Instruction template. 353 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm, 354 InstrItinClass itin = NoItinerary> 355 : I<o, F, outs, ins, asm, [], itin> {} 356 357 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated. 358 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern, 359 InstrItinClass itin = NoItinerary> 360 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> { 361 let FPForm = fp; 362 let Pattern = pattern; 363 } 364 365 // Templates for instructions that use a 16- or 32-bit segmented address as 366 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP) 367 // 368 // Iseg16 - 16-bit segment selector, 16-bit offset 369 // Iseg32 - 16-bit segment selector, 32-bit offset 370 371 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm, 372 list<dag> pattern, InstrItinClass itin = NoItinerary> 373 : X86Inst<o, f, Imm16, outs, ins, asm, itin> { 374 let Pattern = pattern; 375 let CodeSize = 3; 376 } 377 378 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm, 379 list<dag> pattern, InstrItinClass itin = NoItinerary> 380 : X86Inst<o, f, Imm32, outs, ins, asm, itin> { 381 let Pattern = pattern; 382 let CodeSize = 3; 383 } 384 385 // SI - SSE 1 & 2 scalar instructions 386 class SI<bits<8> o, Format F, dag outs, dag ins, string asm, 387 list<dag> pattern, InstrItinClass itin = NoItinerary> 388 : I<o, F, outs, ins, asm, pattern, itin> { 389 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 390 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], 391 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], 392 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], 393 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 394 [UseSSE1]))))); 395 396 // AVX instructions have a 'v' prefix in the mnemonic 397 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 398 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 399 asm)); 400 } 401 402 // SIi8 - SSE 1 & 2 scalar instructions 403 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 404 list<dag> pattern, InstrItinClass itin = NoItinerary> 405 : Ii8<o, F, outs, ins, asm, pattern, itin> { 406 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 407 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], 408 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], 409 [UseSSE2]))); 410 411 // AVX instructions have a 'v' prefix in the mnemonic 412 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 413 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 414 asm)); 415 } 416 417 // PI - SSE 1 & 2 packed instructions 418 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, 419 InstrItinClass itin, Domain d> 420 : I<o, F, outs, ins, asm, pattern, itin, d> { 421 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 422 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], 423 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 424 [UseSSE1]))); 425 426 // AVX instructions have a 'v' prefix in the mnemonic 427 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 428 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 429 asm)); 430 } 431 432 // MMXPI - SSE 1 & 2 packed instructions with MMX operands 433 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, 434 InstrItinClass itin, Domain d> 435 : I<o, F, outs, ins, asm, pattern, itin, d> { 436 let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasSSE2], 437 [HasSSE1]); 438 } 439 440 // PIi8 - SSE 1 & 2 packed instructions with immediate 441 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 442 list<dag> pattern, InstrItinClass itin, Domain d> 443 : Ii8<o, F, outs, ins, asm, pattern, itin, d> { 444 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 445 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], 446 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 447 [UseSSE1]))); 448 449 // AVX instructions have a 'v' prefix in the mnemonic 450 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 451 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 452 asm)); 453 } 454 455 // SSE1 Instruction Templates: 456 // 457 // SSI - SSE1 instructions with XS prefix. 458 // PSI - SSE1 instructions with PS prefix. 459 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix. 460 // VSSI - SSE1 instructions with XS prefix in AVX form. 461 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single. 462 463 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, 464 list<dag> pattern, InstrItinClass itin = NoItinerary> 465 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>; 466 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 467 list<dag> pattern, InstrItinClass itin = NoItinerary> 468 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>; 469 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, 470 list<dag> pattern, InstrItinClass itin = NoItinerary> 471 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS, 472 Requires<[UseSSE1]>; 473 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 474 list<dag> pattern, InstrItinClass itin = NoItinerary> 475 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS, 476 Requires<[UseSSE1]>; 477 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm, 478 list<dag> pattern, InstrItinClass itin = NoItinerary> 479 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS, 480 Requires<[HasAVX]>; 481 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm, 482 list<dag> pattern, InstrItinClass itin = NoItinerary> 483 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, PS, 484 Requires<[HasAVX]>; 485 486 // SSE2 Instruction Templates: 487 // 488 // SDI - SSE2 instructions with XD prefix. 489 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. 490 // S2SI - SSE2 instructions with XS prefix. 491 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. 492 // PDI - SSE2 instructions with PD prefix, packed double domain. 493 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix. 494 // VSDI - SSE2 scalar instructions with XD prefix in AVX form. 495 // VPDI - SSE2 vector instructions with PD prefix in AVX form, 496 // packed double domain. 497 // VS2I - SSE2 scalar instructions with PD prefix in AVX form. 498 // S2I - SSE2 scalar instructions with PD prefix. 499 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as 500 // MMX operands. 501 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as 502 // MMX operands. 503 504 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, 505 list<dag> pattern, InstrItinClass itin = NoItinerary> 506 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>; 507 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 508 list<dag> pattern, InstrItinClass itin = NoItinerary> 509 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>; 510 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm, 511 list<dag> pattern, InstrItinClass itin = NoItinerary> 512 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>; 513 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 514 list<dag> pattern, InstrItinClass itin = NoItinerary> 515 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>; 516 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, 517 list<dag> pattern, InstrItinClass itin = NoItinerary> 518 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD, 519 Requires<[UseSSE2]>; 520 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 521 list<dag> pattern, InstrItinClass itin = NoItinerary> 522 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD, 523 Requires<[UseSSE2]>; 524 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm, 525 list<dag> pattern, InstrItinClass itin = NoItinerary> 526 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD, 527 Requires<[UseAVX]>; 528 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm, 529 list<dag> pattern, InstrItinClass itin = NoItinerary> 530 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS, 531 Requires<[HasAVX]>; 532 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm, 533 list<dag> pattern, InstrItinClass itin = NoItinerary> 534 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, 535 PD, Requires<[HasAVX]>; 536 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 537 list<dag> pattern, InstrItinClass itin = NoItinerary> 538 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD, 539 Requires<[UseAVX]>; 540 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm, 541 list<dag> pattern, InstrItinClass itin = NoItinerary> 542 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>; 543 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 544 list<dag> pattern, InstrItinClass itin = NoItinerary> 545 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>; 546 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 547 list<dag> pattern, InstrItinClass itin = NoItinerary> 548 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>; 549 550 // SSE3 Instruction Templates: 551 // 552 // S3I - SSE3 instructions with PD prefixes. 553 // S3SI - SSE3 instructions with XS prefix. 554 // S3DI - SSE3 instructions with XD prefix. 555 556 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, 557 list<dag> pattern, InstrItinClass itin = NoItinerary> 558 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS, 559 Requires<[UseSSE3]>; 560 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, 561 list<dag> pattern, InstrItinClass itin = NoItinerary> 562 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD, 563 Requires<[UseSSE3]>; 564 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, 565 list<dag> pattern, InstrItinClass itin = NoItinerary> 566 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD, 567 Requires<[UseSSE3]>; 568 569 570 // SSSE3 Instruction Templates: 571 // 572 // SS38I - SSSE3 instructions with T8 prefix. 573 // SS3AI - SSSE3 instructions with TA prefix. 574 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands. 575 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands. 576 // 577 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version 578 // uses the MMX registers. The 64-bit versions are grouped with the MMX 579 // classes. They need to be enabled even if AVX is enabled. 580 581 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm, 582 list<dag> pattern, InstrItinClass itin = NoItinerary> 583 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 584 Requires<[UseSSSE3]>; 585 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, 586 list<dag> pattern, InstrItinClass itin = NoItinerary> 587 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 588 Requires<[UseSSSE3]>; 589 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm, 590 list<dag> pattern, InstrItinClass itin = NoItinerary> 591 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PS, 592 Requires<[HasSSSE3]>; 593 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, 594 list<dag> pattern, InstrItinClass itin = NoItinerary> 595 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPS, 596 Requires<[HasSSSE3]>; 597 598 // SSE4.1 Instruction Templates: 599 // 600 // SS48I - SSE 4.1 instructions with T8 prefix. 601 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. 602 // 603 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm, 604 list<dag> pattern, InstrItinClass itin = NoItinerary> 605 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 606 Requires<[UseSSE41]>; 607 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 608 list<dag> pattern, InstrItinClass itin = NoItinerary> 609 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 610 Requires<[UseSSE41]>; 611 612 // SSE4.2 Instruction Templates: 613 // 614 // SS428I - SSE 4.2 instructions with T8 prefix. 615 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm, 616 list<dag> pattern, InstrItinClass itin = NoItinerary> 617 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 618 Requires<[UseSSE42]>; 619 620 // SS42FI - SSE 4.2 instructions with T8XD prefix. 621 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns. 622 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm, 623 list<dag> pattern, InstrItinClass itin = NoItinerary> 624 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>; 625 626 // SS42AI = SSE 4.2 instructions with TA prefix 627 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm, 628 list<dag> pattern, InstrItinClass itin = NoItinerary> 629 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 630 Requires<[UseSSE42]>; 631 632 // AVX Instruction Templates: 633 // Instructions introduced in AVX (no SSE equivalent forms) 634 // 635 // AVX8I - AVX instructions with T8PD prefix. 636 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8. 637 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm, 638 list<dag> pattern, InstrItinClass itin = NoItinerary> 639 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 640 Requires<[HasAVX]>; 641 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 642 list<dag> pattern, InstrItinClass itin = NoItinerary> 643 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 644 Requires<[HasAVX]>; 645 646 // AVX2 Instruction Templates: 647 // Instructions introduced in AVX2 (no SSE equivalent forms) 648 // 649 // AVX28I - AVX2 instructions with T8PD prefix. 650 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8. 651 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm, 652 list<dag> pattern, InstrItinClass itin = NoItinerary> 653 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 654 Requires<[HasAVX2]>; 655 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 656 list<dag> pattern, InstrItinClass itin = NoItinerary> 657 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 658 Requires<[HasAVX2]>; 659 660 661 // AVX-512 Instruction Templates: 662 // Instructions introduced in AVX-512 (no SSE equivalent forms) 663 // 664 // AVX5128I - AVX-512 instructions with T8PD prefix. 665 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8. 666 // AVX512PDI - AVX-512 instructions with PD, double packed. 667 // AVX512PSI - AVX-512 instructions with PS, single packed. 668 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes. 669 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain. 670 // AVX512BI - AVX-512 instructions with PD, int packed domain. 671 // AVX512SI - AVX-512 scalar instructions with PD prefix. 672 673 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm, 674 list<dag> pattern, InstrItinClass itin = NoItinerary> 675 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 676 Requires<[HasAVX512]>; 677 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm, 678 list<dag> pattern, InstrItinClass itin = NoItinerary> 679 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS, 680 Requires<[HasAVX512]>; 681 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm, 682 list<dag> pattern, InstrItinClass itin = NoItinerary> 683 : I<o, F, outs, ins, asm, pattern, itin>, XS, 684 Requires<[HasAVX512]>; 685 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm, 686 list<dag> pattern, InstrItinClass itin = NoItinerary> 687 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD, 688 Requires<[HasAVX512]>; 689 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm, 690 list<dag> pattern, InstrItinClass itin = NoItinerary> 691 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD, 692 Requires<[HasAVX512]>; 693 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 694 list<dag> pattern, InstrItinClass itin = NoItinerary> 695 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD, 696 Requires<[HasAVX512]>; 697 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 698 list<dag> pattern, InstrItinClass itin = NoItinerary> 699 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 700 Requires<[HasAVX512]>; 701 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm, 702 list<dag> pattern, InstrItinClass itin = NoItinerary> 703 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, 704 Requires<[HasAVX512]>; 705 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm, 706 list<dag> pattern, InstrItinClass itin = NoItinerary> 707 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD, 708 Requires<[HasAVX512]>; 709 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm, 710 list<dag> pattern, InstrItinClass itin = NoItinerary> 711 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS, 712 Requires<[HasAVX512]>; 713 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 714 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary> 715 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>; 716 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm, 717 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary> 718 : I<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>; 719 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm, 720 list<dag>pattern, InstrItinClass itin = NoItinerary> 721 : I<o, F, outs, ins, asm, pattern, itin>, T8PD, 722 EVEX_4V, Requires<[HasAVX512]>; 723 724 // AES Instruction Templates: 725 // 726 // AES8I 727 // These use the same encoding as the SSE4.2 T8 and TA encodings. 728 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm, 729 list<dag>pattern, InstrItinClass itin = IIC_AES> 730 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, 731 Requires<[HasAES]>; 732 733 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm, 734 list<dag> pattern, InstrItinClass itin = NoItinerary> 735 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 736 Requires<[HasAES]>; 737 738 // PCLMUL Instruction Templates 739 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 740 list<dag>pattern, InstrItinClass itin = NoItinerary> 741 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 742 Requires<[HasPCLMUL]>; 743 744 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 745 list<dag>pattern, InstrItinClass itin = NoItinerary> 746 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 747 VEX_4V, Requires<[HasAVX, HasPCLMUL]>; 748 749 // FMA3 Instruction Templates 750 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm, 751 list<dag>pattern, InstrItinClass itin = NoItinerary> 752 : I<o, F, outs, ins, asm, pattern, itin>, T8PD, 753 VEX_4V, FMASC, Requires<[HasFMA]>; 754 755 // FMA4 Instruction Templates 756 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm, 757 list<dag>pattern, InstrItinClass itin = NoItinerary> 758 : Ii8<o, F, outs, ins, asm, pattern, itin>, TAPD, 759 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>; 760 761 // XOP 2, 3 and 4 Operand Instruction Template 762 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm, 763 list<dag> pattern, InstrItinClass itin = NoItinerary> 764 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, 765 XOP9, Requires<[HasXOP]>; 766 767 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte 768 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm, 769 list<dag> pattern, InstrItinClass itin = NoItinerary> 770 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, 771 XOP8, Requires<[HasXOP]>; 772 773 // XOP 5 operand instruction (VEX encoding!) 774 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm, 775 list<dag>pattern, InstrItinClass itin = NoItinerary> 776 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, 777 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>; 778 779 // X86-64 Instruction templates... 780 // 781 782 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, 783 list<dag> pattern, InstrItinClass itin = NoItinerary> 784 : I<o, F, outs, ins, asm, pattern, itin>, REX_W; 785 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm, 786 list<dag> pattern, InstrItinClass itin = NoItinerary> 787 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W; 788 class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm, 789 list<dag> pattern, InstrItinClass itin = NoItinerary> 790 : Ii16<o, F, outs, ins, asm, pattern, itin>, REX_W; 791 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm, 792 list<dag> pattern, InstrItinClass itin = NoItinerary> 793 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W; 794 class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm, 795 list<dag> pattern, InstrItinClass itin = NoItinerary> 796 : Ii32S<o, F, outs, ins, asm, pattern, itin>, REX_W; 797 798 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm, 799 list<dag> pattern, InstrItinClass itin = NoItinerary> 800 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W { 801 let Pattern = pattern; 802 let CodeSize = 3; 803 } 804 805 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm, 806 list<dag> pattern, InstrItinClass itin = NoItinerary> 807 : X86Inst<o, f, Imm64, outs, ins, asm, itin> { 808 let Pattern = pattern; 809 let CodeSize = 3; 810 } 811 812 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 813 list<dag> pattern, InstrItinClass itin = NoItinerary> 814 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W; 815 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 816 list<dag> pattern, InstrItinClass itin = NoItinerary> 817 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W; 818 819 // MMX Instruction templates 820 // 821 822 // MMXI - MMX instructions with TB prefix. 823 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode. 824 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode. 825 // MMX2I - MMX / SSE2 instructions with PD prefix. 826 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. 827 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. 828 // MMXID - MMX instructions with XD prefix. 829 // MMXIS - MMX instructions with XS prefix. 830 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, 831 list<dag> pattern, InstrItinClass itin = NoItinerary> 832 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>; 833 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm, 834 list<dag> pattern, InstrItinClass itin = NoItinerary> 835 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,Not64BitMode]>; 836 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm, 837 list<dag> pattern, InstrItinClass itin = NoItinerary> 838 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,In64BitMode]>; 839 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, 840 list<dag> pattern, InstrItinClass itin = NoItinerary> 841 : I<o, F, outs, ins, asm, pattern, itin>, PS, REX_W, Requires<[HasMMX]>; 842 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, 843 list<dag> pattern, InstrItinClass itin = NoItinerary> 844 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>; 845 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 846 list<dag> pattern, InstrItinClass itin = NoItinerary> 847 : Ii8<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>; 848 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, 849 list<dag> pattern, InstrItinClass itin = NoItinerary> 850 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>; 851 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, 852 list<dag> pattern, InstrItinClass itin = NoItinerary> 853 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>; 854
