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      1 //===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file describes the X86 instructions that are generally used in
     11 // privileged modes.  These are not typically used by the compiler, but are
     12 // supported for the assembler and disassembler.
     13 //
     14 //===----------------------------------------------------------------------===//
     15 
     16 let SchedRW = [WriteSystem] in {
     17 let Defs = [RAX, RDX] in
     18   def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
     19               TB;
     20 
     21 let Defs = [RAX, RCX, RDX] in
     22   def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
     23 
     24 // CPU flow control instructions
     25 
     26 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
     27   def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
     28   def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
     29 }
     30 
     31 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
     32 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
     33 
     34 // Interrupt and SysCall Instructions.
     35 let Uses = [EFLAGS] in
     36   def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
     37 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
     38               [(int_x86_int (i8 3))], IIC_INT3>;
     39 } // SchedRW
     40 
     41 def : Pat<(debugtrap),
     42           (INT3)>;
     43 
     44 // The long form of "int $3" turns into int3 as a size optimization.
     45 // FIXME: This doesn't work because InstAlias can't match immediate constants.
     46 //def : InstAlias<"int\t$3", (INT3)>;
     47 
     48 let SchedRW = [WriteSystem] in {
     49 
     50 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
     51               [(int_x86_int imm:$trap)], IIC_INT>;
     52 
     53 
     54 def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
     55 def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
     56 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
     57                Requires<[In64BitMode]>;
     58 
     59 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
     60                  IIC_SYS_ENTER_EXIT>, TB;
     61 
     62 def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
     63                  IIC_SYS_ENTER_EXIT>, TB;
     64 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [],
     65                  IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;
     66 
     67 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize16;
     68 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>,
     69              OpSize32;
     70 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
     71              Requires<[In64BitMode]>;
     72 } // SchedRW
     73 
     74 
     75 //===----------------------------------------------------------------------===//
     76 //  Input/Output Instructions.
     77 //
     78 let SchedRW = [WriteSystem] in {
     79 let Defs = [AL], Uses = [DX] in
     80 def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
     81                "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
     82 let Defs = [AX], Uses = [DX] in
     83 def IN16rr : I<0xED, RawFrm, (outs), (ins),
     84                "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>,  OpSize16;
     85 let Defs = [EAX], Uses = [DX] in
     86 def IN32rr : I<0xED, RawFrm, (outs), (ins),
     87                "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
     88 
     89 let Defs = [AL] in
     90 def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
     91                   "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
     92 let Defs = [AX] in
     93 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
     94                   "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
     95 let Defs = [EAX] in
     96 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
     97                   "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
     98 
     99 let Uses = [DX, AL] in
    100 def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
    101                 "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
    102 let Uses = [DX, AX] in
    103 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
    104                 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
    105 let Uses = [DX, EAX] in
    106 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
    107                 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
    108 
    109 let Uses = [AL] in
    110 def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
    111                    "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
    112 let Uses = [AX] in
    113 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
    114                    "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
    115 let Uses = [EAX] in
    116 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
    117                   "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
    118 
    119 } // SchedRW
    120 
    121 //===----------------------------------------------------------------------===//
    122 // Moves to and from debug registers
    123 
    124 let SchedRW = [WriteSystem] in {
    125 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
    126                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
    127                 Requires<[Not64BitMode]>;
    128 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
    129                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
    130                 Requires<[In64BitMode]>;
    131 
    132 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
    133                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
    134                 Requires<[Not64BitMode]>;
    135 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
    136                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
    137                 Requires<[In64BitMode]>;
    138 } // SchedRW
    139 
    140 //===----------------------------------------------------------------------===//
    141 // Moves to and from control registers
    142 
    143 let SchedRW = [WriteSystem] in {
    144 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
    145                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
    146                 Requires<[Not64BitMode]>;
    147 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
    148                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
    149                 Requires<[In64BitMode]>;
    150 
    151 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
    152                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
    153                 Requires<[Not64BitMode]>;
    154 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
    155                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
    156                 Requires<[In64BitMode]>;
    157 } // SchedRW
    158 
    159 //===----------------------------------------------------------------------===//
    160 // Segment override instruction prefixes
    161 
    162 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
    163 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
    164 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
    165 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
    166 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
    167 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
    168 
    169 
    170 //===----------------------------------------------------------------------===//
    171 // Moves to and from segment registers.
    172 //
    173 
    174 let SchedRW = [WriteMove] in {
    175 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
    176                 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
    177 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
    178                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
    179 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
    180                  "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
    181 
    182 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
    183                 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
    184 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
    185                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
    186 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
    187                  "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
    188 
    189 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
    190                 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
    191 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
    192                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
    193 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
    194                  "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
    195 
    196 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
    197                 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
    198 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
    199                 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
    200 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
    201                  "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
    202 } // SchedRW
    203 
    204 //===----------------------------------------------------------------------===//
    205 // Segmentation support instructions.
    206 
    207 let SchedRW = [WriteSystem] in {
    208 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
    209 
    210 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 
    211                 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
    212                 OpSize16;
    213 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
    214                 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
    215                 OpSize16;
    216 
    217 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
    218 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 
    219                 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
    220                 OpSize32;
    221 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
    222                 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
    223                 OpSize32;
    224 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
    225 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 
    226                  "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
    227 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
    228                  "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
    229 
    230 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
    231                 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
    232                 OpSize16;
    233 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
    234                 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
    235                 OpSize16;
    236 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
    237                 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
    238                 OpSize32;
    239 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
    240                 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
    241                 OpSize32;
    242 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
    243                  "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB; 
    244 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
    245                  "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
    246 
    247 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
    248                [], IIC_INVLPG>, TB;
    249 
    250 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
    251                "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
    252 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
    253                "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
    254 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
    255                 "str{q}\t$dst", [], IIC_STR>, TB;
    256 def STRm   : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
    257                "str{w}\t$dst", [], IIC_STR>, TB;
    258 
    259 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
    260              "ltr{w}\t$src", [], IIC_LTR>, TB;
    261 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
    262              "ltr{w}\t$src", [], IIC_LTR>, TB;
    263              
    264 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
    265                  "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
    266                  OpSize16, Requires<[Not64BitMode]>;
    267 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
    268                  "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
    269                  OpSize32, Requires<[Not64BitMode]>;
    270 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
    271                  "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
    272                  OpSize16, Requires<[Not64BitMode]>;
    273 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
    274                  "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
    275                  OpSize32, Requires<[Not64BitMode]>;
    276 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
    277                  "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
    278                  OpSize16, Requires<[Not64BitMode]>;
    279 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
    280                  "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
    281                  OpSize32, Requires<[Not64BitMode]>;
    282 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
    283                  "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
    284                  OpSize16, Requires<[Not64BitMode]>;
    285 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
    286                  "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
    287                  OpSize32, Requires<[Not64BitMode]>;
    288 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
    289                  "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
    290 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
    291                  "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
    292                OpSize32, Requires<[Not64BitMode]>;
    293 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
    294                  "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
    295 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
    296                  "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
    297                OpSize32, Requires<[Not64BitMode]>;
    298 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
    299                  "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
    300                OpSize32, Requires<[In64BitMode]>;
    301 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
    302                  "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
    303                OpSize32, Requires<[In64BitMode]>;
    304 
    305 // No "pop cs" instruction.
    306 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
    307                 "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
    308               OpSize16, Requires<[Not64BitMode]>;
    309 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
    310                 "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
    311               OpSize32, Requires<[Not64BitMode]>;
    312 
    313 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
    314                 "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
    315               OpSize16, Requires<[Not64BitMode]>;
    316 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
    317                 "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
    318               OpSize32, Requires<[Not64BitMode]>;
    319 
    320 def POPES16 : I<0x07, RawFrm, (outs), (ins),
    321                 "pop{w}\t{%es|es}", [], IIC_POP_SR>,
    322               OpSize16, Requires<[Not64BitMode]>;
    323 def POPES32 : I<0x07, RawFrm, (outs), (ins),
    324                 "pop{l}\t{%es|es}", [], IIC_POP_SR>,
    325               OpSize32, Requires<[Not64BitMode]>;
    326 
    327 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
    328                 "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
    329 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
    330                 "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
    331               OpSize32, Requires<[Not64BitMode]>;
    332 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
    333                 "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB,
    334               OpSize32, Requires<[In64BitMode]>;
    335 
    336 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
    337                 "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
    338 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
    339                 "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
    340               OpSize32, Requires<[Not64BitMode]>;
    341 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
    342                 "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB,
    343               OpSize32, Requires<[In64BitMode]>;
    344 
    345 
    346 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
    347                 "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
    348 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
    349                 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
    350                 
    351 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
    352                 "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
    353 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
    354                 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
    355 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
    356                  "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
    357                 
    358 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
    359                 "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
    360 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
    361                 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
    362                 
    363 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
    364                 "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
    365 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
    366                 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
    367 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
    368                  "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
    369                 
    370 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
    371                 "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
    372 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
    373                 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
    374                 
    375 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
    376                  "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
    377 
    378 
    379 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
    380               "verr\t$seg", [], IIC_VERR>, TB;
    381 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
    382               "verr\t$seg", [], IIC_VERR>, TB;
    383 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
    384               "verw\t$seg", [], IIC_VERW_MEM>, TB;
    385 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
    386               "verw\t$seg", [], IIC_VERW_REG>, TB;
    387 } // SchedRW
    388 
    389 //===----------------------------------------------------------------------===//
    390 // Descriptor-table support instructions
    391 
    392 let SchedRW = [WriteSystem] in {
    393 def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
    394               "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
    395 def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
    396               "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
    397 def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
    398               "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
    399 def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
    400               "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
    401 def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
    402               "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
    403 def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
    404               "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
    405 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
    406                 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
    407 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
    408                 "sldt{w}\t$dst", [], IIC_SLDT>, TB;
    409 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
    410                 "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
    411                 
    412 // LLDT is not interpreted specially in 64-bit mode because there is no sign
    413 //   extension.
    414 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
    415                  "sldt{q}\t$dst", [], IIC_SLDT>, TB;
    416 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
    417                  "sldt{q}\t$dst", [], IIC_SLDT>, TB;
    418 
    419 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
    420               "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
    421 def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
    422               "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
    423 def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
    424               "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
    425 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
    426               "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
    427 def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
    428               "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
    429 def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
    430               "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
    431 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
    432                 "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
    433 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
    434                 "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
    435 } // SchedRW
    436 
    437 //===----------------------------------------------------------------------===//
    438 // Specialized register support
    439 let SchedRW = [WriteSystem] in {
    440 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
    441 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
    442 
    443 let Defs = [RAX, RDX], Uses = [ECX] in
    444   def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)], IIC_RDPMC>,
    445               TB;
    446 
    447 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins), 
    448                 "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
    449 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins), 
    450                 "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
    451 // no m form encodable; use SMSW16m
    452 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins), 
    453                  "smsw{q}\t$dst", [], IIC_SMSW>, TB;
    454 
    455 // For memory operands, there is only a 16-bit form
    456 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
    457                 "smsw{w}\t$dst", [], IIC_SMSW>, TB;
    458 
    459 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
    460                 "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
    461 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
    462                 "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
    463 
    464 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
    465   def CPUID32 : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB,
    466   Requires<[Not64BitMode]>;
    467 let Defs = [RAX, RBX, RCX, RDX], Uses = [RAX, RCX] in
    468   def CPUID64 : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB,
    469   Requires<[In64BitMode]>;
    470 } // SchedRW
    471 
    472 //===----------------------------------------------------------------------===//
    473 // Cache instructions
    474 let SchedRW = [WriteSystem] in {
    475 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
    476 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
    477 } // SchedRW
    478 
    479 //===----------------------------------------------------------------------===//
    480 // XSAVE instructions
    481 let SchedRW = [WriteSystem] in {
    482 let Defs = [RDX, RAX], Uses = [RCX] in
    483   def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
    484 
    485 let Uses = [RDX, RAX, RCX] in
    486   def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
    487 
    488 let Uses = [RDX, RAX] in {
    489   def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
    490                "xsave\t$dst", []>, TB;
    491   def XSAVE64 : RI<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
    492                  "xsave{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
    493   def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
    494                "xrstor\t$dst", []>, TB;
    495   def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
    496                  "xrstor{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
    497   def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
    498                   "xsaveopt\t$dst", []>, TB;
    499   def XSAVEOPT64 : RI<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
    500                     "xsaveopt{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
    501 }
    502 } // SchedRW
    503 
    504 //===----------------------------------------------------------------------===//
    505 // VIA PadLock crypto instructions
    506 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
    507   def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
    508 
    509 def : InstAlias<"xstorerng", (XSTORE)>;
    510 
    511 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
    512   def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
    513   def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
    514   def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
    515   def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
    516   def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
    517 }
    518 
    519 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
    520   def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
    521   def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
    522 }
    523 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
    524   def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
    525 
    526 //===----------------------------------------------------------------------===//
    527 // FS/GS Base Instructions
    528 let Predicates = [HasFSGSBase, In64BitMode] in {
    529   def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
    530                    "rdfsbase{l}\t$dst",
    531                    [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
    532   def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
    533                      "rdfsbase{q}\t$dst",
    534                      [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
    535   def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
    536                    "rdgsbase{l}\t$dst",
    537                    [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
    538   def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
    539                      "rdgsbase{q}\t$dst",
    540                      [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
    541   def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
    542                    "wrfsbase{l}\t$src",
    543                    [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
    544   def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
    545                       "wrfsbase{q}\t$src",
    546                       [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
    547   def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
    548                    "wrgsbase{l}\t$src",
    549                    [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
    550   def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
    551                       "wrgsbase{q}\t$src",
    552                       [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
    553 }
    554 
    555 //===----------------------------------------------------------------------===//
    556 // INVPCID Instruction
    557 def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
    558                 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
    559                 Requires<[Not64BitMode]>;
    560 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
    561                 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
    562                 Requires<[In64BitMode]>;
    563 
    564 //===----------------------------------------------------------------------===//
    565 // SMAP Instruction
    566 let Defs = [EFLAGS], Uses = [EFLAGS] in {
    567   def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
    568   def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
    569 }
    570