1 ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s 2 3 ; Extract of an upper half of a vector is an "ext.16b v0, v0, v0, #8" insn. 4 5 define <8 x i8> @v8i8(<16 x i8> %a) nounwind { 6 ; CHECK: v8i8 7 ; CHECK: ext.16b v0, v0, v0, #8 8 ; CHECK: ret 9 %ret = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 10 ret <8 x i8> %ret 11 } 12 13 define <4 x i16> @v4i16(<8 x i16> %a) nounwind { 14 ; CHECK-LABEL: v4i16: 15 ; CHECK: ext.16b v0, v0, v0, #8 16 ; CHECK: ret 17 %ret = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 18 ret <4 x i16> %ret 19 } 20 21 define <2 x i32> @v2i32(<4 x i32> %a) nounwind { 22 ; CHECK-LABEL: v2i32: 23 ; CHECK: ext.16b v0, v0, v0, #8 24 ; CHECK: ret 25 %ret = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3> 26 ret <2 x i32> %ret 27 } 28 29 define <1 x i64> @v1i64(<2 x i64> %a) nounwind { 30 ; CHECK-LABEL: v1i64: 31 ; CHECK: ext.16b v0, v0, v0, #8 32 ; CHECK: ret 33 %ret = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> <i32 1> 34 ret <1 x i64> %ret 35 } 36 37 define <2 x float> @v2f32(<4 x float> %a) nounwind { 38 ; CHECK-LABEL: v2f32: 39 ; CHECK: ext.16b v0, v0, v0, #8 40 ; CHECK: ret 41 %ret = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> <i32 2, i32 3> 42 ret <2 x float> %ret 43 } 44 45 define <1 x double> @v1f64(<2 x double> %a) nounwind { 46 ; CHECK-LABEL: v1f64: 47 ; CHECK: ext.16b v0, v0, v0, #8 48 ; CHECK: ret 49 %ret = shufflevector <2 x double> %a, <2 x double> %a, <1 x i32> <i32 1> 50 ret <1 x double> %ret 51 } 52
