1 ; Positive test for inline register constraints 2 ; 3 ; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=CHECK_LITTLE_32 %s 4 ; RUN: llc -march=mips < %s | FileCheck -check-prefix=CHECK_BIG_32 %s 5 6 %union.u_tag = type { i64 } 7 %struct.anon = type { i32, i32 } 8 @uval = common global %union.u_tag zeroinitializer, align 8 9 10 ; X with -3 11 define i32 @constraint_X() nounwind { 12 entry: 13 ;CHECK_LITTLE_32-LABEL: constraint_X: 14 ;CHECK_LITTLE_32: #APP 15 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd 16 ;CHECK_LITTLE_32: #NO_APP 17 tail call i32 asm sideeffect "addiu $0,$1,${2:X}", "=r,r,I"(i32 7, i32 -3) ; 18 ret i32 0 19 } 20 21 ; x with -3 22 define i32 @constraint_x() nounwind { 23 entry: 24 ;CHECK_LITTLE_32-LABEL: constraint_x: 25 ;CHECK_LITTLE_32: #APP 26 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},0xfffd 27 ;CHECK_LITTLE_32: #NO_APP 28 tail call i32 asm sideeffect "addiu $0,$1,${2:x}", "=r,r,I"(i32 7, i32 -3) ; 29 ret i32 0 30 } 31 32 ; d with -3 33 define i32 @constraint_d() nounwind { 34 entry: 35 ;CHECK_LITTLE_32-LABEL: constraint_d: 36 ;CHECK_LITTLE_32: #APP 37 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-3 38 ;CHECK_LITTLE_32: #NO_APP 39 tail call i32 asm sideeffect "addiu $0,$1,${2:d}", "=r,r,I"(i32 7, i32 -3) ; 40 ret i32 0 41 } 42 43 ; m with -3 44 define i32 @constraint_m() nounwind { 45 entry: 46 ;CHECK_LITTLE_32-LABEL: constraint_m: 47 ;CHECK_LITTLE_32: #APP 48 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-4 49 ;CHECK_LITTLE_32: #NO_APP 50 tail call i32 asm sideeffect "addiu $0,$1,${2:m}", "=r,r,I"(i32 7, i32 -3) ; 51 ret i32 0 52 } 53 54 ; z with -3 55 define i32 @constraint_z() nounwind { 56 entry: 57 ;CHECK_LITTLE_32-LABEL: constraint_z: 58 ;CHECK_LITTLE_32: #APP 59 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-3 60 ;CHECK_LITTLE_32: #NO_APP 61 tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) ; 62 63 ; z with 0 64 ;CHECK_LITTLE_32: #APP 65 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},$0 66 ;CHECK_LITTLE_32: #NO_APP 67 tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind 68 ret i32 0 69 } 70 71 ; a long long in 32 bit mode (use to assert) 72 define i32 @constraint_longlong() nounwind { 73 entry: 74 ;CHECK_LITTLE_32-LABEL: constraint_longlong: 75 ;CHECK_LITTLE_32: #APP 76 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},3 77 ;CHECK_LITTLE_32: #NO_APP 78 tail call i64 asm sideeffect "addiu $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind 79 ret i32 0 80 } 81 82 ; D, in little endian the source reg will be 4 bytes into the long long 83 define i32 @constraint_D() nounwind { 84 entry: 85 ;CHECK_LITTLE_32-LABEL: constraint_D: 86 ;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) 87 ;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) 88 ;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) 89 ;CHECK_LITTLE_32: #APP 90 ;CHECK_LITTLE_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} 91 ;CHECK_LITTLE_32: #NO_APP 92 93 ; D, in big endian the source reg will also be 4 bytes into the long long 94 ;CHECK_BIG_32-LABEL: constraint_D: 95 ;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) 96 ;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) 97 ;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) 98 ;CHECK_BIG_32: #APP 99 ;CHECK_BIG_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} 100 ;CHECK_BIG_32: #NO_APP 101 %bosco = load i64* getelementptr inbounds (%union.u_tag* @uval, i32 0, i32 0), align 8 102 %trunc1 = trunc i64 %bosco to i32 103 tail call i32 asm sideeffect "or $0,${1:D},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind 104 ret i32 0 105 } 106 107 ; L, in little endian the source reg will be 0 bytes into the long long 108 define i32 @constraint_L() nounwind { 109 entry: 110 ;CHECK_LITTLE_32-LABEL: constraint_L: 111 ;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) 112 ;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) 113 ;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) 114 ;CHECK_LITTLE_32: #APP 115 ;CHECK_LITTLE_32: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}} 116 ;CHECK_LITTLE_32: #NO_APP 117 ; L, in big endian the source reg will be 4 bytes into the long long 118 ;CHECK_BIG_32-LABEL: constraint_L: 119 ;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) 120 ;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) 121 ;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) 122 ;CHECK_BIG_32: #APP 123 ;CHECK_BIG_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} 124 ;CHECK_BIG_32: #NO_APP 125 %bosco = load i64* getelementptr inbounds (%union.u_tag* @uval, i32 0, i32 0), align 8 126 %trunc1 = trunc i64 %bosco to i32 127 tail call i32 asm sideeffect "or $0,${1:L},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind 128 ret i32 0 129 } 130 131 ; M, in little endian the source reg will be 4 bytes into the long long 132 define i32 @constraint_M() nounwind { 133 entry: 134 ;CHECK_LITTLE_32-LABEL: constraint_M: 135 ;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) 136 ;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) 137 ;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) 138 ;CHECK_LITTLE_32: #APP 139 ;CHECK_LITTLE_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} 140 ;CHECK_LITTLE_32: #NO_APP 141 ; M, in big endian the source reg will be 0 bytes into the long long 142 ;CHECK_BIG_32-LABEL: constraint_M: 143 ;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) 144 ;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) 145 ;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) 146 ;CHECK_BIG_32: #APP 147 ;CHECK_BIG_32: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}} 148 ;CHECK_BIG_32: #NO_APP 149 %bosco = load i64* getelementptr inbounds (%union.u_tag* @uval, i32 0, i32 0), align 8 150 %trunc1 = trunc i64 %bosco to i32 151 tail call i32 asm sideeffect "or $0,${1:M},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind 152 ret i32 0 153 } 154
