1 ; Test the MSA intrinsics that are encoded with the 2R instruction format. 2 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 5 6 @llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 7 @llvm_mips_nloc_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 8 9 define void @llvm_mips_nloc_b_test() nounwind { 10 entry: 11 %0 = load <16 x i8>* @llvm_mips_nloc_b_ARG1 12 %1 = tail call <16 x i8> @llvm.mips.nloc.b(<16 x i8> %0) 13 store <16 x i8> %1, <16 x i8>* @llvm_mips_nloc_b_RES 14 ret void 15 } 16 17 declare <16 x i8> @llvm.mips.nloc.b(<16 x i8>) nounwind 18 19 ; CHECK: llvm_mips_nloc_b_test: 20 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nloc_b_ARG1) 21 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 22 ; CHECK-DAG: nloc.b [[WD:\$w[0-9]+]], [[WS]] 23 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nloc_b_RES) 24 ; CHECK-DAG: st.b [[WD]], 0([[R2]]) 25 ; CHECK: .size llvm_mips_nloc_b_test 26 ; 27 @llvm_mips_nloc_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 28 @llvm_mips_nloc_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 29 30 define void @llvm_mips_nloc_h_test() nounwind { 31 entry: 32 %0 = load <8 x i16>* @llvm_mips_nloc_h_ARG1 33 %1 = tail call <8 x i16> @llvm.mips.nloc.h(<8 x i16> %0) 34 store <8 x i16> %1, <8 x i16>* @llvm_mips_nloc_h_RES 35 ret void 36 } 37 38 declare <8 x i16> @llvm.mips.nloc.h(<8 x i16>) nounwind 39 40 ; CHECK: llvm_mips_nloc_h_test: 41 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nloc_h_ARG1) 42 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 43 ; CHECK-DAG: nloc.h [[WD:\$w[0-9]+]], [[WS]] 44 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nloc_h_RES) 45 ; CHECK-DAG: st.h [[WD]], 0([[R2]]) 46 ; CHECK: .size llvm_mips_nloc_h_test 47 ; 48 @llvm_mips_nloc_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 49 @llvm_mips_nloc_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 50 51 define void @llvm_mips_nloc_w_test() nounwind { 52 entry: 53 %0 = load <4 x i32>* @llvm_mips_nloc_w_ARG1 54 %1 = tail call <4 x i32> @llvm.mips.nloc.w(<4 x i32> %0) 55 store <4 x i32> %1, <4 x i32>* @llvm_mips_nloc_w_RES 56 ret void 57 } 58 59 declare <4 x i32> @llvm.mips.nloc.w(<4 x i32>) nounwind 60 61 ; CHECK: llvm_mips_nloc_w_test: 62 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nloc_w_ARG1) 63 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 64 ; CHECK-DAG: nloc.w [[WD:\$w[0-9]+]], [[WS]] 65 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nloc_w_RES) 66 ; CHECK-DAG: st.w [[WD]], 0([[R2]]) 67 ; CHECK: .size llvm_mips_nloc_w_test 68 ; 69 @llvm_mips_nloc_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 70 @llvm_mips_nloc_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 71 72 define void @llvm_mips_nloc_d_test() nounwind { 73 entry: 74 %0 = load <2 x i64>* @llvm_mips_nloc_d_ARG1 75 %1 = tail call <2 x i64> @llvm.mips.nloc.d(<2 x i64> %0) 76 store <2 x i64> %1, <2 x i64>* @llvm_mips_nloc_d_RES 77 ret void 78 } 79 80 declare <2 x i64> @llvm.mips.nloc.d(<2 x i64>) nounwind 81 82 ; CHECK: llvm_mips_nloc_d_test: 83 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nloc_d_ARG1) 84 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 85 ; CHECK-DAG: nloc.d [[WD:\$w[0-9]+]], [[WS]] 86 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nloc_d_RES) 87 ; CHECK-DAG: st.d [[WD]], 0([[R2]]) 88 ; CHECK: .size llvm_mips_nloc_d_test 89 ; 90 @llvm_mips_nlzc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 91 @llvm_mips_nlzc_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 92 93 define void @llvm_mips_nlzc_b_test() nounwind { 94 entry: 95 %0 = load <16 x i8>* @llvm_mips_nlzc_b_ARG1 96 %1 = tail call <16 x i8> @llvm.mips.nlzc.b(<16 x i8> %0) 97 store <16 x i8> %1, <16 x i8>* @llvm_mips_nlzc_b_RES 98 ret void 99 } 100 101 declare <16 x i8> @llvm.mips.nlzc.b(<16 x i8>) nounwind 102 103 ; CHECK: llvm_mips_nlzc_b_test: 104 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nlzc_b_ARG1) 105 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 106 ; CHECK-DAG: nlzc.b [[WD:\$w[0-9]+]], [[WS]] 107 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nlzc_b_RES) 108 ; CHECK-DAG: st.b [[WD]], 0([[R2]]) 109 ; CHECK: .size llvm_mips_nlzc_b_test 110 ; 111 @llvm_mips_nlzc_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 112 @llvm_mips_nlzc_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 113 114 define void @llvm_mips_nlzc_h_test() nounwind { 115 entry: 116 %0 = load <8 x i16>* @llvm_mips_nlzc_h_ARG1 117 %1 = tail call <8 x i16> @llvm.mips.nlzc.h(<8 x i16> %0) 118 store <8 x i16> %1, <8 x i16>* @llvm_mips_nlzc_h_RES 119 ret void 120 } 121 122 declare <8 x i16> @llvm.mips.nlzc.h(<8 x i16>) nounwind 123 124 ; CHECK: llvm_mips_nlzc_h_test: 125 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nlzc_h_ARG1) 126 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 127 ; CHECK-DAG: nlzc.h [[WD:\$w[0-9]+]], [[WS]] 128 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nlzc_h_RES) 129 ; CHECK-DAG: st.h [[WD]], 0([[R2]]) 130 ; CHECK: .size llvm_mips_nlzc_h_test 131 ; 132 @llvm_mips_nlzc_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 133 @llvm_mips_nlzc_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 134 135 define void @llvm_mips_nlzc_w_test() nounwind { 136 entry: 137 %0 = load <4 x i32>* @llvm_mips_nlzc_w_ARG1 138 %1 = tail call <4 x i32> @llvm.mips.nlzc.w(<4 x i32> %0) 139 store <4 x i32> %1, <4 x i32>* @llvm_mips_nlzc_w_RES 140 ret void 141 } 142 143 declare <4 x i32> @llvm.mips.nlzc.w(<4 x i32>) nounwind 144 145 ; CHECK: llvm_mips_nlzc_w_test: 146 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nlzc_w_ARG1) 147 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 148 ; CHECK-DAG: nlzc.w [[WD:\$w[0-9]+]], [[WS]] 149 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nlzc_w_RES) 150 ; CHECK-DAG: st.w [[WD]], 0([[R2]]) 151 ; CHECK: .size llvm_mips_nlzc_w_test 152 ; 153 @llvm_mips_nlzc_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 154 @llvm_mips_nlzc_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 155 156 define void @llvm_mips_nlzc_d_test() nounwind { 157 entry: 158 %0 = load <2 x i64>* @llvm_mips_nlzc_d_ARG1 159 %1 = tail call <2 x i64> @llvm.mips.nlzc.d(<2 x i64> %0) 160 store <2 x i64> %1, <2 x i64>* @llvm_mips_nlzc_d_RES 161 ret void 162 } 163 164 declare <2 x i64> @llvm.mips.nlzc.d(<2 x i64>) nounwind 165 166 ; CHECK: llvm_mips_nlzc_d_test: 167 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nlzc_d_ARG1) 168 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 169 ; CHECK-DAG: nlzc.d [[WD:\$w[0-9]+]], [[WS]] 170 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nlzc_d_RES) 171 ; CHECK-DAG: st.d [[WD]], 0([[R2]]) 172 ; CHECK: .size llvm_mips_nlzc_d_test 173 ; 174 @llvm_mips_pcnt_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 175 @llvm_mips_pcnt_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 176 177 define void @llvm_mips_pcnt_b_test() nounwind { 178 entry: 179 %0 = load <16 x i8>* @llvm_mips_pcnt_b_ARG1 180 %1 = tail call <16 x i8> @llvm.mips.pcnt.b(<16 x i8> %0) 181 store <16 x i8> %1, <16 x i8>* @llvm_mips_pcnt_b_RES 182 ret void 183 } 184 185 declare <16 x i8> @llvm.mips.pcnt.b(<16 x i8>) nounwind 186 187 ; CHECK: llvm_mips_pcnt_b_test: 188 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_pcnt_b_ARG1) 189 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 190 ; CHECK-DAG: pcnt.b [[WD:\$w[0-9]+]], [[WS]] 191 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_pcnt_b_RES) 192 ; CHECK-DAG: st.b [[WD]], 0([[R2]]) 193 ; CHECK: .size llvm_mips_pcnt_b_test 194 ; 195 @llvm_mips_pcnt_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 196 @llvm_mips_pcnt_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 197 198 define void @llvm_mips_pcnt_h_test() nounwind { 199 entry: 200 %0 = load <8 x i16>* @llvm_mips_pcnt_h_ARG1 201 %1 = tail call <8 x i16> @llvm.mips.pcnt.h(<8 x i16> %0) 202 store <8 x i16> %1, <8 x i16>* @llvm_mips_pcnt_h_RES 203 ret void 204 } 205 206 declare <8 x i16> @llvm.mips.pcnt.h(<8 x i16>) nounwind 207 208 ; CHECK: llvm_mips_pcnt_h_test: 209 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_pcnt_h_ARG1) 210 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 211 ; CHECK-DAG: pcnt.h [[WD:\$w[0-9]+]], [[WS]] 212 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_pcnt_h_RES) 213 ; CHECK-DAG: st.h [[WD]], 0([[R2]]) 214 ; CHECK: .size llvm_mips_pcnt_h_test 215 ; 216 @llvm_mips_pcnt_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 217 @llvm_mips_pcnt_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 218 219 define void @llvm_mips_pcnt_w_test() nounwind { 220 entry: 221 %0 = load <4 x i32>* @llvm_mips_pcnt_w_ARG1 222 %1 = tail call <4 x i32> @llvm.mips.pcnt.w(<4 x i32> %0) 223 store <4 x i32> %1, <4 x i32>* @llvm_mips_pcnt_w_RES 224 ret void 225 } 226 227 declare <4 x i32> @llvm.mips.pcnt.w(<4 x i32>) nounwind 228 229 ; CHECK: llvm_mips_pcnt_w_test: 230 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_pcnt_w_ARG1) 231 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 232 ; CHECK-DAG: pcnt.w [[WD:\$w[0-9]+]], [[WS]] 233 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_pcnt_w_RES) 234 ; CHECK-DAG: st.w [[WD]], 0([[R2]]) 235 ; CHECK: .size llvm_mips_pcnt_w_test 236 ; 237 @llvm_mips_pcnt_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 238 @llvm_mips_pcnt_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 239 240 define void @llvm_mips_pcnt_d_test() nounwind { 241 entry: 242 %0 = load <2 x i64>* @llvm_mips_pcnt_d_ARG1 243 %1 = tail call <2 x i64> @llvm.mips.pcnt.d(<2 x i64> %0) 244 store <2 x i64> %1, <2 x i64>* @llvm_mips_pcnt_d_RES 245 ret void 246 } 247 248 declare <2 x i64> @llvm.mips.pcnt.d(<2 x i64>) nounwind 249 250 ; CHECK: llvm_mips_pcnt_d_test: 251 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_pcnt_d_ARG1) 252 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 253 ; CHECK-DAG: pcnt.d [[WD:\$w[0-9]+]], [[WS]] 254 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_pcnt_d_RES) 255 ; CHECK-DAG: st.d [[WD]], 0([[R2]]) 256 ; CHECK: .size llvm_mips_pcnt_d_test 257 ; 258
