1 ; Test the MSA intrinsics that are encoded with the 3R instruction format. 2 ; There are lots of these so this covers those beginning with 'a' 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7 ; It should fail to compile without fp64. 8 ; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \ 9 ; RUN: FileCheck -check-prefix=FP32ERROR %s 10 ; FP32ERROR: LLVM ERROR: MSA requires a 64-bit FPU register file (FR=1 mode). 11 12 @llvm_mips_add_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 13 @llvm_mips_add_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 14 @llvm_mips_add_a_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 15 16 define void @llvm_mips_add_a_b_test() nounwind { 17 entry: 18 %0 = load <16 x i8>* @llvm_mips_add_a_b_ARG1 19 %1 = load <16 x i8>* @llvm_mips_add_a_b_ARG2 20 %2 = tail call <16 x i8> @llvm.mips.add.a.b(<16 x i8> %0, <16 x i8> %1) 21 store <16 x i8> %2, <16 x i8>* @llvm_mips_add_a_b_RES 22 ret void 23 } 24 25 declare <16 x i8> @llvm.mips.add.a.b(<16 x i8>, <16 x i8>) nounwind 26 27 ; CHECK: llvm_mips_add_a_b_test: 28 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_add_a_b_ARG1) 29 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_add_a_b_ARG2) 30 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 31 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 32 ; CHECK-DAG: add_a.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 33 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_add_a_b_RES) 34 ; CHECK-DAG: st.b [[WD]], 0([[R3]]) 35 ; CHECK: .size llvm_mips_add_a_b_test 36 ; 37 @llvm_mips_add_a_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 38 @llvm_mips_add_a_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 39 @llvm_mips_add_a_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 40 41 define void @llvm_mips_add_a_h_test() nounwind { 42 entry: 43 %0 = load <8 x i16>* @llvm_mips_add_a_h_ARG1 44 %1 = load <8 x i16>* @llvm_mips_add_a_h_ARG2 45 %2 = tail call <8 x i16> @llvm.mips.add.a.h(<8 x i16> %0, <8 x i16> %1) 46 store <8 x i16> %2, <8 x i16>* @llvm_mips_add_a_h_RES 47 ret void 48 } 49 50 declare <8 x i16> @llvm.mips.add.a.h(<8 x i16>, <8 x i16>) nounwind 51 52 ; CHECK: llvm_mips_add_a_h_test: 53 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_add_a_h_ARG1) 54 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_add_a_h_ARG2) 55 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 56 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 57 ; CHECK-DAG: add_a.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 58 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_add_a_h_RES) 59 ; CHECK-DAG: st.h [[WD]], 0([[R3]]) 60 ; CHECK: .size llvm_mips_add_a_h_test 61 ; 62 @llvm_mips_add_a_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 63 @llvm_mips_add_a_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 64 @llvm_mips_add_a_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 65 66 define void @llvm_mips_add_a_w_test() nounwind { 67 entry: 68 %0 = load <4 x i32>* @llvm_mips_add_a_w_ARG1 69 %1 = load <4 x i32>* @llvm_mips_add_a_w_ARG2 70 %2 = tail call <4 x i32> @llvm.mips.add.a.w(<4 x i32> %0, <4 x i32> %1) 71 store <4 x i32> %2, <4 x i32>* @llvm_mips_add_a_w_RES 72 ret void 73 } 74 75 declare <4 x i32> @llvm.mips.add.a.w(<4 x i32>, <4 x i32>) nounwind 76 77 ; CHECK: llvm_mips_add_a_w_test: 78 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_add_a_w_ARG1) 79 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_add_a_w_ARG2) 80 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 81 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 82 ; CHECK-DAG: add_a.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 83 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_add_a_w_RES) 84 ; CHECK-DAG: st.w [[WD]], 0([[R3]]) 85 ; CHECK: .size llvm_mips_add_a_w_test 86 ; 87 @llvm_mips_add_a_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 88 @llvm_mips_add_a_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 89 @llvm_mips_add_a_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 90 91 define void @llvm_mips_add_a_d_test() nounwind { 92 entry: 93 %0 = load <2 x i64>* @llvm_mips_add_a_d_ARG1 94 %1 = load <2 x i64>* @llvm_mips_add_a_d_ARG2 95 %2 = tail call <2 x i64> @llvm.mips.add.a.d(<2 x i64> %0, <2 x i64> %1) 96 store <2 x i64> %2, <2 x i64>* @llvm_mips_add_a_d_RES 97 ret void 98 } 99 100 declare <2 x i64> @llvm.mips.add.a.d(<2 x i64>, <2 x i64>) nounwind 101 102 ; CHECK: llvm_mips_add_a_d_test: 103 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_add_a_d_ARG1) 104 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_add_a_d_ARG2) 105 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 106 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 107 ; CHECK-DAG: add_a.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 108 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_add_a_d_RES) 109 ; CHECK-DAG: st.d [[WD]], 0([[R3]]) 110 ; CHECK: .size llvm_mips_add_a_d_test 111 ; 112 @llvm_mips_adds_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 113 @llvm_mips_adds_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 114 @llvm_mips_adds_a_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 115 116 define void @llvm_mips_adds_a_b_test() nounwind { 117 entry: 118 %0 = load <16 x i8>* @llvm_mips_adds_a_b_ARG1 119 %1 = load <16 x i8>* @llvm_mips_adds_a_b_ARG2 120 %2 = tail call <16 x i8> @llvm.mips.adds.a.b(<16 x i8> %0, <16 x i8> %1) 121 store <16 x i8> %2, <16 x i8>* @llvm_mips_adds_a_b_RES 122 ret void 123 } 124 125 declare <16 x i8> @llvm.mips.adds.a.b(<16 x i8>, <16 x i8>) nounwind 126 127 ; CHECK: llvm_mips_adds_a_b_test: 128 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_a_b_ARG1) 129 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_a_b_ARG2) 130 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 131 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 132 ; CHECK-DAG: adds_a.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 133 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_a_b_RES) 134 ; CHECK-DAG: st.b [[WD]], 0([[R3]]) 135 ; CHECK: .size llvm_mips_adds_a_b_test 136 ; 137 @llvm_mips_adds_a_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 138 @llvm_mips_adds_a_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 139 @llvm_mips_adds_a_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 140 141 define void @llvm_mips_adds_a_h_test() nounwind { 142 entry: 143 %0 = load <8 x i16>* @llvm_mips_adds_a_h_ARG1 144 %1 = load <8 x i16>* @llvm_mips_adds_a_h_ARG2 145 %2 = tail call <8 x i16> @llvm.mips.adds.a.h(<8 x i16> %0, <8 x i16> %1) 146 store <8 x i16> %2, <8 x i16>* @llvm_mips_adds_a_h_RES 147 ret void 148 } 149 150 declare <8 x i16> @llvm.mips.adds.a.h(<8 x i16>, <8 x i16>) nounwind 151 152 ; CHECK: llvm_mips_adds_a_h_test: 153 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_a_h_ARG1) 154 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_a_h_ARG2) 155 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 156 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 157 ; CHECK-DAG: adds_a.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 158 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_a_h_RES) 159 ; CHECK-DAG: st.h [[WD]], 0([[R3]]) 160 ; CHECK: .size llvm_mips_adds_a_h_test 161 ; 162 @llvm_mips_adds_a_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 163 @llvm_mips_adds_a_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 164 @llvm_mips_adds_a_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 165 166 define void @llvm_mips_adds_a_w_test() nounwind { 167 entry: 168 %0 = load <4 x i32>* @llvm_mips_adds_a_w_ARG1 169 %1 = load <4 x i32>* @llvm_mips_adds_a_w_ARG2 170 %2 = tail call <4 x i32> @llvm.mips.adds.a.w(<4 x i32> %0, <4 x i32> %1) 171 store <4 x i32> %2, <4 x i32>* @llvm_mips_adds_a_w_RES 172 ret void 173 } 174 175 declare <4 x i32> @llvm.mips.adds.a.w(<4 x i32>, <4 x i32>) nounwind 176 177 ; CHECK: llvm_mips_adds_a_w_test: 178 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_a_w_ARG1) 179 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_a_w_ARG2) 180 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 181 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 182 ; CHECK-DAG: adds_a.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 183 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_a_w_RES) 184 ; CHECK-DAG: st.w [[WD]], 0([[R3]]) 185 ; CHECK: .size llvm_mips_adds_a_w_test 186 ; 187 @llvm_mips_adds_a_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 188 @llvm_mips_adds_a_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 189 @llvm_mips_adds_a_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 190 191 define void @llvm_mips_adds_a_d_test() nounwind { 192 entry: 193 %0 = load <2 x i64>* @llvm_mips_adds_a_d_ARG1 194 %1 = load <2 x i64>* @llvm_mips_adds_a_d_ARG2 195 %2 = tail call <2 x i64> @llvm.mips.adds.a.d(<2 x i64> %0, <2 x i64> %1) 196 store <2 x i64> %2, <2 x i64>* @llvm_mips_adds_a_d_RES 197 ret void 198 } 199 200 declare <2 x i64> @llvm.mips.adds.a.d(<2 x i64>, <2 x i64>) nounwind 201 202 ; CHECK: llvm_mips_adds_a_d_test: 203 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_a_d_ARG1) 204 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_a_d_ARG2) 205 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 206 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 207 ; CHECK-DAG: adds_a.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 208 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_a_d_RES) 209 ; CHECK-DAG: st.d [[WD]], 0([[R3]]) 210 ; CHECK: .size llvm_mips_adds_a_d_test 211 ; 212 @llvm_mips_adds_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 213 @llvm_mips_adds_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 214 @llvm_mips_adds_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 215 216 define void @llvm_mips_adds_s_b_test() nounwind { 217 entry: 218 %0 = load <16 x i8>* @llvm_mips_adds_s_b_ARG1 219 %1 = load <16 x i8>* @llvm_mips_adds_s_b_ARG2 220 %2 = tail call <16 x i8> @llvm.mips.adds.s.b(<16 x i8> %0, <16 x i8> %1) 221 store <16 x i8> %2, <16 x i8>* @llvm_mips_adds_s_b_RES 222 ret void 223 } 224 225 declare <16 x i8> @llvm.mips.adds.s.b(<16 x i8>, <16 x i8>) nounwind 226 227 ; CHECK: llvm_mips_adds_s_b_test: 228 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_s_b_ARG1) 229 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_s_b_ARG2) 230 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 231 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 232 ; CHECK-DAG: adds_s.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 233 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_s_b_RES) 234 ; CHECK-DAG: st.b [[WD]], 0([[R3]]) 235 ; CHECK: .size llvm_mips_adds_s_b_test 236 ; 237 @llvm_mips_adds_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 238 @llvm_mips_adds_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 239 @llvm_mips_adds_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 240 241 define void @llvm_mips_adds_s_h_test() nounwind { 242 entry: 243 %0 = load <8 x i16>* @llvm_mips_adds_s_h_ARG1 244 %1 = load <8 x i16>* @llvm_mips_adds_s_h_ARG2 245 %2 = tail call <8 x i16> @llvm.mips.adds.s.h(<8 x i16> %0, <8 x i16> %1) 246 store <8 x i16> %2, <8 x i16>* @llvm_mips_adds_s_h_RES 247 ret void 248 } 249 250 declare <8 x i16> @llvm.mips.adds.s.h(<8 x i16>, <8 x i16>) nounwind 251 252 ; CHECK: llvm_mips_adds_s_h_test: 253 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_s_h_ARG1) 254 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_s_h_ARG2) 255 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 256 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 257 ; CHECK-DAG: adds_s.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 258 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_s_h_RES) 259 ; CHECK-DAG: st.h [[WD]], 0([[R3]]) 260 ; CHECK: .size llvm_mips_adds_s_h_test 261 ; 262 @llvm_mips_adds_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 263 @llvm_mips_adds_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 264 @llvm_mips_adds_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 265 266 define void @llvm_mips_adds_s_w_test() nounwind { 267 entry: 268 %0 = load <4 x i32>* @llvm_mips_adds_s_w_ARG1 269 %1 = load <4 x i32>* @llvm_mips_adds_s_w_ARG2 270 %2 = tail call <4 x i32> @llvm.mips.adds.s.w(<4 x i32> %0, <4 x i32> %1) 271 store <4 x i32> %2, <4 x i32>* @llvm_mips_adds_s_w_RES 272 ret void 273 } 274 275 declare <4 x i32> @llvm.mips.adds.s.w(<4 x i32>, <4 x i32>) nounwind 276 277 ; CHECK: llvm_mips_adds_s_w_test: 278 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_s_w_ARG1) 279 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_s_w_ARG2) 280 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 281 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 282 ; CHECK-DAG: adds_s.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 283 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_s_w_RES) 284 ; CHECK-DAG: st.w [[WD]], 0([[R3]]) 285 ; CHECK: .size llvm_mips_adds_s_w_test 286 ; 287 @llvm_mips_adds_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 288 @llvm_mips_adds_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 289 @llvm_mips_adds_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 290 291 define void @llvm_mips_adds_s_d_test() nounwind { 292 entry: 293 %0 = load <2 x i64>* @llvm_mips_adds_s_d_ARG1 294 %1 = load <2 x i64>* @llvm_mips_adds_s_d_ARG2 295 %2 = tail call <2 x i64> @llvm.mips.adds.s.d(<2 x i64> %0, <2 x i64> %1) 296 store <2 x i64> %2, <2 x i64>* @llvm_mips_adds_s_d_RES 297 ret void 298 } 299 300 declare <2 x i64> @llvm.mips.adds.s.d(<2 x i64>, <2 x i64>) nounwind 301 302 ; CHECK: llvm_mips_adds_s_d_test: 303 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_s_d_ARG1) 304 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_s_d_ARG2) 305 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 306 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 307 ; CHECK-DAG: adds_s.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 308 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_s_d_RES) 309 ; CHECK-DAG: st.d [[WD]], 0([[R3]]) 310 ; CHECK: .size llvm_mips_adds_s_d_test 311 ; 312 @llvm_mips_adds_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 313 @llvm_mips_adds_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 314 @llvm_mips_adds_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 315 316 define void @llvm_mips_adds_u_b_test() nounwind { 317 entry: 318 %0 = load <16 x i8>* @llvm_mips_adds_u_b_ARG1 319 %1 = load <16 x i8>* @llvm_mips_adds_u_b_ARG2 320 %2 = tail call <16 x i8> @llvm.mips.adds.u.b(<16 x i8> %0, <16 x i8> %1) 321 store <16 x i8> %2, <16 x i8>* @llvm_mips_adds_u_b_RES 322 ret void 323 } 324 325 declare <16 x i8> @llvm.mips.adds.u.b(<16 x i8>, <16 x i8>) nounwind 326 327 ; CHECK: llvm_mips_adds_u_b_test: 328 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_u_b_ARG1) 329 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_u_b_ARG2) 330 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 331 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 332 ; CHECK-DAG: adds_u.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 333 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_u_b_RES) 334 ; CHECK-DAG: st.b [[WD]], 0([[R3]]) 335 ; CHECK: .size llvm_mips_adds_u_b_test 336 ; 337 @llvm_mips_adds_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 338 @llvm_mips_adds_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 339 @llvm_mips_adds_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 340 341 define void @llvm_mips_adds_u_h_test() nounwind { 342 entry: 343 %0 = load <8 x i16>* @llvm_mips_adds_u_h_ARG1 344 %1 = load <8 x i16>* @llvm_mips_adds_u_h_ARG2 345 %2 = tail call <8 x i16> @llvm.mips.adds.u.h(<8 x i16> %0, <8 x i16> %1) 346 store <8 x i16> %2, <8 x i16>* @llvm_mips_adds_u_h_RES 347 ret void 348 } 349 350 declare <8 x i16> @llvm.mips.adds.u.h(<8 x i16>, <8 x i16>) nounwind 351 352 ; CHECK: llvm_mips_adds_u_h_test: 353 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_u_h_ARG1) 354 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_u_h_ARG2) 355 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 356 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 357 ; CHECK-DAG: adds_u.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 358 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_u_h_RES) 359 ; CHECK-DAG: st.h [[WD]], 0([[R3]]) 360 ; CHECK: .size llvm_mips_adds_u_h_test 361 ; 362 @llvm_mips_adds_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 363 @llvm_mips_adds_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 364 @llvm_mips_adds_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 365 366 define void @llvm_mips_adds_u_w_test() nounwind { 367 entry: 368 %0 = load <4 x i32>* @llvm_mips_adds_u_w_ARG1 369 %1 = load <4 x i32>* @llvm_mips_adds_u_w_ARG2 370 %2 = tail call <4 x i32> @llvm.mips.adds.u.w(<4 x i32> %0, <4 x i32> %1) 371 store <4 x i32> %2, <4 x i32>* @llvm_mips_adds_u_w_RES 372 ret void 373 } 374 375 declare <4 x i32> @llvm.mips.adds.u.w(<4 x i32>, <4 x i32>) nounwind 376 377 ; CHECK: llvm_mips_adds_u_w_test: 378 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_u_w_ARG1) 379 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_u_w_ARG2) 380 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 381 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 382 ; CHECK-DAG: adds_u.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 383 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_u_w_RES) 384 ; CHECK-DAG: st.w [[WD]], 0([[R3]]) 385 ; CHECK: .size llvm_mips_adds_u_w_test 386 ; 387 @llvm_mips_adds_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 388 @llvm_mips_adds_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 389 @llvm_mips_adds_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 390 391 define void @llvm_mips_adds_u_d_test() nounwind { 392 entry: 393 %0 = load <2 x i64>* @llvm_mips_adds_u_d_ARG1 394 %1 = load <2 x i64>* @llvm_mips_adds_u_d_ARG2 395 %2 = tail call <2 x i64> @llvm.mips.adds.u.d(<2 x i64> %0, <2 x i64> %1) 396 store <2 x i64> %2, <2 x i64>* @llvm_mips_adds_u_d_RES 397 ret void 398 } 399 400 declare <2 x i64> @llvm.mips.adds.u.d(<2 x i64>, <2 x i64>) nounwind 401 402 ; CHECK: llvm_mips_adds_u_d_test: 403 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_adds_u_d_ARG1) 404 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_adds_u_d_ARG2) 405 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 406 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 407 ; CHECK-DAG: adds_u.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 408 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_adds_u_d_RES) 409 ; CHECK-DAG: st.d [[WD]], 0([[R3]]) 410 ; CHECK: .size llvm_mips_adds_u_d_test 411 ; 412 @llvm_mips_addv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 413 @llvm_mips_addv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 414 @llvm_mips_addv_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 415 416 define void @llvm_mips_addv_b_test() nounwind { 417 entry: 418 %0 = load <16 x i8>* @llvm_mips_addv_b_ARG1 419 %1 = load <16 x i8>* @llvm_mips_addv_b_ARG2 420 %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1) 421 store <16 x i8> %2, <16 x i8>* @llvm_mips_addv_b_RES 422 ret void 423 } 424 425 declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>) nounwind 426 427 ; CHECK: llvm_mips_addv_b_test: 428 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_b_ARG1) 429 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_b_ARG2) 430 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 431 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 432 ; CHECK-DAG: addv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 433 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_b_RES) 434 ; CHECK-DAG: st.b [[WD]], 0([[R3]]) 435 ; CHECK: .size llvm_mips_addv_b_test 436 ; 437 @llvm_mips_addv_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 438 @llvm_mips_addv_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 439 @llvm_mips_addv_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 440 441 define void @llvm_mips_addv_h_test() nounwind { 442 entry: 443 %0 = load <8 x i16>* @llvm_mips_addv_h_ARG1 444 %1 = load <8 x i16>* @llvm_mips_addv_h_ARG2 445 %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %1) 446 store <8 x i16> %2, <8 x i16>* @llvm_mips_addv_h_RES 447 ret void 448 } 449 450 declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>) nounwind 451 452 ; CHECK: llvm_mips_addv_h_test: 453 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_h_ARG1) 454 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_h_ARG2) 455 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 456 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 457 ; CHECK-DAG: addv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 458 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_h_RES) 459 ; CHECK-DAG: st.h [[WD]], 0([[R3]]) 460 ; CHECK: .size llvm_mips_addv_h_test 461 ; 462 @llvm_mips_addv_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 463 @llvm_mips_addv_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 464 @llvm_mips_addv_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 465 466 define void @llvm_mips_addv_w_test() nounwind { 467 entry: 468 %0 = load <4 x i32>* @llvm_mips_addv_w_ARG1 469 %1 = load <4 x i32>* @llvm_mips_addv_w_ARG2 470 %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1) 471 store <4 x i32> %2, <4 x i32>* @llvm_mips_addv_w_RES 472 ret void 473 } 474 475 declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>) nounwind 476 477 ; CHECK: llvm_mips_addv_w_test: 478 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_w_ARG1) 479 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_w_ARG2) 480 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 481 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 482 ; CHECK-DAG: addv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 483 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_w_RES) 484 ; CHECK-DAG: st.w [[WD]], 0([[R3]]) 485 ; CHECK: .size llvm_mips_addv_w_test 486 ; 487 @llvm_mips_addv_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 488 @llvm_mips_addv_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 489 @llvm_mips_addv_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 490 491 define void @llvm_mips_addv_d_test() nounwind { 492 entry: 493 %0 = load <2 x i64>* @llvm_mips_addv_d_ARG1 494 %1 = load <2 x i64>* @llvm_mips_addv_d_ARG2 495 %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %1) 496 store <2 x i64> %2, <2 x i64>* @llvm_mips_addv_d_RES 497 ret void 498 } 499 500 declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>) nounwind 501 502 ; CHECK: llvm_mips_addv_d_test: 503 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_d_ARG1) 504 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_d_ARG2) 505 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 506 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 507 ; CHECK-DAG: addv.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 508 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_d_RES) 509 ; CHECK-DAG: st.d [[WD]], 0([[R3]]) 510 ; CHECK: .size llvm_mips_addv_d_test 511 ; 512 513 define void @addv_b_test() nounwind { 514 entry: 515 %0 = load <16 x i8>* @llvm_mips_addv_b_ARG1 516 %1 = load <16 x i8>* @llvm_mips_addv_b_ARG2 517 %2 = add <16 x i8> %0, %1 518 store <16 x i8> %2, <16 x i8>* @llvm_mips_addv_b_RES 519 ret void 520 } 521 522 ; CHECK: addv_b_test: 523 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_b_ARG1) 524 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_b_ARG2) 525 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 526 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 527 ; CHECK-DAG: addv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 528 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_b_RES) 529 ; CHECK-DAG: st.b [[WD]], 0([[R3]]) 530 ; CHECK: .size addv_b_test 531 ; 532 533 define void @addv_h_test() nounwind { 534 entry: 535 %0 = load <8 x i16>* @llvm_mips_addv_h_ARG1 536 %1 = load <8 x i16>* @llvm_mips_addv_h_ARG2 537 %2 = add <8 x i16> %0, %1 538 store <8 x i16> %2, <8 x i16>* @llvm_mips_addv_h_RES 539 ret void 540 } 541 542 ; CHECK: addv_h_test: 543 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_h_ARG1) 544 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_h_ARG2) 545 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 546 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 547 ; CHECK-DAG: addv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 548 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_h_RES) 549 ; CHECK-DAG: st.h [[WD]], 0([[R3]]) 550 ; CHECK: .size addv_h_test 551 ; 552 553 define void @addv_w_test() nounwind { 554 entry: 555 %0 = load <4 x i32>* @llvm_mips_addv_w_ARG1 556 %1 = load <4 x i32>* @llvm_mips_addv_w_ARG2 557 %2 = add <4 x i32> %0, %1 558 store <4 x i32> %2, <4 x i32>* @llvm_mips_addv_w_RES 559 ret void 560 } 561 562 ; CHECK: addv_w_test: 563 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_w_ARG1) 564 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_w_ARG2) 565 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 566 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 567 ; CHECK-DAG: addv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 568 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_w_RES) 569 ; CHECK-DAG: st.w [[WD]], 0([[R3]]) 570 ; CHECK: .size addv_w_test 571 ; 572 573 define void @addv_d_test() nounwind { 574 entry: 575 %0 = load <2 x i64>* @llvm_mips_addv_d_ARG1 576 %1 = load <2 x i64>* @llvm_mips_addv_d_ARG2 577 %2 = add <2 x i64> %0, %1 578 store <2 x i64> %2, <2 x i64>* @llvm_mips_addv_d_RES 579 ret void 580 } 581 582 ; CHECK: addv_d_test: 583 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_addv_d_ARG1) 584 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_addv_d_ARG2) 585 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 586 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 587 ; CHECK-DAG: addv.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 588 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_addv_d_RES) 589 ; CHECK-DAG: st.d [[WD]], 0([[R3]]) 590 ; CHECK: .size addv_d_test 591 ; 592 @llvm_mips_asub_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 593 @llvm_mips_asub_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 594 @llvm_mips_asub_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 595 596 define void @llvm_mips_asub_s_b_test() nounwind { 597 entry: 598 %0 = load <16 x i8>* @llvm_mips_asub_s_b_ARG1 599 %1 = load <16 x i8>* @llvm_mips_asub_s_b_ARG2 600 %2 = tail call <16 x i8> @llvm.mips.asub.s.b(<16 x i8> %0, <16 x i8> %1) 601 store <16 x i8> %2, <16 x i8>* @llvm_mips_asub_s_b_RES 602 ret void 603 } 604 605 declare <16 x i8> @llvm.mips.asub.s.b(<16 x i8>, <16 x i8>) nounwind 606 607 ; CHECK: llvm_mips_asub_s_b_test: 608 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_s_b_ARG1) 609 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_s_b_ARG2) 610 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 611 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 612 ; CHECK-DAG: asub_s.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 613 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_s_b_RES) 614 ; CHECK-DAG: st.b [[WD]], 0([[R3]]) 615 ; CHECK: .size llvm_mips_asub_s_b_test 616 ; 617 @llvm_mips_asub_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 618 @llvm_mips_asub_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 619 @llvm_mips_asub_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 620 621 define void @llvm_mips_asub_s_h_test() nounwind { 622 entry: 623 %0 = load <8 x i16>* @llvm_mips_asub_s_h_ARG1 624 %1 = load <8 x i16>* @llvm_mips_asub_s_h_ARG2 625 %2 = tail call <8 x i16> @llvm.mips.asub.s.h(<8 x i16> %0, <8 x i16> %1) 626 store <8 x i16> %2, <8 x i16>* @llvm_mips_asub_s_h_RES 627 ret void 628 } 629 630 declare <8 x i16> @llvm.mips.asub.s.h(<8 x i16>, <8 x i16>) nounwind 631 632 ; CHECK: llvm_mips_asub_s_h_test: 633 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_s_h_ARG1) 634 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_s_h_ARG2) 635 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 636 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 637 ; CHECK-DAG: asub_s.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 638 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_s_h_RES) 639 ; CHECK-DAG: st.h [[WD]], 0([[R3]]) 640 ; CHECK: .size llvm_mips_asub_s_h_test 641 ; 642 @llvm_mips_asub_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 643 @llvm_mips_asub_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 644 @llvm_mips_asub_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 645 646 define void @llvm_mips_asub_s_w_test() nounwind { 647 entry: 648 %0 = load <4 x i32>* @llvm_mips_asub_s_w_ARG1 649 %1 = load <4 x i32>* @llvm_mips_asub_s_w_ARG2 650 %2 = tail call <4 x i32> @llvm.mips.asub.s.w(<4 x i32> %0, <4 x i32> %1) 651 store <4 x i32> %2, <4 x i32>* @llvm_mips_asub_s_w_RES 652 ret void 653 } 654 655 declare <4 x i32> @llvm.mips.asub.s.w(<4 x i32>, <4 x i32>) nounwind 656 657 ; CHECK: llvm_mips_asub_s_w_test: 658 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_s_w_ARG1) 659 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_s_w_ARG2) 660 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 661 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 662 ; CHECK-DAG: asub_s.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 663 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_s_w_RES) 664 ; CHECK-DAG: st.w [[WD]], 0([[R3]]) 665 ; CHECK: .size llvm_mips_asub_s_w_test 666 ; 667 @llvm_mips_asub_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 668 @llvm_mips_asub_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 669 @llvm_mips_asub_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 670 671 define void @llvm_mips_asub_s_d_test() nounwind { 672 entry: 673 %0 = load <2 x i64>* @llvm_mips_asub_s_d_ARG1 674 %1 = load <2 x i64>* @llvm_mips_asub_s_d_ARG2 675 %2 = tail call <2 x i64> @llvm.mips.asub.s.d(<2 x i64> %0, <2 x i64> %1) 676 store <2 x i64> %2, <2 x i64>* @llvm_mips_asub_s_d_RES 677 ret void 678 } 679 680 declare <2 x i64> @llvm.mips.asub.s.d(<2 x i64>, <2 x i64>) nounwind 681 682 ; CHECK: llvm_mips_asub_s_d_test: 683 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_s_d_ARG1) 684 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_s_d_ARG2) 685 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 686 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 687 ; CHECK-DAG: asub_s.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 688 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_s_d_RES) 689 ; CHECK-DAG: st.d [[WD]], 0([[R3]]) 690 ; CHECK: .size llvm_mips_asub_s_d_test 691 ; 692 @llvm_mips_asub_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 693 @llvm_mips_asub_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 694 @llvm_mips_asub_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 695 696 define void @llvm_mips_asub_u_b_test() nounwind { 697 entry: 698 %0 = load <16 x i8>* @llvm_mips_asub_u_b_ARG1 699 %1 = load <16 x i8>* @llvm_mips_asub_u_b_ARG2 700 %2 = tail call <16 x i8> @llvm.mips.asub.u.b(<16 x i8> %0, <16 x i8> %1) 701 store <16 x i8> %2, <16 x i8>* @llvm_mips_asub_u_b_RES 702 ret void 703 } 704 705 declare <16 x i8> @llvm.mips.asub.u.b(<16 x i8>, <16 x i8>) nounwind 706 707 ; CHECK: llvm_mips_asub_u_b_test: 708 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_u_b_ARG1) 709 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_u_b_ARG2) 710 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 711 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 712 ; CHECK-DAG: asub_u.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 713 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_u_b_RES) 714 ; CHECK-DAG: st.b [[WD]], 0([[R3]]) 715 ; CHECK: .size llvm_mips_asub_u_b_test 716 ; 717 @llvm_mips_asub_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 718 @llvm_mips_asub_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 719 @llvm_mips_asub_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 720 721 define void @llvm_mips_asub_u_h_test() nounwind { 722 entry: 723 %0 = load <8 x i16>* @llvm_mips_asub_u_h_ARG1 724 %1 = load <8 x i16>* @llvm_mips_asub_u_h_ARG2 725 %2 = tail call <8 x i16> @llvm.mips.asub.u.h(<8 x i16> %0, <8 x i16> %1) 726 store <8 x i16> %2, <8 x i16>* @llvm_mips_asub_u_h_RES 727 ret void 728 } 729 730 declare <8 x i16> @llvm.mips.asub.u.h(<8 x i16>, <8 x i16>) nounwind 731 732 ; CHECK: llvm_mips_asub_u_h_test: 733 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_u_h_ARG1) 734 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_u_h_ARG2) 735 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 736 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 737 ; CHECK-DAG: asub_u.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 738 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_u_h_RES) 739 ; CHECK-DAG: st.h [[WD]], 0([[R3]]) 740 ; CHECK: .size llvm_mips_asub_u_h_test 741 ; 742 @llvm_mips_asub_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 743 @llvm_mips_asub_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 744 @llvm_mips_asub_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 745 746 define void @llvm_mips_asub_u_w_test() nounwind { 747 entry: 748 %0 = load <4 x i32>* @llvm_mips_asub_u_w_ARG1 749 %1 = load <4 x i32>* @llvm_mips_asub_u_w_ARG2 750 %2 = tail call <4 x i32> @llvm.mips.asub.u.w(<4 x i32> %0, <4 x i32> %1) 751 store <4 x i32> %2, <4 x i32>* @llvm_mips_asub_u_w_RES 752 ret void 753 } 754 755 declare <4 x i32> @llvm.mips.asub.u.w(<4 x i32>, <4 x i32>) nounwind 756 757 ; CHECK: llvm_mips_asub_u_w_test: 758 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_u_w_ARG1) 759 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_u_w_ARG2) 760 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 761 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 762 ; CHECK-DAG: asub_u.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 763 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_u_w_RES) 764 ; CHECK-DAG: st.w [[WD]], 0([[R3]]) 765 ; CHECK: .size llvm_mips_asub_u_w_test 766 ; 767 @llvm_mips_asub_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 768 @llvm_mips_asub_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 769 @llvm_mips_asub_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 770 771 define void @llvm_mips_asub_u_d_test() nounwind { 772 entry: 773 %0 = load <2 x i64>* @llvm_mips_asub_u_d_ARG1 774 %1 = load <2 x i64>* @llvm_mips_asub_u_d_ARG2 775 %2 = tail call <2 x i64> @llvm.mips.asub.u.d(<2 x i64> %0, <2 x i64> %1) 776 store <2 x i64> %2, <2 x i64>* @llvm_mips_asub_u_d_RES 777 ret void 778 } 779 780 declare <2 x i64> @llvm.mips.asub.u.d(<2 x i64>, <2 x i64>) nounwind 781 782 ; CHECK: llvm_mips_asub_u_d_test: 783 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_asub_u_d_ARG1) 784 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_asub_u_d_ARG2) 785 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 786 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 787 ; CHECK-DAG: asub_u.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 788 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_asub_u_d_RES) 789 ; CHECK-DAG: st.d [[WD]], 0([[R3]]) 790 ; CHECK: .size llvm_mips_asub_u_d_test 791 ; 792 @llvm_mips_ave_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 793 @llvm_mips_ave_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 794 @llvm_mips_ave_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 795 796 define void @llvm_mips_ave_s_b_test() nounwind { 797 entry: 798 %0 = load <16 x i8>* @llvm_mips_ave_s_b_ARG1 799 %1 = load <16 x i8>* @llvm_mips_ave_s_b_ARG2 800 %2 = tail call <16 x i8> @llvm.mips.ave.s.b(<16 x i8> %0, <16 x i8> %1) 801 store <16 x i8> %2, <16 x i8>* @llvm_mips_ave_s_b_RES 802 ret void 803 } 804 805 declare <16 x i8> @llvm.mips.ave.s.b(<16 x i8>, <16 x i8>) nounwind 806 807 ; CHECK: llvm_mips_ave_s_b_test: 808 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_s_b_ARG1) 809 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_s_b_ARG2) 810 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 811 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 812 ; CHECK-DAG: ave_s.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 813 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_s_b_RES) 814 ; CHECK-DAG: st.b [[WD]], 0([[R3]]) 815 ; CHECK: .size llvm_mips_ave_s_b_test 816 ; 817 @llvm_mips_ave_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 818 @llvm_mips_ave_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 819 @llvm_mips_ave_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 820 821 define void @llvm_mips_ave_s_h_test() nounwind { 822 entry: 823 %0 = load <8 x i16>* @llvm_mips_ave_s_h_ARG1 824 %1 = load <8 x i16>* @llvm_mips_ave_s_h_ARG2 825 %2 = tail call <8 x i16> @llvm.mips.ave.s.h(<8 x i16> %0, <8 x i16> %1) 826 store <8 x i16> %2, <8 x i16>* @llvm_mips_ave_s_h_RES 827 ret void 828 } 829 830 declare <8 x i16> @llvm.mips.ave.s.h(<8 x i16>, <8 x i16>) nounwind 831 832 ; CHECK: llvm_mips_ave_s_h_test: 833 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_s_h_ARG1) 834 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_s_h_ARG2) 835 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 836 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 837 ; CHECK-DAG: ave_s.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 838 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_s_h_RES) 839 ; CHECK-DAG: st.h [[WD]], 0([[R3]]) 840 ; CHECK: .size llvm_mips_ave_s_h_test 841 ; 842 @llvm_mips_ave_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 843 @llvm_mips_ave_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 844 @llvm_mips_ave_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 845 846 define void @llvm_mips_ave_s_w_test() nounwind { 847 entry: 848 %0 = load <4 x i32>* @llvm_mips_ave_s_w_ARG1 849 %1 = load <4 x i32>* @llvm_mips_ave_s_w_ARG2 850 %2 = tail call <4 x i32> @llvm.mips.ave.s.w(<4 x i32> %0, <4 x i32> %1) 851 store <4 x i32> %2, <4 x i32>* @llvm_mips_ave_s_w_RES 852 ret void 853 } 854 855 declare <4 x i32> @llvm.mips.ave.s.w(<4 x i32>, <4 x i32>) nounwind 856 857 ; CHECK: llvm_mips_ave_s_w_test: 858 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_s_w_ARG1) 859 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_s_w_ARG2) 860 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 861 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 862 ; CHECK-DAG: ave_s.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 863 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_s_w_RES) 864 ; CHECK-DAG: st.w [[WD]], 0([[R3]]) 865 ; CHECK: .size llvm_mips_ave_s_w_test 866 ; 867 @llvm_mips_ave_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 868 @llvm_mips_ave_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 869 @llvm_mips_ave_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 870 871 define void @llvm_mips_ave_s_d_test() nounwind { 872 entry: 873 %0 = load <2 x i64>* @llvm_mips_ave_s_d_ARG1 874 %1 = load <2 x i64>* @llvm_mips_ave_s_d_ARG2 875 %2 = tail call <2 x i64> @llvm.mips.ave.s.d(<2 x i64> %0, <2 x i64> %1) 876 store <2 x i64> %2, <2 x i64>* @llvm_mips_ave_s_d_RES 877 ret void 878 } 879 880 declare <2 x i64> @llvm.mips.ave.s.d(<2 x i64>, <2 x i64>) nounwind 881 882 ; CHECK: llvm_mips_ave_s_d_test: 883 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_s_d_ARG1) 884 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_s_d_ARG2) 885 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 886 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 887 ; CHECK-DAG: ave_s.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 888 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_s_d_RES) 889 ; CHECK-DAG: st.d [[WD]], 0([[R3]]) 890 ; CHECK: .size llvm_mips_ave_s_d_test 891 ; 892 @llvm_mips_ave_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 893 @llvm_mips_ave_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 894 @llvm_mips_ave_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 895 896 define void @llvm_mips_ave_u_b_test() nounwind { 897 entry: 898 %0 = load <16 x i8>* @llvm_mips_ave_u_b_ARG1 899 %1 = load <16 x i8>* @llvm_mips_ave_u_b_ARG2 900 %2 = tail call <16 x i8> @llvm.mips.ave.u.b(<16 x i8> %0, <16 x i8> %1) 901 store <16 x i8> %2, <16 x i8>* @llvm_mips_ave_u_b_RES 902 ret void 903 } 904 905 declare <16 x i8> @llvm.mips.ave.u.b(<16 x i8>, <16 x i8>) nounwind 906 907 ; CHECK: llvm_mips_ave_u_b_test: 908 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_u_b_ARG1) 909 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_u_b_ARG2) 910 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 911 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 912 ; CHECK-DAG: ave_u.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 913 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_u_b_RES) 914 ; CHECK-DAG: st.b [[WD]], 0([[R3]]) 915 ; CHECK: .size llvm_mips_ave_u_b_test 916 ; 917 @llvm_mips_ave_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 918 @llvm_mips_ave_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 919 @llvm_mips_ave_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 920 921 define void @llvm_mips_ave_u_h_test() nounwind { 922 entry: 923 %0 = load <8 x i16>* @llvm_mips_ave_u_h_ARG1 924 %1 = load <8 x i16>* @llvm_mips_ave_u_h_ARG2 925 %2 = tail call <8 x i16> @llvm.mips.ave.u.h(<8 x i16> %0, <8 x i16> %1) 926 store <8 x i16> %2, <8 x i16>* @llvm_mips_ave_u_h_RES 927 ret void 928 } 929 930 declare <8 x i16> @llvm.mips.ave.u.h(<8 x i16>, <8 x i16>) nounwind 931 932 ; CHECK: llvm_mips_ave_u_h_test: 933 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_u_h_ARG1) 934 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_u_h_ARG2) 935 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 936 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 937 ; CHECK-DAG: ave_u.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 938 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_u_h_RES) 939 ; CHECK-DAG: st.h [[WD]], 0([[R3]]) 940 ; CHECK: .size llvm_mips_ave_u_h_test 941 ; 942 @llvm_mips_ave_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 943 @llvm_mips_ave_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 944 @llvm_mips_ave_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 945 946 define void @llvm_mips_ave_u_w_test() nounwind { 947 entry: 948 %0 = load <4 x i32>* @llvm_mips_ave_u_w_ARG1 949 %1 = load <4 x i32>* @llvm_mips_ave_u_w_ARG2 950 %2 = tail call <4 x i32> @llvm.mips.ave.u.w(<4 x i32> %0, <4 x i32> %1) 951 store <4 x i32> %2, <4 x i32>* @llvm_mips_ave_u_w_RES 952 ret void 953 } 954 955 declare <4 x i32> @llvm.mips.ave.u.w(<4 x i32>, <4 x i32>) nounwind 956 957 ; CHECK: llvm_mips_ave_u_w_test: 958 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_u_w_ARG1) 959 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_u_w_ARG2) 960 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 961 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 962 ; CHECK-DAG: ave_u.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 963 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_u_w_RES) 964 ; CHECK-DAG: st.w [[WD]], 0([[R3]]) 965 ; CHECK: .size llvm_mips_ave_u_w_test 966 ; 967 @llvm_mips_ave_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 968 @llvm_mips_ave_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 969 @llvm_mips_ave_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 970 971 define void @llvm_mips_ave_u_d_test() nounwind { 972 entry: 973 %0 = load <2 x i64>* @llvm_mips_ave_u_d_ARG1 974 %1 = load <2 x i64>* @llvm_mips_ave_u_d_ARG2 975 %2 = tail call <2 x i64> @llvm.mips.ave.u.d(<2 x i64> %0, <2 x i64> %1) 976 store <2 x i64> %2, <2 x i64>* @llvm_mips_ave_u_d_RES 977 ret void 978 } 979 980 declare <2 x i64> @llvm.mips.ave.u.d(<2 x i64>, <2 x i64>) nounwind 981 982 ; CHECK: llvm_mips_ave_u_d_test: 983 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ave_u_d_ARG1) 984 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ave_u_d_ARG2) 985 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 986 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 987 ; CHECK-DAG: ave_u.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 988 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_ave_u_d_RES) 989 ; CHECK-DAG: st.d [[WD]], 0([[R3]]) 990 ; CHECK: .size llvm_mips_ave_u_d_test 991 ; 992 @llvm_mips_aver_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 993 @llvm_mips_aver_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 994 @llvm_mips_aver_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 995 996 define void @llvm_mips_aver_s_b_test() nounwind { 997 entry: 998 %0 = load <16 x i8>* @llvm_mips_aver_s_b_ARG1 999 %1 = load <16 x i8>* @llvm_mips_aver_s_b_ARG2 1000 %2 = tail call <16 x i8> @llvm.mips.aver.s.b(<16 x i8> %0, <16 x i8> %1) 1001 store <16 x i8> %2, <16 x i8>* @llvm_mips_aver_s_b_RES 1002 ret void 1003 } 1004 1005 declare <16 x i8> @llvm.mips.aver.s.b(<16 x i8>, <16 x i8>) nounwind 1006 1007 ; CHECK: llvm_mips_aver_s_b_test: 1008 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_s_b_ARG1) 1009 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_s_b_ARG2) 1010 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 1011 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 1012 ; CHECK-DAG: aver_s.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1013 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_s_b_RES) 1014 ; CHECK-DAG: st.b [[WD]], 0([[R3]]) 1015 ; CHECK: .size llvm_mips_aver_s_b_test 1016 ; 1017 @llvm_mips_aver_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 1018 @llvm_mips_aver_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 1019 @llvm_mips_aver_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 1020 1021 define void @llvm_mips_aver_s_h_test() nounwind { 1022 entry: 1023 %0 = load <8 x i16>* @llvm_mips_aver_s_h_ARG1 1024 %1 = load <8 x i16>* @llvm_mips_aver_s_h_ARG2 1025 %2 = tail call <8 x i16> @llvm.mips.aver.s.h(<8 x i16> %0, <8 x i16> %1) 1026 store <8 x i16> %2, <8 x i16>* @llvm_mips_aver_s_h_RES 1027 ret void 1028 } 1029 1030 declare <8 x i16> @llvm.mips.aver.s.h(<8 x i16>, <8 x i16>) nounwind 1031 1032 ; CHECK: llvm_mips_aver_s_h_test: 1033 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_s_h_ARG1) 1034 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_s_h_ARG2) 1035 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 1036 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 1037 ; CHECK-DAG: aver_s.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1038 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_s_h_RES) 1039 ; CHECK-DAG: st.h [[WD]], 0([[R3]]) 1040 ; CHECK: .size llvm_mips_aver_s_h_test 1041 ; 1042 @llvm_mips_aver_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 1043 @llvm_mips_aver_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 1044 @llvm_mips_aver_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 1045 1046 define void @llvm_mips_aver_s_w_test() nounwind { 1047 entry: 1048 %0 = load <4 x i32>* @llvm_mips_aver_s_w_ARG1 1049 %1 = load <4 x i32>* @llvm_mips_aver_s_w_ARG2 1050 %2 = tail call <4 x i32> @llvm.mips.aver.s.w(<4 x i32> %0, <4 x i32> %1) 1051 store <4 x i32> %2, <4 x i32>* @llvm_mips_aver_s_w_RES 1052 ret void 1053 } 1054 1055 declare <4 x i32> @llvm.mips.aver.s.w(<4 x i32>, <4 x i32>) nounwind 1056 1057 ; CHECK: llvm_mips_aver_s_w_test: 1058 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_s_w_ARG1) 1059 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_s_w_ARG2) 1060 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 1061 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 1062 ; CHECK-DAG: aver_s.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1063 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_s_w_RES) 1064 ; CHECK-DAG: st.w [[WD]], 0([[R3]]) 1065 ; CHECK: .size llvm_mips_aver_s_w_test 1066 ; 1067 @llvm_mips_aver_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 1068 @llvm_mips_aver_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 1069 @llvm_mips_aver_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 1070 1071 define void @llvm_mips_aver_s_d_test() nounwind { 1072 entry: 1073 %0 = load <2 x i64>* @llvm_mips_aver_s_d_ARG1 1074 %1 = load <2 x i64>* @llvm_mips_aver_s_d_ARG2 1075 %2 = tail call <2 x i64> @llvm.mips.aver.s.d(<2 x i64> %0, <2 x i64> %1) 1076 store <2 x i64> %2, <2 x i64>* @llvm_mips_aver_s_d_RES 1077 ret void 1078 } 1079 1080 declare <2 x i64> @llvm.mips.aver.s.d(<2 x i64>, <2 x i64>) nounwind 1081 1082 ; CHECK: llvm_mips_aver_s_d_test: 1083 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_s_d_ARG1) 1084 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_s_d_ARG2) 1085 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 1086 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 1087 ; CHECK-DAG: aver_s.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1088 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_s_d_RES) 1089 ; CHECK-DAG: st.d [[WD]], 0([[R3]]) 1090 ; CHECK: .size llvm_mips_aver_s_d_test 1091 ; 1092 @llvm_mips_aver_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 1093 @llvm_mips_aver_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 1094 @llvm_mips_aver_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 1095 1096 define void @llvm_mips_aver_u_b_test() nounwind { 1097 entry: 1098 %0 = load <16 x i8>* @llvm_mips_aver_u_b_ARG1 1099 %1 = load <16 x i8>* @llvm_mips_aver_u_b_ARG2 1100 %2 = tail call <16 x i8> @llvm.mips.aver.u.b(<16 x i8> %0, <16 x i8> %1) 1101 store <16 x i8> %2, <16 x i8>* @llvm_mips_aver_u_b_RES 1102 ret void 1103 } 1104 1105 declare <16 x i8> @llvm.mips.aver.u.b(<16 x i8>, <16 x i8>) nounwind 1106 1107 ; CHECK: llvm_mips_aver_u_b_test: 1108 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_u_b_ARG1) 1109 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_u_b_ARG2) 1110 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 1111 ; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) 1112 ; CHECK-DAG: aver_u.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1113 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_u_b_RES) 1114 ; CHECK-DAG: st.b [[WD]], 0([[R3]]) 1115 ; CHECK: .size llvm_mips_aver_u_b_test 1116 ; 1117 @llvm_mips_aver_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 1118 @llvm_mips_aver_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 1119 @llvm_mips_aver_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 1120 1121 define void @llvm_mips_aver_u_h_test() nounwind { 1122 entry: 1123 %0 = load <8 x i16>* @llvm_mips_aver_u_h_ARG1 1124 %1 = load <8 x i16>* @llvm_mips_aver_u_h_ARG2 1125 %2 = tail call <8 x i16> @llvm.mips.aver.u.h(<8 x i16> %0, <8 x i16> %1) 1126 store <8 x i16> %2, <8 x i16>* @llvm_mips_aver_u_h_RES 1127 ret void 1128 } 1129 1130 declare <8 x i16> @llvm.mips.aver.u.h(<8 x i16>, <8 x i16>) nounwind 1131 1132 ; CHECK: llvm_mips_aver_u_h_test: 1133 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_u_h_ARG1) 1134 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_u_h_ARG2) 1135 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 1136 ; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) 1137 ; CHECK-DAG: aver_u.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1138 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_u_h_RES) 1139 ; CHECK-DAG: st.h [[WD]], 0([[R3]]) 1140 ; CHECK: .size llvm_mips_aver_u_h_test 1141 ; 1142 @llvm_mips_aver_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 1143 @llvm_mips_aver_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 1144 @llvm_mips_aver_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 1145 1146 define void @llvm_mips_aver_u_w_test() nounwind { 1147 entry: 1148 %0 = load <4 x i32>* @llvm_mips_aver_u_w_ARG1 1149 %1 = load <4 x i32>* @llvm_mips_aver_u_w_ARG2 1150 %2 = tail call <4 x i32> @llvm.mips.aver.u.w(<4 x i32> %0, <4 x i32> %1) 1151 store <4 x i32> %2, <4 x i32>* @llvm_mips_aver_u_w_RES 1152 ret void 1153 } 1154 1155 declare <4 x i32> @llvm.mips.aver.u.w(<4 x i32>, <4 x i32>) nounwind 1156 1157 ; CHECK: llvm_mips_aver_u_w_test: 1158 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_u_w_ARG1) 1159 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_u_w_ARG2) 1160 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 1161 ; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) 1162 ; CHECK-DAG: aver_u.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1163 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_u_w_RES) 1164 ; CHECK-DAG: st.w [[WD]], 0([[R3]]) 1165 ; CHECK: .size llvm_mips_aver_u_w_test 1166 ; 1167 @llvm_mips_aver_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 1168 @llvm_mips_aver_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 1169 @llvm_mips_aver_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 1170 1171 define void @llvm_mips_aver_u_d_test() nounwind { 1172 entry: 1173 %0 = load <2 x i64>* @llvm_mips_aver_u_d_ARG1 1174 %1 = load <2 x i64>* @llvm_mips_aver_u_d_ARG2 1175 %2 = tail call <2 x i64> @llvm.mips.aver.u.d(<2 x i64> %0, <2 x i64> %1) 1176 store <2 x i64> %2, <2 x i64>* @llvm_mips_aver_u_d_RES 1177 ret void 1178 } 1179 1180 declare <2 x i64> @llvm.mips.aver.u.d(<2 x i64>, <2 x i64>) nounwind 1181 1182 ; CHECK: llvm_mips_aver_u_d_test: 1183 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_aver_u_d_ARG1) 1184 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_aver_u_d_ARG2) 1185 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 1186 ; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) 1187 ; CHECK-DAG: aver_u.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] 1188 ; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_aver_u_d_RES) 1189 ; CHECK-DAG: st.d [[WD]], 0([[R3]]) 1190 ; CHECK: .size llvm_mips_aver_u_d_test 1191 ; 1192
