1 ; Test the MSA intrinsics that are encoded with the 3R instruction format. 2 ; There are lots of these so this covers those beginning with 'd' 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7 @llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8 @llvm_mips_div_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 9 @llvm_mips_div_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 10 11 define void @llvm_mips_div_s_b_test() nounwind { 12 entry: 13 %0 = load <16 x i8>* @llvm_mips_div_s_b_ARG1 14 %1 = load <16 x i8>* @llvm_mips_div_s_b_ARG2 15 %2 = tail call <16 x i8> @llvm.mips.div.s.b(<16 x i8> %0, <16 x i8> %1) 16 store <16 x i8> %2, <16 x i8>* @llvm_mips_div_s_b_RES 17 ret void 18 } 19 20 declare <16 x i8> @llvm.mips.div.s.b(<16 x i8>, <16 x i8>) nounwind 21 22 ; CHECK: llvm_mips_div_s_b_test: 23 ; CHECK: ld.b 24 ; CHECK: ld.b 25 ; CHECK: div_s.b 26 ; CHECK: st.b 27 ; CHECK: .size llvm_mips_div_s_b_test 28 ; 29 @llvm_mips_div_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 30 @llvm_mips_div_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 31 @llvm_mips_div_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 32 33 define void @llvm_mips_div_s_h_test() nounwind { 34 entry: 35 %0 = load <8 x i16>* @llvm_mips_div_s_h_ARG1 36 %1 = load <8 x i16>* @llvm_mips_div_s_h_ARG2 37 %2 = tail call <8 x i16> @llvm.mips.div.s.h(<8 x i16> %0, <8 x i16> %1) 38 store <8 x i16> %2, <8 x i16>* @llvm_mips_div_s_h_RES 39 ret void 40 } 41 42 declare <8 x i16> @llvm.mips.div.s.h(<8 x i16>, <8 x i16>) nounwind 43 44 ; CHECK: llvm_mips_div_s_h_test: 45 ; CHECK: ld.h 46 ; CHECK: ld.h 47 ; CHECK: div_s.h 48 ; CHECK: st.h 49 ; CHECK: .size llvm_mips_div_s_h_test 50 ; 51 @llvm_mips_div_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 52 @llvm_mips_div_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 53 @llvm_mips_div_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 54 55 define void @llvm_mips_div_s_w_test() nounwind { 56 entry: 57 %0 = load <4 x i32>* @llvm_mips_div_s_w_ARG1 58 %1 = load <4 x i32>* @llvm_mips_div_s_w_ARG2 59 %2 = tail call <4 x i32> @llvm.mips.div.s.w(<4 x i32> %0, <4 x i32> %1) 60 store <4 x i32> %2, <4 x i32>* @llvm_mips_div_s_w_RES 61 ret void 62 } 63 64 declare <4 x i32> @llvm.mips.div.s.w(<4 x i32>, <4 x i32>) nounwind 65 66 ; CHECK: llvm_mips_div_s_w_test: 67 ; CHECK: ld.w 68 ; CHECK: ld.w 69 ; CHECK: div_s.w 70 ; CHECK: st.w 71 ; CHECK: .size llvm_mips_div_s_w_test 72 ; 73 @llvm_mips_div_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 74 @llvm_mips_div_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 75 @llvm_mips_div_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 76 77 define void @llvm_mips_div_s_d_test() nounwind { 78 entry: 79 %0 = load <2 x i64>* @llvm_mips_div_s_d_ARG1 80 %1 = load <2 x i64>* @llvm_mips_div_s_d_ARG2 81 %2 = tail call <2 x i64> @llvm.mips.div.s.d(<2 x i64> %0, <2 x i64> %1) 82 store <2 x i64> %2, <2 x i64>* @llvm_mips_div_s_d_RES 83 ret void 84 } 85 86 declare <2 x i64> @llvm.mips.div.s.d(<2 x i64>, <2 x i64>) nounwind 87 88 ; CHECK: llvm_mips_div_s_d_test: 89 ; CHECK: ld.d 90 ; CHECK: ld.d 91 ; CHECK: div_s.d 92 ; CHECK: st.d 93 ; CHECK: .size llvm_mips_div_s_d_test 94 ; 95 96 define void @div_s_b_test() nounwind { 97 entry: 98 %0 = load <16 x i8>* @llvm_mips_div_s_b_ARG1 99 %1 = load <16 x i8>* @llvm_mips_div_s_b_ARG2 100 %2 = sdiv <16 x i8> %0, %1 101 store <16 x i8> %2, <16 x i8>* @llvm_mips_div_s_b_RES 102 ret void 103 } 104 105 ; CHECK: div_s_b_test: 106 ; CHECK: ld.b 107 ; CHECK: ld.b 108 ; CHECK: div_s.b 109 ; CHECK: st.b 110 ; CHECK: .size div_s_b_test 111 112 define void @div_s_h_test() nounwind { 113 entry: 114 %0 = load <8 x i16>* @llvm_mips_div_s_h_ARG1 115 %1 = load <8 x i16>* @llvm_mips_div_s_h_ARG2 116 %2 = sdiv <8 x i16> %0, %1 117 store <8 x i16> %2, <8 x i16>* @llvm_mips_div_s_h_RES 118 ret void 119 } 120 121 ; CHECK: div_s_h_test: 122 ; CHECK: ld.h 123 ; CHECK: ld.h 124 ; CHECK: div_s.h 125 ; CHECK: st.h 126 ; CHECK: .size div_s_h_test 127 128 define void @div_s_w_test() nounwind { 129 entry: 130 %0 = load <4 x i32>* @llvm_mips_div_s_w_ARG1 131 %1 = load <4 x i32>* @llvm_mips_div_s_w_ARG2 132 %2 = sdiv <4 x i32> %0, %1 133 store <4 x i32> %2, <4 x i32>* @llvm_mips_div_s_w_RES 134 ret void 135 } 136 137 ; CHECK: div_s_w_test: 138 ; CHECK: ld.w 139 ; CHECK: ld.w 140 ; CHECK: div_s.w 141 ; CHECK: st.w 142 ; CHECK: .size div_s_w_test 143 144 define void @div_s_d_test() nounwind { 145 entry: 146 %0 = load <2 x i64>* @llvm_mips_div_s_d_ARG1 147 %1 = load <2 x i64>* @llvm_mips_div_s_d_ARG2 148 %2 = sdiv <2 x i64> %0, %1 149 store <2 x i64> %2, <2 x i64>* @llvm_mips_div_s_d_RES 150 ret void 151 } 152 153 ; CHECK: div_s_d_test: 154 ; CHECK: ld.d 155 ; CHECK: ld.d 156 ; CHECK: div_s.d 157 ; CHECK: st.d 158 ; CHECK: .size div_s_d_test 159 ; 160 @llvm_mips_div_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 161 @llvm_mips_div_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 162 @llvm_mips_div_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 163 164 define void @llvm_mips_div_u_b_test() nounwind { 165 entry: 166 %0 = load <16 x i8>* @llvm_mips_div_u_b_ARG1 167 %1 = load <16 x i8>* @llvm_mips_div_u_b_ARG2 168 %2 = tail call <16 x i8> @llvm.mips.div.u.b(<16 x i8> %0, <16 x i8> %1) 169 store <16 x i8> %2, <16 x i8>* @llvm_mips_div_u_b_RES 170 ret void 171 } 172 173 declare <16 x i8> @llvm.mips.div.u.b(<16 x i8>, <16 x i8>) nounwind 174 175 ; CHECK: llvm_mips_div_u_b_test: 176 ; CHECK: ld.b 177 ; CHECK: ld.b 178 ; CHECK: div_u.b 179 ; CHECK: st.b 180 ; CHECK: .size llvm_mips_div_u_b_test 181 ; 182 @llvm_mips_div_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 183 @llvm_mips_div_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 184 @llvm_mips_div_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 185 186 define void @llvm_mips_div_u_h_test() nounwind { 187 entry: 188 %0 = load <8 x i16>* @llvm_mips_div_u_h_ARG1 189 %1 = load <8 x i16>* @llvm_mips_div_u_h_ARG2 190 %2 = tail call <8 x i16> @llvm.mips.div.u.h(<8 x i16> %0, <8 x i16> %1) 191 store <8 x i16> %2, <8 x i16>* @llvm_mips_div_u_h_RES 192 ret void 193 } 194 195 declare <8 x i16> @llvm.mips.div.u.h(<8 x i16>, <8 x i16>) nounwind 196 197 ; CHECK: llvm_mips_div_u_h_test: 198 ; CHECK: ld.h 199 ; CHECK: ld.h 200 ; CHECK: div_u.h 201 ; CHECK: st.h 202 ; CHECK: .size llvm_mips_div_u_h_test 203 ; 204 @llvm_mips_div_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 205 @llvm_mips_div_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 206 @llvm_mips_div_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 207 208 define void @llvm_mips_div_u_w_test() nounwind { 209 entry: 210 %0 = load <4 x i32>* @llvm_mips_div_u_w_ARG1 211 %1 = load <4 x i32>* @llvm_mips_div_u_w_ARG2 212 %2 = tail call <4 x i32> @llvm.mips.div.u.w(<4 x i32> %0, <4 x i32> %1) 213 store <4 x i32> %2, <4 x i32>* @llvm_mips_div_u_w_RES 214 ret void 215 } 216 217 declare <4 x i32> @llvm.mips.div.u.w(<4 x i32>, <4 x i32>) nounwind 218 219 ; CHECK: llvm_mips_div_u_w_test: 220 ; CHECK: ld.w 221 ; CHECK: ld.w 222 ; CHECK: div_u.w 223 ; CHECK: st.w 224 ; CHECK: .size llvm_mips_div_u_w_test 225 ; 226 @llvm_mips_div_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 227 @llvm_mips_div_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 228 @llvm_mips_div_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 229 230 define void @llvm_mips_div_u_d_test() nounwind { 231 entry: 232 %0 = load <2 x i64>* @llvm_mips_div_u_d_ARG1 233 %1 = load <2 x i64>* @llvm_mips_div_u_d_ARG2 234 %2 = tail call <2 x i64> @llvm.mips.div.u.d(<2 x i64> %0, <2 x i64> %1) 235 store <2 x i64> %2, <2 x i64>* @llvm_mips_div_u_d_RES 236 ret void 237 } 238 239 declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>) nounwind 240 241 ; CHECK: llvm_mips_div_u_d_test: 242 ; CHECK: ld.d 243 ; CHECK: ld.d 244 ; CHECK: div_u.d 245 ; CHECK: st.d 246 ; CHECK: .size llvm_mips_div_u_d_test 247 ; 248 249 define void @div_u_b_test() nounwind { 250 entry: 251 %0 = load <16 x i8>* @llvm_mips_div_u_b_ARG1 252 %1 = load <16 x i8>* @llvm_mips_div_u_b_ARG2 253 %2 = udiv <16 x i8> %0, %1 254 store <16 x i8> %2, <16 x i8>* @llvm_mips_div_u_b_RES 255 ret void 256 } 257 258 ; CHECK: div_u_b_test: 259 ; CHECK: ld.b 260 ; CHECK: ld.b 261 ; CHECK: div_u.b 262 ; CHECK: st.b 263 ; CHECK: .size div_u_b_test 264 265 define void @div_u_h_test() nounwind { 266 entry: 267 %0 = load <8 x i16>* @llvm_mips_div_u_h_ARG1 268 %1 = load <8 x i16>* @llvm_mips_div_u_h_ARG2 269 %2 = udiv <8 x i16> %0, %1 270 store <8 x i16> %2, <8 x i16>* @llvm_mips_div_u_h_RES 271 ret void 272 } 273 274 ; CHECK: div_u_h_test: 275 ; CHECK: ld.h 276 ; CHECK: ld.h 277 ; CHECK: div_u.h 278 ; CHECK: st.h 279 ; CHECK: .size div_u_h_test 280 281 define void @div_u_w_test() nounwind { 282 entry: 283 %0 = load <4 x i32>* @llvm_mips_div_u_w_ARG1 284 %1 = load <4 x i32>* @llvm_mips_div_u_w_ARG2 285 %2 = udiv <4 x i32> %0, %1 286 store <4 x i32> %2, <4 x i32>* @llvm_mips_div_u_w_RES 287 ret void 288 } 289 290 ; CHECK: div_u_w_test: 291 ; CHECK: ld.w 292 ; CHECK: ld.w 293 ; CHECK: div_u.w 294 ; CHECK: st.w 295 ; CHECK: .size div_u_w_test 296 297 define void @div_u_d_test() nounwind { 298 entry: 299 %0 = load <2 x i64>* @llvm_mips_div_u_d_ARG1 300 %1 = load <2 x i64>* @llvm_mips_div_u_d_ARG2 301 %2 = udiv <2 x i64> %0, %1 302 store <2 x i64> %2, <2 x i64>* @llvm_mips_div_u_d_RES 303 ret void 304 } 305 306 ; CHECK: div_u_d_test: 307 ; CHECK: ld.d 308 ; CHECK: ld.d 309 ; CHECK: div_u.d 310 ; CHECK: st.d 311 ; CHECK: .size div_u_d_test 312 ; 313 @llvm_mips_dotp_s_h_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, 314 i8 4, i8 5, i8 6, i8 7, 315 i8 8, i8 9, i8 10, i8 11, 316 i8 12, i8 13, i8 14, i8 15>, 317 align 16 318 @llvm_mips_dotp_s_h_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, 319 i8 20, i8 21, i8 22, i8 23, 320 i8 24, i8 25, i8 26, i8 27, 321 i8 28, i8 29, i8 30, i8 31>, 322 align 16 323 @llvm_mips_dotp_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, 324 i16 0, i16 0, i16 0, i16 0>, 325 align 16 326 327 define void @llvm_mips_dotp_s_h_test() nounwind { 328 entry: 329 %0 = load <16 x i8>* @llvm_mips_dotp_s_h_ARG1 330 %1 = load <16 x i8>* @llvm_mips_dotp_s_h_ARG2 331 %2 = tail call <8 x i16> @llvm.mips.dotp.s.h(<16 x i8> %0, <16 x i8> %1) 332 store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_s_h_RES 333 ret void 334 } 335 336 declare <8 x i16> @llvm.mips.dotp.s.h(<16 x i8>, <16 x i8>) nounwind 337 338 ; CHECK: llvm_mips_dotp_s_h_test: 339 ; CHECK: ld.b 340 ; CHECK: ld.b 341 ; CHECK: dotp_s.h 342 ; CHECK: st.h 343 ; CHECK: .size llvm_mips_dotp_s_h_test 344 ; 345 @llvm_mips_dotp_s_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, 346 i16 4, i16 5, i16 6, i16 7>, 347 align 16 348 @llvm_mips_dotp_s_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, 349 i16 8, i16 9, i16 10, i16 11>, 350 align 16 351 @llvm_mips_dotp_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, 352 align 16 353 354 define void @llvm_mips_dotp_s_w_test() nounwind { 355 entry: 356 %0 = load <8 x i16>* @llvm_mips_dotp_s_w_ARG1 357 %1 = load <8 x i16>* @llvm_mips_dotp_s_w_ARG2 358 %2 = tail call <4 x i32> @llvm.mips.dotp.s.w(<8 x i16> %0, <8 x i16> %1) 359 store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_s_w_RES 360 ret void 361 } 362 363 declare <4 x i32> @llvm.mips.dotp.s.w(<8 x i16>, <8 x i16>) nounwind 364 365 ; CHECK: llvm_mips_dotp_s_w_test: 366 ; CHECK: ld.h 367 ; CHECK: ld.h 368 ; CHECK: dotp_s.w 369 ; CHECK: st.w 370 ; CHECK: .size llvm_mips_dotp_s_w_test 371 ; 372 @llvm_mips_dotp_s_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 0, i32 1>, 373 align 16 374 @llvm_mips_dotp_s_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 2, i32 3>, 375 align 16 376 @llvm_mips_dotp_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 377 378 define void @llvm_mips_dotp_s_d_test() nounwind { 379 entry: 380 %0 = load <4 x i32>* @llvm_mips_dotp_s_d_ARG1 381 %1 = load <4 x i32>* @llvm_mips_dotp_s_d_ARG2 382 %2 = tail call <2 x i64> @llvm.mips.dotp.s.d(<4 x i32> %0, <4 x i32> %1) 383 store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_s_d_RES 384 ret void 385 } 386 387 declare <2 x i64> @llvm.mips.dotp.s.d(<4 x i32>, <4 x i32>) nounwind 388 389 ; CHECK: llvm_mips_dotp_s_d_test: 390 ; CHECK: ld.w 391 ; CHECK: ld.w 392 ; CHECK: dotp_s.d 393 ; CHECK: st.d 394 ; CHECK: .size llvm_mips_dotp_s_d_test 395 ; 396 @llvm_mips_dotp_u_h_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, 397 i8 4, i8 5, i8 6, i8 7, 398 i8 8, i8 9, i8 10, i8 11, 399 i8 12, i8 13, i8 14, i8 15>, 400 align 16 401 @llvm_mips_dotp_u_h_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, 402 i8 20, i8 21, i8 22, i8 23, 403 i8 24, i8 25, i8 26, i8 27, 404 i8 28, i8 29, i8 30, i8 31>, 405 align 16 406 @llvm_mips_dotp_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, 407 i16 0, i16 0, i16 0, i16 0>, 408 align 16 409 410 define void @llvm_mips_dotp_u_h_test() nounwind { 411 entry: 412 %0 = load <16 x i8>* @llvm_mips_dotp_u_h_ARG1 413 %1 = load <16 x i8>* @llvm_mips_dotp_u_h_ARG2 414 %2 = tail call <8 x i16> @llvm.mips.dotp.u.h(<16 x i8> %0, <16 x i8> %1) 415 store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_u_h_RES 416 ret void 417 } 418 419 declare <8 x i16> @llvm.mips.dotp.u.h(<16 x i8>, <16 x i8>) nounwind 420 421 ; CHECK: llvm_mips_dotp_u_h_test: 422 ; CHECK: ld.b 423 ; CHECK: ld.b 424 ; CHECK: dotp_u.h 425 ; CHECK: st.h 426 ; CHECK: .size llvm_mips_dotp_u_h_test 427 ; 428 @llvm_mips_dotp_u_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, 429 i16 4, i16 5, i16 6, i16 7>, 430 align 16 431 @llvm_mips_dotp_u_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, 432 i16 8, i16 9, i16 10, i16 11>, 433 align 16 434 @llvm_mips_dotp_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, 435 align 16 436 437 define void @llvm_mips_dotp_u_w_test() nounwind { 438 entry: 439 %0 = load <8 x i16>* @llvm_mips_dotp_u_w_ARG1 440 %1 = load <8 x i16>* @llvm_mips_dotp_u_w_ARG2 441 %2 = tail call <4 x i32> @llvm.mips.dotp.u.w(<8 x i16> %0, <8 x i16> %1) 442 store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_u_w_RES 443 ret void 444 } 445 446 declare <4 x i32> @llvm.mips.dotp.u.w(<8 x i16>, <8 x i16>) nounwind 447 448 ; CHECK: llvm_mips_dotp_u_w_test: 449 ; CHECK: ld.h 450 ; CHECK: ld.h 451 ; CHECK: dotp_u.w 452 ; CHECK: st.w 453 ; CHECK: .size llvm_mips_dotp_u_w_test 454 ; 455 @llvm_mips_dotp_u_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 0, i32 1>, 456 align 16 457 @llvm_mips_dotp_u_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 2, i32 3>, 458 align 16 459 @llvm_mips_dotp_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 460 461 define void @llvm_mips_dotp_u_d_test() nounwind { 462 entry: 463 %0 = load <4 x i32>* @llvm_mips_dotp_u_d_ARG1 464 %1 = load <4 x i32>* @llvm_mips_dotp_u_d_ARG2 465 %2 = tail call <2 x i64> @llvm.mips.dotp.u.d(<4 x i32> %0, <4 x i32> %1) 466 store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_u_d_RES 467 ret void 468 } 469 470 declare <2 x i64> @llvm.mips.dotp.u.d(<4 x i32>, <4 x i32>) nounwind 471 472 ; CHECK: llvm_mips_dotp_u_d_test: 473 ; CHECK: ld.w 474 ; CHECK: ld.w 475 ; CHECK: dotp_u.d 476 ; CHECK: st.d 477 ; CHECK: .size llvm_mips_dotp_u_d_test 478 ; 479
