1 ; Test the MSA intrinsics that are encoded with the 3R instruction format. 2 ; There are lots of these so this covers those beginning with 'i' 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7 @llvm_mips_ilvev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8 @llvm_mips_ilvev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 9 @llvm_mips_ilvev_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 10 11 define void @llvm_mips_ilvev_b_test() nounwind { 12 entry: 13 %0 = load <16 x i8>* @llvm_mips_ilvev_b_ARG1 14 %1 = load <16 x i8>* @llvm_mips_ilvev_b_ARG2 15 %2 = tail call <16 x i8> @llvm.mips.ilvev.b(<16 x i8> %0, <16 x i8> %1) 16 store <16 x i8> %2, <16 x i8>* @llvm_mips_ilvev_b_RES 17 ret void 18 } 19 20 declare <16 x i8> @llvm.mips.ilvev.b(<16 x i8>, <16 x i8>) nounwind 21 22 ; CHECK: llvm_mips_ilvev_b_test: 23 ; CHECK: ld.b 24 ; CHECK: ld.b 25 ; CHECK: ilvev.b 26 ; CHECK: st.b 27 ; CHECK: .size llvm_mips_ilvev_b_test 28 ; 29 @llvm_mips_ilvev_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 30 @llvm_mips_ilvev_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 31 @llvm_mips_ilvev_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 32 33 define void @llvm_mips_ilvev_h_test() nounwind { 34 entry: 35 %0 = load <8 x i16>* @llvm_mips_ilvev_h_ARG1 36 %1 = load <8 x i16>* @llvm_mips_ilvev_h_ARG2 37 %2 = tail call <8 x i16> @llvm.mips.ilvev.h(<8 x i16> %0, <8 x i16> %1) 38 store <8 x i16> %2, <8 x i16>* @llvm_mips_ilvev_h_RES 39 ret void 40 } 41 42 declare <8 x i16> @llvm.mips.ilvev.h(<8 x i16>, <8 x i16>) nounwind 43 44 ; CHECK: llvm_mips_ilvev_h_test: 45 ; CHECK: ld.h 46 ; CHECK: ld.h 47 ; CHECK: ilvev.h 48 ; CHECK: st.h 49 ; CHECK: .size llvm_mips_ilvev_h_test 50 ; 51 @llvm_mips_ilvev_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 52 @llvm_mips_ilvev_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 53 @llvm_mips_ilvev_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 54 55 define void @llvm_mips_ilvev_w_test() nounwind { 56 entry: 57 %0 = load <4 x i32>* @llvm_mips_ilvev_w_ARG1 58 %1 = load <4 x i32>* @llvm_mips_ilvev_w_ARG2 59 %2 = tail call <4 x i32> @llvm.mips.ilvev.w(<4 x i32> %0, <4 x i32> %1) 60 store <4 x i32> %2, <4 x i32>* @llvm_mips_ilvev_w_RES 61 ret void 62 } 63 64 declare <4 x i32> @llvm.mips.ilvev.w(<4 x i32>, <4 x i32>) nounwind 65 66 ; CHECK: llvm_mips_ilvev_w_test: 67 ; CHECK: ld.w 68 ; CHECK: ld.w 69 ; CHECK: ilvev.w 70 ; CHECK: st.w 71 ; CHECK: .size llvm_mips_ilvev_w_test 72 ; 73 @llvm_mips_ilvev_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 74 @llvm_mips_ilvev_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 75 @llvm_mips_ilvev_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 76 77 define void @llvm_mips_ilvev_d_test() nounwind { 78 entry: 79 %0 = load <2 x i64>* @llvm_mips_ilvev_d_ARG1 80 %1 = load <2 x i64>* @llvm_mips_ilvev_d_ARG2 81 %2 = tail call <2 x i64> @llvm.mips.ilvev.d(<2 x i64> %0, <2 x i64> %1) 82 store <2 x i64> %2, <2 x i64>* @llvm_mips_ilvev_d_RES 83 ret void 84 } 85 86 declare <2 x i64> @llvm.mips.ilvev.d(<2 x i64>, <2 x i64>) nounwind 87 88 ; CHECK: llvm_mips_ilvev_d_test: 89 ; CHECK: ld.d 90 ; CHECK: ld.d 91 ; CHECK: ilvev.d 92 ; CHECK: st.d 93 ; CHECK: .size llvm_mips_ilvev_d_test 94 ; 95 @llvm_mips_ilvl_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 96 @llvm_mips_ilvl_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 97 @llvm_mips_ilvl_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 98 99 define void @llvm_mips_ilvl_b_test() nounwind { 100 entry: 101 %0 = load <16 x i8>* @llvm_mips_ilvl_b_ARG1 102 %1 = load <16 x i8>* @llvm_mips_ilvl_b_ARG2 103 %2 = tail call <16 x i8> @llvm.mips.ilvl.b(<16 x i8> %0, <16 x i8> %1) 104 store <16 x i8> %2, <16 x i8>* @llvm_mips_ilvl_b_RES 105 ret void 106 } 107 108 declare <16 x i8> @llvm.mips.ilvl.b(<16 x i8>, <16 x i8>) nounwind 109 110 ; CHECK: llvm_mips_ilvl_b_test: 111 ; CHECK: ld.b 112 ; CHECK: ld.b 113 ; CHECK: ilvl.b 114 ; CHECK: st.b 115 ; CHECK: .size llvm_mips_ilvl_b_test 116 ; 117 @llvm_mips_ilvl_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 118 @llvm_mips_ilvl_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 119 @llvm_mips_ilvl_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 120 121 define void @llvm_mips_ilvl_h_test() nounwind { 122 entry: 123 %0 = load <8 x i16>* @llvm_mips_ilvl_h_ARG1 124 %1 = load <8 x i16>* @llvm_mips_ilvl_h_ARG2 125 %2 = tail call <8 x i16> @llvm.mips.ilvl.h(<8 x i16> %0, <8 x i16> %1) 126 store <8 x i16> %2, <8 x i16>* @llvm_mips_ilvl_h_RES 127 ret void 128 } 129 130 declare <8 x i16> @llvm.mips.ilvl.h(<8 x i16>, <8 x i16>) nounwind 131 132 ; CHECK: llvm_mips_ilvl_h_test: 133 ; CHECK: ld.h 134 ; CHECK: ld.h 135 ; CHECK: ilvl.h 136 ; CHECK: st.h 137 ; CHECK: .size llvm_mips_ilvl_h_test 138 ; 139 @llvm_mips_ilvl_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 140 @llvm_mips_ilvl_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 141 @llvm_mips_ilvl_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 142 143 define void @llvm_mips_ilvl_w_test() nounwind { 144 entry: 145 %0 = load <4 x i32>* @llvm_mips_ilvl_w_ARG1 146 %1 = load <4 x i32>* @llvm_mips_ilvl_w_ARG2 147 %2 = tail call <4 x i32> @llvm.mips.ilvl.w(<4 x i32> %0, <4 x i32> %1) 148 store <4 x i32> %2, <4 x i32>* @llvm_mips_ilvl_w_RES 149 ret void 150 } 151 152 declare <4 x i32> @llvm.mips.ilvl.w(<4 x i32>, <4 x i32>) nounwind 153 154 ; CHECK: llvm_mips_ilvl_w_test: 155 ; CHECK: ld.w 156 ; CHECK: ld.w 157 ; CHECK: ilvl.w 158 ; CHECK: st.w 159 ; CHECK: .size llvm_mips_ilvl_w_test 160 ; 161 @llvm_mips_ilvl_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 162 @llvm_mips_ilvl_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 163 @llvm_mips_ilvl_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 164 165 define void @llvm_mips_ilvl_d_test() nounwind { 166 entry: 167 %0 = load <2 x i64>* @llvm_mips_ilvl_d_ARG1 168 %1 = load <2 x i64>* @llvm_mips_ilvl_d_ARG2 169 %2 = tail call <2 x i64> @llvm.mips.ilvl.d(<2 x i64> %0, <2 x i64> %1) 170 store <2 x i64> %2, <2 x i64>* @llvm_mips_ilvl_d_RES 171 ret void 172 } 173 174 declare <2 x i64> @llvm.mips.ilvl.d(<2 x i64>, <2 x i64>) nounwind 175 176 ; CHECK: llvm_mips_ilvl_d_test: 177 ; CHECK: ld.d 178 ; CHECK: ld.d 179 ; CHECK: ilvl.d 180 ; CHECK: st.d 181 ; CHECK: .size llvm_mips_ilvl_d_test 182 ; 183 @llvm_mips_ilvod_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 184 @llvm_mips_ilvod_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 185 @llvm_mips_ilvod_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 186 187 define void @llvm_mips_ilvod_b_test() nounwind { 188 entry: 189 %0 = load <16 x i8>* @llvm_mips_ilvod_b_ARG1 190 %1 = load <16 x i8>* @llvm_mips_ilvod_b_ARG2 191 %2 = tail call <16 x i8> @llvm.mips.ilvod.b(<16 x i8> %0, <16 x i8> %1) 192 store <16 x i8> %2, <16 x i8>* @llvm_mips_ilvod_b_RES 193 ret void 194 } 195 196 declare <16 x i8> @llvm.mips.ilvod.b(<16 x i8>, <16 x i8>) nounwind 197 198 ; CHECK: llvm_mips_ilvod_b_test: 199 ; CHECK: ld.b 200 ; CHECK: ld.b 201 ; CHECK: ilvod.b 202 ; CHECK: st.b 203 ; CHECK: .size llvm_mips_ilvod_b_test 204 ; 205 @llvm_mips_ilvod_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 206 @llvm_mips_ilvod_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 207 @llvm_mips_ilvod_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 208 209 define void @llvm_mips_ilvod_h_test() nounwind { 210 entry: 211 %0 = load <8 x i16>* @llvm_mips_ilvod_h_ARG1 212 %1 = load <8 x i16>* @llvm_mips_ilvod_h_ARG2 213 %2 = tail call <8 x i16> @llvm.mips.ilvod.h(<8 x i16> %0, <8 x i16> %1) 214 store <8 x i16> %2, <8 x i16>* @llvm_mips_ilvod_h_RES 215 ret void 216 } 217 218 declare <8 x i16> @llvm.mips.ilvod.h(<8 x i16>, <8 x i16>) nounwind 219 220 ; CHECK: llvm_mips_ilvod_h_test: 221 ; CHECK: ld.h 222 ; CHECK: ld.h 223 ; CHECK: ilvod.h 224 ; CHECK: st.h 225 ; CHECK: .size llvm_mips_ilvod_h_test 226 ; 227 @llvm_mips_ilvod_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 228 @llvm_mips_ilvod_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 229 @llvm_mips_ilvod_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 230 231 define void @llvm_mips_ilvod_w_test() nounwind { 232 entry: 233 %0 = load <4 x i32>* @llvm_mips_ilvod_w_ARG1 234 %1 = load <4 x i32>* @llvm_mips_ilvod_w_ARG2 235 %2 = tail call <4 x i32> @llvm.mips.ilvod.w(<4 x i32> %0, <4 x i32> %1) 236 store <4 x i32> %2, <4 x i32>* @llvm_mips_ilvod_w_RES 237 ret void 238 } 239 240 declare <4 x i32> @llvm.mips.ilvod.w(<4 x i32>, <4 x i32>) nounwind 241 242 ; CHECK: llvm_mips_ilvod_w_test: 243 ; CHECK: ld.w 244 ; CHECK: ld.w 245 ; CHECK: ilvod.w 246 ; CHECK: st.w 247 ; CHECK: .size llvm_mips_ilvod_w_test 248 ; 249 @llvm_mips_ilvod_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 250 @llvm_mips_ilvod_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 251 @llvm_mips_ilvod_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 252 253 define void @llvm_mips_ilvod_d_test() nounwind { 254 entry: 255 %0 = load <2 x i64>* @llvm_mips_ilvod_d_ARG1 256 %1 = load <2 x i64>* @llvm_mips_ilvod_d_ARG2 257 %2 = tail call <2 x i64> @llvm.mips.ilvod.d(<2 x i64> %0, <2 x i64> %1) 258 store <2 x i64> %2, <2 x i64>* @llvm_mips_ilvod_d_RES 259 ret void 260 } 261 262 declare <2 x i64> @llvm.mips.ilvod.d(<2 x i64>, <2 x i64>) nounwind 263 264 ; CHECK: llvm_mips_ilvod_d_test: 265 ; CHECK: ld.d 266 ; CHECK: ld.d 267 ; CHECK: ilvod.d 268 ; CHECK: st.d 269 ; CHECK: .size llvm_mips_ilvod_d_test 270 ; 271 @llvm_mips_ilvr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 272 @llvm_mips_ilvr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 273 @llvm_mips_ilvr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 274 275 define void @llvm_mips_ilvr_b_test() nounwind { 276 entry: 277 %0 = load <16 x i8>* @llvm_mips_ilvr_b_ARG1 278 %1 = load <16 x i8>* @llvm_mips_ilvr_b_ARG2 279 %2 = tail call <16 x i8> @llvm.mips.ilvr.b(<16 x i8> %0, <16 x i8> %1) 280 store <16 x i8> %2, <16 x i8>* @llvm_mips_ilvr_b_RES 281 ret void 282 } 283 284 declare <16 x i8> @llvm.mips.ilvr.b(<16 x i8>, <16 x i8>) nounwind 285 286 ; CHECK: llvm_mips_ilvr_b_test: 287 ; CHECK: ld.b 288 ; CHECK: ld.b 289 ; CHECK: ilvr.b 290 ; CHECK: st.b 291 ; CHECK: .size llvm_mips_ilvr_b_test 292 ; 293 @llvm_mips_ilvr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 294 @llvm_mips_ilvr_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 295 @llvm_mips_ilvr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 296 297 define void @llvm_mips_ilvr_h_test() nounwind { 298 entry: 299 %0 = load <8 x i16>* @llvm_mips_ilvr_h_ARG1 300 %1 = load <8 x i16>* @llvm_mips_ilvr_h_ARG2 301 %2 = tail call <8 x i16> @llvm.mips.ilvr.h(<8 x i16> %0, <8 x i16> %1) 302 store <8 x i16> %2, <8 x i16>* @llvm_mips_ilvr_h_RES 303 ret void 304 } 305 306 declare <8 x i16> @llvm.mips.ilvr.h(<8 x i16>, <8 x i16>) nounwind 307 308 ; CHECK: llvm_mips_ilvr_h_test: 309 ; CHECK: ld.h 310 ; CHECK: ld.h 311 ; CHECK: ilvr.h 312 ; CHECK: st.h 313 ; CHECK: .size llvm_mips_ilvr_h_test 314 ; 315 @llvm_mips_ilvr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 316 @llvm_mips_ilvr_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 317 @llvm_mips_ilvr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 318 319 define void @llvm_mips_ilvr_w_test() nounwind { 320 entry: 321 %0 = load <4 x i32>* @llvm_mips_ilvr_w_ARG1 322 %1 = load <4 x i32>* @llvm_mips_ilvr_w_ARG2 323 %2 = tail call <4 x i32> @llvm.mips.ilvr.w(<4 x i32> %0, <4 x i32> %1) 324 store <4 x i32> %2, <4 x i32>* @llvm_mips_ilvr_w_RES 325 ret void 326 } 327 328 declare <4 x i32> @llvm.mips.ilvr.w(<4 x i32>, <4 x i32>) nounwind 329 330 ; CHECK: llvm_mips_ilvr_w_test: 331 ; CHECK: ld.w 332 ; CHECK: ld.w 333 ; CHECK: ilvr.w 334 ; CHECK: st.w 335 ; CHECK: .size llvm_mips_ilvr_w_test 336 ; 337 @llvm_mips_ilvr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 338 @llvm_mips_ilvr_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 339 @llvm_mips_ilvr_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 340 341 define void @llvm_mips_ilvr_d_test() nounwind { 342 entry: 343 %0 = load <2 x i64>* @llvm_mips_ilvr_d_ARG1 344 %1 = load <2 x i64>* @llvm_mips_ilvr_d_ARG2 345 %2 = tail call <2 x i64> @llvm.mips.ilvr.d(<2 x i64> %0, <2 x i64> %1) 346 store <2 x i64> %2, <2 x i64>* @llvm_mips_ilvr_d_RES 347 ret void 348 } 349 350 declare <2 x i64> @llvm.mips.ilvr.d(<2 x i64>, <2 x i64>) nounwind 351 352 ; CHECK: llvm_mips_ilvr_d_test: 353 ; CHECK: ld.d 354 ; CHECK: ld.d 355 ; CHECK: ilvr.d 356 ; CHECK: st.d 357 ; CHECK: .size llvm_mips_ilvr_d_test 358 ; 359
