1 ; Test the MSA splat intrinsics that are encoded with the 3R instruction 2 ; format. 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ 5 ; RUN: FileCheck -check-prefix=MIPS32 %s 6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ 7 ; RUN: FileCheck -check-prefix=MIPS32 %s 8 9 @llvm_mips_splat_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 10 @llvm_mips_splat_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 11 12 define void @llvm_mips_splat_b_test(i32 %a) nounwind { 13 entry: 14 %0 = load <16 x i8>* @llvm_mips_splat_b_ARG1 15 %1 = tail call <16 x i8> @llvm.mips.splat.b(<16 x i8> %0, i32 %a) 16 store <16 x i8> %1, <16 x i8>* @llvm_mips_splat_b_RES 17 ret void 18 } 19 20 declare <16 x i8> @llvm.mips.splat.b(<16 x i8>, i32) nounwind 21 22 ; MIPS32: llvm_mips_splat_b_test: 23 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_splat_b_ARG1)( 24 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_splat_b_RES)( 25 ; MIPS32-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) 26 ; MIPS32-DAG: splat.b [[R4:\$w[0-9]+]], [[R3]][$4] 27 ; MIPS32-DAG: st.b [[R4]], 0([[R2]]) 28 ; MIPS32: .size llvm_mips_splat_b_test 29 30 @llvm_mips_splat_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 31 @llvm_mips_splat_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 32 33 define void @llvm_mips_splat_h_test(i32 %a) nounwind { 34 entry: 35 %0 = load <8 x i16>* @llvm_mips_splat_h_ARG1 36 %1 = tail call <8 x i16> @llvm.mips.splat.h(<8 x i16> %0, i32 %a) 37 store <8 x i16> %1, <8 x i16>* @llvm_mips_splat_h_RES 38 ret void 39 } 40 41 declare <8 x i16> @llvm.mips.splat.h(<8 x i16>, i32) nounwind 42 43 ; MIPS32: llvm_mips_splat_h_test: 44 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_splat_h_ARG1)( 45 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_splat_h_RES)( 46 ; MIPS32-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]]) 47 ; MIPS32-DAG: splat.h [[R4:\$w[0-9]+]], [[R3]][$4] 48 ; MIPS32-DAG: st.h [[R4]], 0([[R2]]) 49 ; MIPS32: .size llvm_mips_splat_h_test 50 51 @llvm_mips_splat_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 52 @llvm_mips_splat_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 53 54 define void @llvm_mips_splat_w_test(i32 %a) nounwind { 55 entry: 56 %0 = load <4 x i32>* @llvm_mips_splat_w_ARG1 57 %1 = tail call <4 x i32> @llvm.mips.splat.w(<4 x i32> %0, i32 %a) 58 store <4 x i32> %1, <4 x i32>* @llvm_mips_splat_w_RES 59 ret void 60 } 61 62 declare <4 x i32> @llvm.mips.splat.w(<4 x i32>, i32) nounwind 63 64 ; MIPS32: llvm_mips_splat_w_test: 65 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_splat_w_ARG1)( 66 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_splat_w_RES)( 67 ; MIPS32-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]]) 68 ; MIPS32-DAG: splat.w [[R4:\$w[0-9]+]], [[R3]][$4] 69 ; MIPS32-DAG: st.w [[R4]], 0([[R2]]) 70 ; MIPS32: .size llvm_mips_splat_w_test 71 72 @llvm_mips_splat_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 73 @llvm_mips_splat_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 74 75 define void @llvm_mips_splat_d_test(i32 %a) nounwind { 76 entry: 77 %0 = load <2 x i64>* @llvm_mips_splat_d_ARG1 78 %1 = tail call <2 x i64> @llvm.mips.splat.d(<2 x i64> %0, i32 %a) 79 store <2 x i64> %1, <2 x i64>* @llvm_mips_splat_d_RES 80 ret void 81 } 82 83 declare <2 x i64> @llvm.mips.splat.d(<2 x i64>, i32) nounwind 84 85 ; MIPS32: llvm_mips_splat_d_test: 86 ; FIXME: This test is currently disabled for MIPS32 because the indices are 87 ; difficult to match. This is because 64-bit values cannot be stored in 88 ; GPR32. 89 ; MIPS64-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_splat_d_ARG1)( 90 ; MIPS64-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_splat_d_RES)( 91 ; MIPS64-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]]) 92 ; MIPS64-DAG: splat.d [[R4:\$w[0-9]+]], [[R3]][$4] 93 ; MIPS64-DAG: st.d [[R4]], 0([[R2]]) 94 ; MIPS32: .size llvm_mips_splat_d_test 95
