1 ; Test the MSA intrinsics that are encoded with the 3RF instruction format. 2 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 5 6 @llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 7 @llvm_mips_fadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 8 @llvm_mips_fadd_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 9 10 define void @llvm_mips_fadd_w_test() nounwind { 11 entry: 12 %0 = load <4 x float>* @llvm_mips_fadd_w_ARG1 13 %1 = load <4 x float>* @llvm_mips_fadd_w_ARG2 14 %2 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %1) 15 store <4 x float> %2, <4 x float>* @llvm_mips_fadd_w_RES 16 ret void 17 } 18 19 declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>) nounwind 20 21 ; CHECK: llvm_mips_fadd_w_test: 22 ; CHECK: ld.w 23 ; CHECK: ld.w 24 ; CHECK: fadd.w 25 ; CHECK: st.w 26 ; CHECK: .size llvm_mips_fadd_w_test 27 ; 28 @llvm_mips_fadd_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 29 @llvm_mips_fadd_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 30 @llvm_mips_fadd_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 31 32 define void @llvm_mips_fadd_d_test() nounwind { 33 entry: 34 %0 = load <2 x double>* @llvm_mips_fadd_d_ARG1 35 %1 = load <2 x double>* @llvm_mips_fadd_d_ARG2 36 %2 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %1) 37 store <2 x double> %2, <2 x double>* @llvm_mips_fadd_d_RES 38 ret void 39 } 40 41 declare <2 x double> @llvm.mips.fadd.d(<2 x double>, <2 x double>) nounwind 42 43 ; CHECK: llvm_mips_fadd_d_test: 44 ; CHECK: ld.d 45 ; CHECK: ld.d 46 ; CHECK: fadd.d 47 ; CHECK: st.d 48 ; CHECK: .size llvm_mips_fadd_d_test 49 50 define void @fadd_w_test() nounwind { 51 entry: 52 %0 = load <4 x float>* @llvm_mips_fadd_w_ARG1 53 %1 = load <4 x float>* @llvm_mips_fadd_w_ARG2 54 %2 = fadd <4 x float> %0, %1 55 store <4 x float> %2, <4 x float>* @llvm_mips_fadd_w_RES 56 ret void 57 } 58 59 ; CHECK: fadd_w_test: 60 ; CHECK: ld.w 61 ; CHECK: ld.w 62 ; CHECK: fadd.w 63 ; CHECK: st.w 64 ; CHECK: .size fadd_w_test 65 66 define void @fadd_d_test() nounwind { 67 entry: 68 %0 = load <2 x double>* @llvm_mips_fadd_d_ARG1 69 %1 = load <2 x double>* @llvm_mips_fadd_d_ARG2 70 %2 = fadd <2 x double> %0, %1 71 store <2 x double> %2, <2 x double>* @llvm_mips_fadd_d_RES 72 ret void 73 } 74 75 ; CHECK: fadd_d_test: 76 ; CHECK: ld.d 77 ; CHECK: ld.d 78 ; CHECK: fadd.d 79 ; CHECK: st.d 80 ; CHECK: .size fadd_d_test 81 ; 82 @llvm_mips_fdiv_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 83 @llvm_mips_fdiv_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 84 @llvm_mips_fdiv_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 85 86 define void @llvm_mips_fdiv_w_test() nounwind { 87 entry: 88 %0 = load <4 x float>* @llvm_mips_fdiv_w_ARG1 89 %1 = load <4 x float>* @llvm_mips_fdiv_w_ARG2 90 %2 = tail call <4 x float> @llvm.mips.fdiv.w(<4 x float> %0, <4 x float> %1) 91 store <4 x float> %2, <4 x float>* @llvm_mips_fdiv_w_RES 92 ret void 93 } 94 95 declare <4 x float> @llvm.mips.fdiv.w(<4 x float>, <4 x float>) nounwind 96 97 ; CHECK: llvm_mips_fdiv_w_test: 98 ; CHECK: ld.w 99 ; CHECK: ld.w 100 ; CHECK: fdiv.w 101 ; CHECK: st.w 102 ; CHECK: .size llvm_mips_fdiv_w_test 103 ; 104 @llvm_mips_fdiv_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 105 @llvm_mips_fdiv_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 106 @llvm_mips_fdiv_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 107 108 define void @llvm_mips_fdiv_d_test() nounwind { 109 entry: 110 %0 = load <2 x double>* @llvm_mips_fdiv_d_ARG1 111 %1 = load <2 x double>* @llvm_mips_fdiv_d_ARG2 112 %2 = tail call <2 x double> @llvm.mips.fdiv.d(<2 x double> %0, <2 x double> %1) 113 store <2 x double> %2, <2 x double>* @llvm_mips_fdiv_d_RES 114 ret void 115 } 116 117 declare <2 x double> @llvm.mips.fdiv.d(<2 x double>, <2 x double>) nounwind 118 119 ; CHECK: llvm_mips_fdiv_d_test: 120 ; CHECK: ld.d 121 ; CHECK: ld.d 122 ; CHECK: fdiv.d 123 ; CHECK: st.d 124 ; CHECK: .size llvm_mips_fdiv_d_test 125 126 define void @fdiv_w_test() nounwind { 127 entry: 128 %0 = load <4 x float>* @llvm_mips_fdiv_w_ARG1 129 %1 = load <4 x float>* @llvm_mips_fdiv_w_ARG2 130 %2 = fdiv <4 x float> %0, %1 131 store <4 x float> %2, <4 x float>* @llvm_mips_fdiv_w_RES 132 ret void 133 } 134 135 ; CHECK: fdiv_w_test: 136 ; CHECK: ld.w 137 ; CHECK: ld.w 138 ; CHECK: fdiv.w 139 ; CHECK: st.w 140 ; CHECK: .size fdiv_w_test 141 142 define void @fdiv_d_test() nounwind { 143 entry: 144 %0 = load <2 x double>* @llvm_mips_fdiv_d_ARG1 145 %1 = load <2 x double>* @llvm_mips_fdiv_d_ARG2 146 %2 = fdiv <2 x double> %0, %1 147 store <2 x double> %2, <2 x double>* @llvm_mips_fdiv_d_RES 148 ret void 149 } 150 151 ; CHECK: fdiv_d_test: 152 ; CHECK: ld.d 153 ; CHECK: ld.d 154 ; CHECK: fdiv.d 155 ; CHECK: st.d 156 ; CHECK: .size fdiv_d_test 157 ; 158 @llvm_mips_fmin_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 159 @llvm_mips_fmin_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 160 @llvm_mips_fmin_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 161 162 define void @llvm_mips_fmin_w_test() nounwind { 163 entry: 164 %0 = load <4 x float>* @llvm_mips_fmin_w_ARG1 165 %1 = load <4 x float>* @llvm_mips_fmin_w_ARG2 166 %2 = tail call <4 x float> @llvm.mips.fmin.w(<4 x float> %0, <4 x float> %1) 167 store <4 x float> %2, <4 x float>* @llvm_mips_fmin_w_RES 168 ret void 169 } 170 171 declare <4 x float> @llvm.mips.fmin.w(<4 x float>, <4 x float>) nounwind 172 173 ; CHECK: llvm_mips_fmin_w_test: 174 ; CHECK: ld.w 175 ; CHECK: ld.w 176 ; CHECK: fmin.w 177 ; CHECK: st.w 178 ; CHECK: .size llvm_mips_fmin_w_test 179 ; 180 @llvm_mips_fmin_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 181 @llvm_mips_fmin_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 182 @llvm_mips_fmin_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 183 184 define void @llvm_mips_fmin_d_test() nounwind { 185 entry: 186 %0 = load <2 x double>* @llvm_mips_fmin_d_ARG1 187 %1 = load <2 x double>* @llvm_mips_fmin_d_ARG2 188 %2 = tail call <2 x double> @llvm.mips.fmin.d(<2 x double> %0, <2 x double> %1) 189 store <2 x double> %2, <2 x double>* @llvm_mips_fmin_d_RES 190 ret void 191 } 192 193 declare <2 x double> @llvm.mips.fmin.d(<2 x double>, <2 x double>) nounwind 194 195 ; CHECK: llvm_mips_fmin_d_test: 196 ; CHECK: ld.d 197 ; CHECK: ld.d 198 ; CHECK: fmin.d 199 ; CHECK: st.d 200 ; CHECK: .size llvm_mips_fmin_d_test 201 ; 202 @llvm_mips_fmin_a_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 203 @llvm_mips_fmin_a_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 204 @llvm_mips_fmin_a_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 205 206 define void @llvm_mips_fmin_a_w_test() nounwind { 207 entry: 208 %0 = load <4 x float>* @llvm_mips_fmin_a_w_ARG1 209 %1 = load <4 x float>* @llvm_mips_fmin_a_w_ARG2 210 %2 = tail call <4 x float> @llvm.mips.fmin.a.w(<4 x float> %0, <4 x float> %1) 211 store <4 x float> %2, <4 x float>* @llvm_mips_fmin_a_w_RES 212 ret void 213 } 214 215 declare <4 x float> @llvm.mips.fmin.a.w(<4 x float>, <4 x float>) nounwind 216 217 ; CHECK: llvm_mips_fmin_a_w_test: 218 ; CHECK: ld.w 219 ; CHECK: ld.w 220 ; CHECK: fmin_a.w 221 ; CHECK: st.w 222 ; CHECK: .size llvm_mips_fmin_a_w_test 223 ; 224 @llvm_mips_fmin_a_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 225 @llvm_mips_fmin_a_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 226 @llvm_mips_fmin_a_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 227 228 define void @llvm_mips_fmin_a_d_test() nounwind { 229 entry: 230 %0 = load <2 x double>* @llvm_mips_fmin_a_d_ARG1 231 %1 = load <2 x double>* @llvm_mips_fmin_a_d_ARG2 232 %2 = tail call <2 x double> @llvm.mips.fmin.a.d(<2 x double> %0, <2 x double> %1) 233 store <2 x double> %2, <2 x double>* @llvm_mips_fmin_a_d_RES 234 ret void 235 } 236 237 declare <2 x double> @llvm.mips.fmin.a.d(<2 x double>, <2 x double>) nounwind 238 239 ; CHECK: llvm_mips_fmin_a_d_test: 240 ; CHECK: ld.d 241 ; CHECK: ld.d 242 ; CHECK: fmin_a.d 243 ; CHECK: st.d 244 ; CHECK: .size llvm_mips_fmin_a_d_test 245 ; 246 @llvm_mips_fmax_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 247 @llvm_mips_fmax_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 248 @llvm_mips_fmax_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 249 250 define void @llvm_mips_fmax_w_test() nounwind { 251 entry: 252 %0 = load <4 x float>* @llvm_mips_fmax_w_ARG1 253 %1 = load <4 x float>* @llvm_mips_fmax_w_ARG2 254 %2 = tail call <4 x float> @llvm.mips.fmax.w(<4 x float> %0, <4 x float> %1) 255 store <4 x float> %2, <4 x float>* @llvm_mips_fmax_w_RES 256 ret void 257 } 258 259 declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind 260 261 ; CHECK: llvm_mips_fmax_w_test: 262 ; CHECK: ld.w 263 ; CHECK: ld.w 264 ; CHECK: fmax.w 265 ; CHECK: st.w 266 ; CHECK: .size llvm_mips_fmax_w_test 267 ; 268 @llvm_mips_fmax_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 269 @llvm_mips_fmax_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 270 @llvm_mips_fmax_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 271 272 define void @llvm_mips_fmax_d_test() nounwind { 273 entry: 274 %0 = load <2 x double>* @llvm_mips_fmax_d_ARG1 275 %1 = load <2 x double>* @llvm_mips_fmax_d_ARG2 276 %2 = tail call <2 x double> @llvm.mips.fmax.d(<2 x double> %0, <2 x double> %1) 277 store <2 x double> %2, <2 x double>* @llvm_mips_fmax_d_RES 278 ret void 279 } 280 281 declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind 282 283 ; CHECK: llvm_mips_fmax_d_test: 284 ; CHECK: ld.d 285 ; CHECK: ld.d 286 ; CHECK: fmax.d 287 ; CHECK: st.d 288 ; CHECK: .size llvm_mips_fmax_d_test 289 ; 290 @llvm_mips_fmax_a_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 291 @llvm_mips_fmax_a_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 292 @llvm_mips_fmax_a_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 293 294 define void @llvm_mips_fmax_a_w_test() nounwind { 295 entry: 296 %0 = load <4 x float>* @llvm_mips_fmax_a_w_ARG1 297 %1 = load <4 x float>* @llvm_mips_fmax_a_w_ARG2 298 %2 = tail call <4 x float> @llvm.mips.fmax.a.w(<4 x float> %0, <4 x float> %1) 299 store <4 x float> %2, <4 x float>* @llvm_mips_fmax_a_w_RES 300 ret void 301 } 302 303 declare <4 x float> @llvm.mips.fmax.a.w(<4 x float>, <4 x float>) nounwind 304 305 ; CHECK: llvm_mips_fmax_a_w_test: 306 ; CHECK: ld.w 307 ; CHECK: ld.w 308 ; CHECK: fmax_a.w 309 ; CHECK: st.w 310 ; CHECK: .size llvm_mips_fmax_a_w_test 311 ; 312 @llvm_mips_fmax_a_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 313 @llvm_mips_fmax_a_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 314 @llvm_mips_fmax_a_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 315 316 define void @llvm_mips_fmax_a_d_test() nounwind { 317 entry: 318 %0 = load <2 x double>* @llvm_mips_fmax_a_d_ARG1 319 %1 = load <2 x double>* @llvm_mips_fmax_a_d_ARG2 320 %2 = tail call <2 x double> @llvm.mips.fmax.a.d(<2 x double> %0, <2 x double> %1) 321 store <2 x double> %2, <2 x double>* @llvm_mips_fmax_a_d_RES 322 ret void 323 } 324 325 declare <2 x double> @llvm.mips.fmax.a.d(<2 x double>, <2 x double>) nounwind 326 327 ; CHECK: llvm_mips_fmax_a_d_test: 328 ; CHECK: ld.d 329 ; CHECK: ld.d 330 ; CHECK: fmax_a.d 331 ; CHECK: st.d 332 ; CHECK: .size llvm_mips_fmax_a_d_test 333 ; 334 @llvm_mips_fmul_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 335 @llvm_mips_fmul_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 336 @llvm_mips_fmul_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 337 338 define void @llvm_mips_fmul_w_test() nounwind { 339 entry: 340 %0 = load <4 x float>* @llvm_mips_fmul_w_ARG1 341 %1 = load <4 x float>* @llvm_mips_fmul_w_ARG2 342 %2 = tail call <4 x float> @llvm.mips.fmul.w(<4 x float> %0, <4 x float> %1) 343 store <4 x float> %2, <4 x float>* @llvm_mips_fmul_w_RES 344 ret void 345 } 346 347 declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>) nounwind 348 349 ; CHECK: llvm_mips_fmul_w_test: 350 ; CHECK: ld.w 351 ; CHECK: ld.w 352 ; CHECK: fmul.w 353 ; CHECK: st.w 354 ; CHECK: .size llvm_mips_fmul_w_test 355 ; 356 @llvm_mips_fmul_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 357 @llvm_mips_fmul_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 358 @llvm_mips_fmul_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 359 360 define void @llvm_mips_fmul_d_test() nounwind { 361 entry: 362 %0 = load <2 x double>* @llvm_mips_fmul_d_ARG1 363 %1 = load <2 x double>* @llvm_mips_fmul_d_ARG2 364 %2 = tail call <2 x double> @llvm.mips.fmul.d(<2 x double> %0, <2 x double> %1) 365 store <2 x double> %2, <2 x double>* @llvm_mips_fmul_d_RES 366 ret void 367 } 368 369 declare <2 x double> @llvm.mips.fmul.d(<2 x double>, <2 x double>) nounwind 370 371 ; CHECK: llvm_mips_fmul_d_test: 372 ; CHECK: ld.d 373 ; CHECK: ld.d 374 ; CHECK: fmul.d 375 ; CHECK: st.d 376 ; CHECK: .size llvm_mips_fmul_d_test 377 378 define void @fmul_w_test() nounwind { 379 entry: 380 %0 = load <4 x float>* @llvm_mips_fmul_w_ARG1 381 %1 = load <4 x float>* @llvm_mips_fmul_w_ARG2 382 %2 = fmul <4 x float> %0, %1 383 store <4 x float> %2, <4 x float>* @llvm_mips_fmul_w_RES 384 ret void 385 } 386 387 ; CHECK: fmul_w_test: 388 ; CHECK: ld.w 389 ; CHECK: ld.w 390 ; CHECK: fmul.w 391 ; CHECK: st.w 392 ; CHECK: .size fmul_w_test 393 394 define void @fmul_d_test() nounwind { 395 entry: 396 %0 = load <2 x double>* @llvm_mips_fmul_d_ARG1 397 %1 = load <2 x double>* @llvm_mips_fmul_d_ARG2 398 %2 = fmul <2 x double> %0, %1 399 store <2 x double> %2, <2 x double>* @llvm_mips_fmul_d_RES 400 ret void 401 } 402 403 ; CHECK: fmul_d_test: 404 ; CHECK: ld.d 405 ; CHECK: ld.d 406 ; CHECK: fmul.d 407 ; CHECK: st.d 408 ; CHECK: .size fmul_d_test 409 ; 410 @llvm_mips_fsub_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 411 @llvm_mips_fsub_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 412 @llvm_mips_fsub_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 413 414 define void @llvm_mips_fsub_w_test() nounwind { 415 entry: 416 %0 = load <4 x float>* @llvm_mips_fsub_w_ARG1 417 %1 = load <4 x float>* @llvm_mips_fsub_w_ARG2 418 %2 = tail call <4 x float> @llvm.mips.fsub.w(<4 x float> %0, <4 x float> %1) 419 store <4 x float> %2, <4 x float>* @llvm_mips_fsub_w_RES 420 ret void 421 } 422 423 declare <4 x float> @llvm.mips.fsub.w(<4 x float>, <4 x float>) nounwind 424 425 ; CHECK: llvm_mips_fsub_w_test: 426 ; CHECK: ld.w 427 ; CHECK: ld.w 428 ; CHECK: fsub.w 429 ; CHECK: st.w 430 ; CHECK: .size llvm_mips_fsub_w_test 431 ; 432 @llvm_mips_fsub_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 433 @llvm_mips_fsub_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 434 @llvm_mips_fsub_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 435 436 define void @llvm_mips_fsub_d_test() nounwind { 437 entry: 438 %0 = load <2 x double>* @llvm_mips_fsub_d_ARG1 439 %1 = load <2 x double>* @llvm_mips_fsub_d_ARG2 440 %2 = tail call <2 x double> @llvm.mips.fsub.d(<2 x double> %0, <2 x double> %1) 441 store <2 x double> %2, <2 x double>* @llvm_mips_fsub_d_RES 442 ret void 443 } 444 445 declare <2 x double> @llvm.mips.fsub.d(<2 x double>, <2 x double>) nounwind 446 447 ; CHECK: llvm_mips_fsub_d_test: 448 ; CHECK: ld.d 449 ; CHECK: ld.d 450 ; CHECK: fsub.d 451 ; CHECK: st.d 452 ; CHECK: .size llvm_mips_fsub_d_test 453 ; 454 455 define void @fsub_w_test() nounwind { 456 entry: 457 %0 = load <4 x float>* @llvm_mips_fsub_w_ARG1 458 %1 = load <4 x float>* @llvm_mips_fsub_w_ARG2 459 %2 = fsub <4 x float> %0, %1 460 store <4 x float> %2, <4 x float>* @llvm_mips_fsub_w_RES 461 ret void 462 } 463 464 ; CHECK: fsub_w_test: 465 ; CHECK: ld.w 466 ; CHECK: ld.w 467 ; CHECK: fsub.w 468 ; CHECK: st.w 469 ; CHECK: .size fsub_w_test 470 471 define void @fsub_d_test() nounwind { 472 entry: 473 %0 = load <2 x double>* @llvm_mips_fsub_d_ARG1 474 %1 = load <2 x double>* @llvm_mips_fsub_d_ARG2 475 %2 = fsub <2 x double> %0, %1 476 store <2 x double> %2, <2 x double>* @llvm_mips_fsub_d_RES 477 ret void 478 } 479 480 ; CHECK: fsub_d_test: 481 ; CHECK: ld.d 482 ; CHECK: ld.d 483 ; CHECK: fsub.d 484 ; CHECK: st.d 485 ; CHECK: .size fsub_d_test 486
