1 ; Test the MSA intrinsics that are encoded with the 3RF instruction format and 2 ; use the result as a third operand. 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7 @llvm_mips_fmadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 8 @llvm_mips_fmadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 9 @llvm_mips_fmadd_w_ARG3 = global <4 x float> <float 8.000000e+00, float 9.000000e+00, float 1.000000e+01, float 1.100000e+01>, align 16 10 @llvm_mips_fmadd_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 11 12 define void @llvm_mips_fmadd_w_test() nounwind { 13 entry: 14 %0 = load <4 x float>* @llvm_mips_fmadd_w_ARG1 15 %1 = load <4 x float>* @llvm_mips_fmadd_w_ARG2 16 %2 = load <4 x float>* @llvm_mips_fmadd_w_ARG3 17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2) 18 store <4 x float> %3, <4 x float>* @llvm_mips_fmadd_w_RES 19 ret void 20 } 21 22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind 23 24 ; CHECK: llvm_mips_fmadd_w_test: 25 ; CHECK: ld.w 26 ; CHECK: ld.w 27 ; CHECK: ld.w 28 ; CHECK: fmadd.w 29 ; CHECK: st.w 30 ; CHECK: .size llvm_mips_fmadd_w_test 31 ; 32 @llvm_mips_fmadd_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 33 @llvm_mips_fmadd_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 34 @llvm_mips_fmadd_d_ARG3 = global <2 x double> <double 4.000000e+00, double 5.000000e+00>, align 16 35 @llvm_mips_fmadd_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 36 37 define void @llvm_mips_fmadd_d_test() nounwind { 38 entry: 39 %0 = load <2 x double>* @llvm_mips_fmadd_d_ARG1 40 %1 = load <2 x double>* @llvm_mips_fmadd_d_ARG2 41 %2 = load <2 x double>* @llvm_mips_fmadd_d_ARG3 42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2) 43 store <2 x double> %3, <2 x double>* @llvm_mips_fmadd_d_RES 44 ret void 45 } 46 47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind 48 49 ; CHECK: llvm_mips_fmadd_d_test: 50 ; CHECK: ld.d 51 ; CHECK: ld.d 52 ; CHECK: ld.d 53 ; CHECK: fmadd.d 54 ; CHECK: st.d 55 ; CHECK: .size llvm_mips_fmadd_d_test 56 ; 57 @llvm_mips_fmsub_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 58 @llvm_mips_fmsub_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 59 @llvm_mips_fmsub_w_ARG3 = global <4 x float> <float 8.000000e+00, float 9.000000e+00, float 1.000000e+01, float 1.100000e+01>, align 16 60 @llvm_mips_fmsub_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 61 62 define void @llvm_mips_fmsub_w_test() nounwind { 63 entry: 64 %0 = load <4 x float>* @llvm_mips_fmsub_w_ARG1 65 %1 = load <4 x float>* @llvm_mips_fmsub_w_ARG2 66 %2 = load <4 x float>* @llvm_mips_fmsub_w_ARG3 67 %3 = tail call <4 x float> @llvm.mips.fmsub.w(<4 x float> %0, <4 x float> %1, <4 x float> %2) 68 store <4 x float> %3, <4 x float>* @llvm_mips_fmsub_w_RES 69 ret void 70 } 71 72 declare <4 x float> @llvm.mips.fmsub.w(<4 x float>, <4 x float>, <4 x float>) nounwind 73 74 ; CHECK: llvm_mips_fmsub_w_test: 75 ; CHECK: ld.w 76 ; CHECK: ld.w 77 ; CHECK: ld.w 78 ; CHECK: fmsub.w 79 ; CHECK: st.w 80 ; CHECK: .size llvm_mips_fmsub_w_test 81 ; 82 @llvm_mips_fmsub_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 83 @llvm_mips_fmsub_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 84 @llvm_mips_fmsub_d_ARG3 = global <2 x double> <double 4.000000e+00, double 5.000000e+00>, align 16 85 @llvm_mips_fmsub_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 86 87 define void @llvm_mips_fmsub_d_test() nounwind { 88 entry: 89 %0 = load <2 x double>* @llvm_mips_fmsub_d_ARG1 90 %1 = load <2 x double>* @llvm_mips_fmsub_d_ARG2 91 %2 = load <2 x double>* @llvm_mips_fmsub_d_ARG3 92 %3 = tail call <2 x double> @llvm.mips.fmsub.d(<2 x double> %0, <2 x double> %1, <2 x double> %2) 93 store <2 x double> %3, <2 x double>* @llvm_mips_fmsub_d_RES 94 ret void 95 } 96 97 declare <2 x double> @llvm.mips.fmsub.d(<2 x double>, <2 x double>, <2 x double>) nounwind 98 99 ; CHECK: llvm_mips_fmsub_d_test: 100 ; CHECK: ld.d 101 ; CHECK: ld.d 102 ; CHECK: ld.d 103 ; CHECK: fmsub.d 104 ; CHECK: st.d 105 ; CHECK: .size llvm_mips_fmsub_d_test 106 ; 107
