1 ; Test the MSA intrinsics that are encoded with the 3RF instruction format and 2 ; produce an integer as a result. 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7 @llvm_mips_fcaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 8 @llvm_mips_fcaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 9 @llvm_mips_fcaf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 10 11 define void @llvm_mips_fcaf_w_test() nounwind { 12 entry: 13 %0 = load <4 x float>* @llvm_mips_fcaf_w_ARG1 14 %1 = load <4 x float>* @llvm_mips_fcaf_w_ARG2 15 %2 = tail call <4 x i32> @llvm.mips.fcaf.w(<4 x float> %0, <4 x float> %1) 16 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcaf_w_RES 17 ret void 18 } 19 20 declare <4 x i32> @llvm.mips.fcaf.w(<4 x float>, <4 x float>) nounwind 21 22 ; CHECK: llvm_mips_fcaf_w_test: 23 ; CHECK: ld.w 24 ; CHECK: ld.w 25 ; CHECK: fcaf.w 26 ; CHECK: st.w 27 ; CHECK: .size llvm_mips_fcaf_w_test 28 ; 29 @llvm_mips_fcaf_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 30 @llvm_mips_fcaf_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 31 @llvm_mips_fcaf_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 32 33 define void @llvm_mips_fcaf_d_test() nounwind { 34 entry: 35 %0 = load <2 x double>* @llvm_mips_fcaf_d_ARG1 36 %1 = load <2 x double>* @llvm_mips_fcaf_d_ARG2 37 %2 = tail call <2 x i64> @llvm.mips.fcaf.d(<2 x double> %0, <2 x double> %1) 38 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcaf_d_RES 39 ret void 40 } 41 42 declare <2 x i64> @llvm.mips.fcaf.d(<2 x double>, <2 x double>) nounwind 43 44 ; CHECK: llvm_mips_fcaf_d_test: 45 ; CHECK: ld.d 46 ; CHECK: ld.d 47 ; CHECK: fcaf.d 48 ; CHECK: st.d 49 ; CHECK: .size llvm_mips_fcaf_d_test 50 ; 51 @llvm_mips_fceq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 52 @llvm_mips_fceq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 53 @llvm_mips_fceq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 54 55 define void @llvm_mips_fceq_w_test() nounwind { 56 entry: 57 %0 = load <4 x float>* @llvm_mips_fceq_w_ARG1 58 %1 = load <4 x float>* @llvm_mips_fceq_w_ARG2 59 %2 = tail call <4 x i32> @llvm.mips.fceq.w(<4 x float> %0, <4 x float> %1) 60 store <4 x i32> %2, <4 x i32>* @llvm_mips_fceq_w_RES 61 ret void 62 } 63 64 declare <4 x i32> @llvm.mips.fceq.w(<4 x float>, <4 x float>) nounwind 65 66 ; CHECK: llvm_mips_fceq_w_test: 67 ; CHECK: ld.w 68 ; CHECK: ld.w 69 ; CHECK: fceq.w 70 ; CHECK: st.w 71 ; CHECK: .size llvm_mips_fceq_w_test 72 ; 73 @llvm_mips_fceq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 74 @llvm_mips_fceq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 75 @llvm_mips_fceq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 76 77 define void @llvm_mips_fceq_d_test() nounwind { 78 entry: 79 %0 = load <2 x double>* @llvm_mips_fceq_d_ARG1 80 %1 = load <2 x double>* @llvm_mips_fceq_d_ARG2 81 %2 = tail call <2 x i64> @llvm.mips.fceq.d(<2 x double> %0, <2 x double> %1) 82 store <2 x i64> %2, <2 x i64>* @llvm_mips_fceq_d_RES 83 ret void 84 } 85 86 declare <2 x i64> @llvm.mips.fceq.d(<2 x double>, <2 x double>) nounwind 87 88 ; CHECK: llvm_mips_fceq_d_test: 89 ; CHECK: ld.d 90 ; CHECK: ld.d 91 ; CHECK: fceq.d 92 ; CHECK: st.d 93 ; CHECK: .size llvm_mips_fceq_d_test 94 ; 95 @llvm_mips_fcle_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 96 @llvm_mips_fcle_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 97 @llvm_mips_fcle_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 98 99 define void @llvm_mips_fcle_w_test() nounwind { 100 entry: 101 %0 = load <4 x float>* @llvm_mips_fcle_w_ARG1 102 %1 = load <4 x float>* @llvm_mips_fcle_w_ARG2 103 %2 = tail call <4 x i32> @llvm.mips.fcle.w(<4 x float> %0, <4 x float> %1) 104 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcle_w_RES 105 ret void 106 } 107 108 declare <4 x i32> @llvm.mips.fcle.w(<4 x float>, <4 x float>) nounwind 109 110 ; CHECK: llvm_mips_fcle_w_test: 111 ; CHECK: ld.w 112 ; CHECK: ld.w 113 ; CHECK: fcle.w 114 ; CHECK: st.w 115 ; CHECK: .size llvm_mips_fcle_w_test 116 ; 117 @llvm_mips_fcle_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 118 @llvm_mips_fcle_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 119 @llvm_mips_fcle_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 120 121 define void @llvm_mips_fcle_d_test() nounwind { 122 entry: 123 %0 = load <2 x double>* @llvm_mips_fcle_d_ARG1 124 %1 = load <2 x double>* @llvm_mips_fcle_d_ARG2 125 %2 = tail call <2 x i64> @llvm.mips.fcle.d(<2 x double> %0, <2 x double> %1) 126 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcle_d_RES 127 ret void 128 } 129 130 declare <2 x i64> @llvm.mips.fcle.d(<2 x double>, <2 x double>) nounwind 131 132 ; CHECK: llvm_mips_fcle_d_test: 133 ; CHECK: ld.d 134 ; CHECK: ld.d 135 ; CHECK: fcle.d 136 ; CHECK: st.d 137 ; CHECK: .size llvm_mips_fcle_d_test 138 ; 139 @llvm_mips_fclt_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 140 @llvm_mips_fclt_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 141 @llvm_mips_fclt_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 142 143 define void @llvm_mips_fclt_w_test() nounwind { 144 entry: 145 %0 = load <4 x float>* @llvm_mips_fclt_w_ARG1 146 %1 = load <4 x float>* @llvm_mips_fclt_w_ARG2 147 %2 = tail call <4 x i32> @llvm.mips.fclt.w(<4 x float> %0, <4 x float> %1) 148 store <4 x i32> %2, <4 x i32>* @llvm_mips_fclt_w_RES 149 ret void 150 } 151 152 declare <4 x i32> @llvm.mips.fclt.w(<4 x float>, <4 x float>) nounwind 153 154 ; CHECK: llvm_mips_fclt_w_test: 155 ; CHECK: ld.w 156 ; CHECK: ld.w 157 ; CHECK: fclt.w 158 ; CHECK: st.w 159 ; CHECK: .size llvm_mips_fclt_w_test 160 ; 161 @llvm_mips_fclt_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 162 @llvm_mips_fclt_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 163 @llvm_mips_fclt_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 164 165 define void @llvm_mips_fclt_d_test() nounwind { 166 entry: 167 %0 = load <2 x double>* @llvm_mips_fclt_d_ARG1 168 %1 = load <2 x double>* @llvm_mips_fclt_d_ARG2 169 %2 = tail call <2 x i64> @llvm.mips.fclt.d(<2 x double> %0, <2 x double> %1) 170 store <2 x i64> %2, <2 x i64>* @llvm_mips_fclt_d_RES 171 ret void 172 } 173 174 declare <2 x i64> @llvm.mips.fclt.d(<2 x double>, <2 x double>) nounwind 175 176 ; CHECK: llvm_mips_fclt_d_test: 177 ; CHECK: ld.d 178 ; CHECK: ld.d 179 ; CHECK: fclt.d 180 ; CHECK: st.d 181 ; CHECK: .size llvm_mips_fclt_d_test 182 ; 183 @llvm_mips_fcor_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 184 @llvm_mips_fcor_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 185 @llvm_mips_fcor_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 186 187 define void @llvm_mips_fcor_w_test() nounwind { 188 entry: 189 %0 = load <4 x float>* @llvm_mips_fcor_w_ARG1 190 %1 = load <4 x float>* @llvm_mips_fcor_w_ARG2 191 %2 = tail call <4 x i32> @llvm.mips.fcor.w(<4 x float> %0, <4 x float> %1) 192 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcor_w_RES 193 ret void 194 } 195 196 declare <4 x i32> @llvm.mips.fcor.w(<4 x float>, <4 x float>) nounwind 197 198 ; CHECK: llvm_mips_fcor_w_test: 199 ; CHECK: ld.w 200 ; CHECK: ld.w 201 ; CHECK: fcor.w 202 ; CHECK: st.w 203 ; CHECK: .size llvm_mips_fcor_w_test 204 ; 205 @llvm_mips_fcor_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 206 @llvm_mips_fcor_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 207 @llvm_mips_fcor_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 208 209 define void @llvm_mips_fcor_d_test() nounwind { 210 entry: 211 %0 = load <2 x double>* @llvm_mips_fcor_d_ARG1 212 %1 = load <2 x double>* @llvm_mips_fcor_d_ARG2 213 %2 = tail call <2 x i64> @llvm.mips.fcor.d(<2 x double> %0, <2 x double> %1) 214 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcor_d_RES 215 ret void 216 } 217 218 declare <2 x i64> @llvm.mips.fcor.d(<2 x double>, <2 x double>) nounwind 219 220 ; CHECK: llvm_mips_fcor_d_test: 221 ; CHECK: ld.d 222 ; CHECK: ld.d 223 ; CHECK: fcor.d 224 ; CHECK: st.d 225 ; CHECK: .size llvm_mips_fcor_d_test 226 ; 227 @llvm_mips_fcne_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 228 @llvm_mips_fcne_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 229 @llvm_mips_fcne_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 230 231 define void @llvm_mips_fcne_w_test() nounwind { 232 entry: 233 %0 = load <4 x float>* @llvm_mips_fcne_w_ARG1 234 %1 = load <4 x float>* @llvm_mips_fcne_w_ARG2 235 %2 = tail call <4 x i32> @llvm.mips.fcne.w(<4 x float> %0, <4 x float> %1) 236 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcne_w_RES 237 ret void 238 } 239 240 declare <4 x i32> @llvm.mips.fcne.w(<4 x float>, <4 x float>) nounwind 241 242 ; CHECK: llvm_mips_fcne_w_test: 243 ; CHECK: ld.w 244 ; CHECK: ld.w 245 ; CHECK: fcne.w 246 ; CHECK: st.w 247 ; CHECK: .size llvm_mips_fcne_w_test 248 ; 249 @llvm_mips_fcne_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 250 @llvm_mips_fcne_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 251 @llvm_mips_fcne_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 252 253 define void @llvm_mips_fcne_d_test() nounwind { 254 entry: 255 %0 = load <2 x double>* @llvm_mips_fcne_d_ARG1 256 %1 = load <2 x double>* @llvm_mips_fcne_d_ARG2 257 %2 = tail call <2 x i64> @llvm.mips.fcne.d(<2 x double> %0, <2 x double> %1) 258 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcne_d_RES 259 ret void 260 } 261 262 declare <2 x i64> @llvm.mips.fcne.d(<2 x double>, <2 x double>) nounwind 263 264 ; CHECK: llvm_mips_fcne_d_test: 265 ; CHECK: ld.d 266 ; CHECK: ld.d 267 ; CHECK: fcne.d 268 ; CHECK: st.d 269 ; CHECK: .size llvm_mips_fcne_d_test 270 ; 271 @llvm_mips_fcueq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 272 @llvm_mips_fcueq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 273 @llvm_mips_fcueq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 274 275 define void @llvm_mips_fcueq_w_test() nounwind { 276 entry: 277 %0 = load <4 x float>* @llvm_mips_fcueq_w_ARG1 278 %1 = load <4 x float>* @llvm_mips_fcueq_w_ARG2 279 %2 = tail call <4 x i32> @llvm.mips.fcueq.w(<4 x float> %0, <4 x float> %1) 280 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcueq_w_RES 281 ret void 282 } 283 284 declare <4 x i32> @llvm.mips.fcueq.w(<4 x float>, <4 x float>) nounwind 285 286 ; CHECK: llvm_mips_fcueq_w_test: 287 ; CHECK: ld.w 288 ; CHECK: ld.w 289 ; CHECK: fcueq.w 290 ; CHECK: st.w 291 ; CHECK: .size llvm_mips_fcueq_w_test 292 ; 293 @llvm_mips_fcueq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 294 @llvm_mips_fcueq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 295 @llvm_mips_fcueq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 296 297 define void @llvm_mips_fcueq_d_test() nounwind { 298 entry: 299 %0 = load <2 x double>* @llvm_mips_fcueq_d_ARG1 300 %1 = load <2 x double>* @llvm_mips_fcueq_d_ARG2 301 %2 = tail call <2 x i64> @llvm.mips.fcueq.d(<2 x double> %0, <2 x double> %1) 302 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcueq_d_RES 303 ret void 304 } 305 306 declare <2 x i64> @llvm.mips.fcueq.d(<2 x double>, <2 x double>) nounwind 307 308 ; CHECK: llvm_mips_fcueq_d_test: 309 ; CHECK: ld.d 310 ; CHECK: ld.d 311 ; CHECK: fcueq.d 312 ; CHECK: st.d 313 ; CHECK: .size llvm_mips_fcueq_d_test 314 ; 315 @llvm_mips_fcult_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 316 @llvm_mips_fcult_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 317 @llvm_mips_fcult_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 318 319 define void @llvm_mips_fcult_w_test() nounwind { 320 entry: 321 %0 = load <4 x float>* @llvm_mips_fcult_w_ARG1 322 %1 = load <4 x float>* @llvm_mips_fcult_w_ARG2 323 %2 = tail call <4 x i32> @llvm.mips.fcult.w(<4 x float> %0, <4 x float> %1) 324 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcult_w_RES 325 ret void 326 } 327 328 declare <4 x i32> @llvm.mips.fcult.w(<4 x float>, <4 x float>) nounwind 329 330 ; CHECK: llvm_mips_fcult_w_test: 331 ; CHECK: ld.w 332 ; CHECK: ld.w 333 ; CHECK: fcult.w 334 ; CHECK: st.w 335 ; CHECK: .size llvm_mips_fcult_w_test 336 ; 337 @llvm_mips_fcult_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 338 @llvm_mips_fcult_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 339 @llvm_mips_fcult_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 340 341 define void @llvm_mips_fcult_d_test() nounwind { 342 entry: 343 %0 = load <2 x double>* @llvm_mips_fcult_d_ARG1 344 %1 = load <2 x double>* @llvm_mips_fcult_d_ARG2 345 %2 = tail call <2 x i64> @llvm.mips.fcult.d(<2 x double> %0, <2 x double> %1) 346 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcult_d_RES 347 ret void 348 } 349 350 declare <2 x i64> @llvm.mips.fcult.d(<2 x double>, <2 x double>) nounwind 351 352 ; CHECK: llvm_mips_fcult_d_test: 353 ; CHECK: ld.d 354 ; CHECK: ld.d 355 ; CHECK: fcult.d 356 ; CHECK: st.d 357 ; CHECK: .size llvm_mips_fcult_d_test 358 ; 359 @llvm_mips_fcule_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 360 @llvm_mips_fcule_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 361 @llvm_mips_fcule_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 362 363 define void @llvm_mips_fcule_w_test() nounwind { 364 entry: 365 %0 = load <4 x float>* @llvm_mips_fcule_w_ARG1 366 %1 = load <4 x float>* @llvm_mips_fcule_w_ARG2 367 %2 = tail call <4 x i32> @llvm.mips.fcule.w(<4 x float> %0, <4 x float> %1) 368 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcule_w_RES 369 ret void 370 } 371 372 declare <4 x i32> @llvm.mips.fcule.w(<4 x float>, <4 x float>) nounwind 373 374 ; CHECK: llvm_mips_fcule_w_test: 375 ; CHECK: ld.w 376 ; CHECK: ld.w 377 ; CHECK: fcule.w 378 ; CHECK: st.w 379 ; CHECK: .size llvm_mips_fcule_w_test 380 ; 381 @llvm_mips_fcule_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 382 @llvm_mips_fcule_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 383 @llvm_mips_fcule_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 384 385 define void @llvm_mips_fcule_d_test() nounwind { 386 entry: 387 %0 = load <2 x double>* @llvm_mips_fcule_d_ARG1 388 %1 = load <2 x double>* @llvm_mips_fcule_d_ARG2 389 %2 = tail call <2 x i64> @llvm.mips.fcule.d(<2 x double> %0, <2 x double> %1) 390 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcule_d_RES 391 ret void 392 } 393 394 declare <2 x i64> @llvm.mips.fcule.d(<2 x double>, <2 x double>) nounwind 395 396 ; CHECK: llvm_mips_fcule_d_test: 397 ; CHECK: ld.d 398 ; CHECK: ld.d 399 ; CHECK: fcule.d 400 ; CHECK: st.d 401 ; CHECK: .size llvm_mips_fcule_d_test 402 ; 403 @llvm_mips_fcun_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 404 @llvm_mips_fcun_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 405 @llvm_mips_fcun_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 406 407 define void @llvm_mips_fcun_w_test() nounwind { 408 entry: 409 %0 = load <4 x float>* @llvm_mips_fcun_w_ARG1 410 %1 = load <4 x float>* @llvm_mips_fcun_w_ARG2 411 %2 = tail call <4 x i32> @llvm.mips.fcun.w(<4 x float> %0, <4 x float> %1) 412 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcun_w_RES 413 ret void 414 } 415 416 declare <4 x i32> @llvm.mips.fcun.w(<4 x float>, <4 x float>) nounwind 417 418 ; CHECK: llvm_mips_fcun_w_test: 419 ; CHECK: ld.w 420 ; CHECK: ld.w 421 ; CHECK: fcun.w 422 ; CHECK: st.w 423 ; CHECK: .size llvm_mips_fcun_w_test 424 ; 425 @llvm_mips_fcun_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 426 @llvm_mips_fcun_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 427 @llvm_mips_fcun_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 428 429 define void @llvm_mips_fcun_d_test() nounwind { 430 entry: 431 %0 = load <2 x double>* @llvm_mips_fcun_d_ARG1 432 %1 = load <2 x double>* @llvm_mips_fcun_d_ARG2 433 %2 = tail call <2 x i64> @llvm.mips.fcun.d(<2 x double> %0, <2 x double> %1) 434 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcun_d_RES 435 ret void 436 } 437 438 declare <2 x i64> @llvm.mips.fcun.d(<2 x double>, <2 x double>) nounwind 439 440 ; CHECK: llvm_mips_fcun_d_test: 441 ; CHECK: ld.d 442 ; CHECK: ld.d 443 ; CHECK: fcun.d 444 ; CHECK: st.d 445 ; CHECK: .size llvm_mips_fcun_d_test 446 ; 447 @llvm_mips_fcune_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 448 @llvm_mips_fcune_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 449 @llvm_mips_fcune_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 450 451 define void @llvm_mips_fcune_w_test() nounwind { 452 entry: 453 %0 = load <4 x float>* @llvm_mips_fcune_w_ARG1 454 %1 = load <4 x float>* @llvm_mips_fcune_w_ARG2 455 %2 = tail call <4 x i32> @llvm.mips.fcune.w(<4 x float> %0, <4 x float> %1) 456 store <4 x i32> %2, <4 x i32>* @llvm_mips_fcune_w_RES 457 ret void 458 } 459 460 declare <4 x i32> @llvm.mips.fcune.w(<4 x float>, <4 x float>) nounwind 461 462 ; CHECK: llvm_mips_fcune_w_test: 463 ; CHECK: ld.w 464 ; CHECK: ld.w 465 ; CHECK: fcune.w 466 ; CHECK: st.w 467 ; CHECK: .size llvm_mips_fcune_w_test 468 ; 469 @llvm_mips_fcune_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 470 @llvm_mips_fcune_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 471 @llvm_mips_fcune_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 472 473 define void @llvm_mips_fcune_d_test() nounwind { 474 entry: 475 %0 = load <2 x double>* @llvm_mips_fcune_d_ARG1 476 %1 = load <2 x double>* @llvm_mips_fcune_d_ARG2 477 %2 = tail call <2 x i64> @llvm.mips.fcune.d(<2 x double> %0, <2 x double> %1) 478 store <2 x i64> %2, <2 x i64>* @llvm_mips_fcune_d_RES 479 ret void 480 } 481 482 declare <2 x i64> @llvm.mips.fcune.d(<2 x double>, <2 x double>) nounwind 483 484 ; CHECK: llvm_mips_fcune_d_test: 485 ; CHECK: ld.d 486 ; CHECK: ld.d 487 ; CHECK: fcune.d 488 ; CHECK: st.d 489 ; CHECK: .size llvm_mips_fcune_d_test 490 ; 491 @llvm_mips_fsaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 492 @llvm_mips_fsaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 493 @llvm_mips_fsaf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 494 495 define void @llvm_mips_fsaf_w_test() nounwind { 496 entry: 497 %0 = load <4 x float>* @llvm_mips_fsaf_w_ARG1 498 %1 = load <4 x float>* @llvm_mips_fsaf_w_ARG2 499 %2 = tail call <4 x i32> @llvm.mips.fsaf.w(<4 x float> %0, <4 x float> %1) 500 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsaf_w_RES 501 ret void 502 } 503 504 declare <4 x i32> @llvm.mips.fsaf.w(<4 x float>, <4 x float>) nounwind 505 506 ; CHECK: llvm_mips_fsaf_w_test: 507 ; CHECK: ld.w 508 ; CHECK: ld.w 509 ; CHECK: fsaf.w 510 ; CHECK: st.w 511 ; CHECK: .size llvm_mips_fsaf_w_test 512 ; 513 @llvm_mips_fsaf_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 514 @llvm_mips_fsaf_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 515 @llvm_mips_fsaf_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 516 517 define void @llvm_mips_fsaf_d_test() nounwind { 518 entry: 519 %0 = load <2 x double>* @llvm_mips_fsaf_d_ARG1 520 %1 = load <2 x double>* @llvm_mips_fsaf_d_ARG2 521 %2 = tail call <2 x i64> @llvm.mips.fsaf.d(<2 x double> %0, <2 x double> %1) 522 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsaf_d_RES 523 ret void 524 } 525 526 declare <2 x i64> @llvm.mips.fsaf.d(<2 x double>, <2 x double>) nounwind 527 528 ; CHECK: llvm_mips_fsaf_d_test: 529 ; CHECK: ld.d 530 ; CHECK: ld.d 531 ; CHECK: fsaf.d 532 ; CHECK: st.d 533 ; CHECK: .size llvm_mips_fsaf_d_test 534 ; 535 @llvm_mips_fseq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 536 @llvm_mips_fseq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 537 @llvm_mips_fseq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 538 539 define void @llvm_mips_fseq_w_test() nounwind { 540 entry: 541 %0 = load <4 x float>* @llvm_mips_fseq_w_ARG1 542 %1 = load <4 x float>* @llvm_mips_fseq_w_ARG2 543 %2 = tail call <4 x i32> @llvm.mips.fseq.w(<4 x float> %0, <4 x float> %1) 544 store <4 x i32> %2, <4 x i32>* @llvm_mips_fseq_w_RES 545 ret void 546 } 547 548 declare <4 x i32> @llvm.mips.fseq.w(<4 x float>, <4 x float>) nounwind 549 550 ; CHECK: llvm_mips_fseq_w_test: 551 ; CHECK: ld.w 552 ; CHECK: ld.w 553 ; CHECK: fseq.w 554 ; CHECK: st.w 555 ; CHECK: .size llvm_mips_fseq_w_test 556 ; 557 @llvm_mips_fseq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 558 @llvm_mips_fseq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 559 @llvm_mips_fseq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 560 561 define void @llvm_mips_fseq_d_test() nounwind { 562 entry: 563 %0 = load <2 x double>* @llvm_mips_fseq_d_ARG1 564 %1 = load <2 x double>* @llvm_mips_fseq_d_ARG2 565 %2 = tail call <2 x i64> @llvm.mips.fseq.d(<2 x double> %0, <2 x double> %1) 566 store <2 x i64> %2, <2 x i64>* @llvm_mips_fseq_d_RES 567 ret void 568 } 569 570 declare <2 x i64> @llvm.mips.fseq.d(<2 x double>, <2 x double>) nounwind 571 572 ; CHECK: llvm_mips_fseq_d_test: 573 ; CHECK: ld.d 574 ; CHECK: ld.d 575 ; CHECK: fseq.d 576 ; CHECK: st.d 577 ; CHECK: .size llvm_mips_fseq_d_test 578 ; 579 @llvm_mips_fsle_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 580 @llvm_mips_fsle_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 581 @llvm_mips_fsle_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 582 583 define void @llvm_mips_fsle_w_test() nounwind { 584 entry: 585 %0 = load <4 x float>* @llvm_mips_fsle_w_ARG1 586 %1 = load <4 x float>* @llvm_mips_fsle_w_ARG2 587 %2 = tail call <4 x i32> @llvm.mips.fsle.w(<4 x float> %0, <4 x float> %1) 588 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsle_w_RES 589 ret void 590 } 591 592 declare <4 x i32> @llvm.mips.fsle.w(<4 x float>, <4 x float>) nounwind 593 594 ; CHECK: llvm_mips_fsle_w_test: 595 ; CHECK: ld.w 596 ; CHECK: ld.w 597 ; CHECK: fsle.w 598 ; CHECK: st.w 599 ; CHECK: .size llvm_mips_fsle_w_test 600 ; 601 @llvm_mips_fsle_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 602 @llvm_mips_fsle_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 603 @llvm_mips_fsle_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 604 605 define void @llvm_mips_fsle_d_test() nounwind { 606 entry: 607 %0 = load <2 x double>* @llvm_mips_fsle_d_ARG1 608 %1 = load <2 x double>* @llvm_mips_fsle_d_ARG2 609 %2 = tail call <2 x i64> @llvm.mips.fsle.d(<2 x double> %0, <2 x double> %1) 610 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsle_d_RES 611 ret void 612 } 613 614 declare <2 x i64> @llvm.mips.fsle.d(<2 x double>, <2 x double>) nounwind 615 616 ; CHECK: llvm_mips_fsle_d_test: 617 ; CHECK: ld.d 618 ; CHECK: ld.d 619 ; CHECK: fsle.d 620 ; CHECK: st.d 621 ; CHECK: .size llvm_mips_fsle_d_test 622 ; 623 @llvm_mips_fslt_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 624 @llvm_mips_fslt_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 625 @llvm_mips_fslt_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 626 627 define void @llvm_mips_fslt_w_test() nounwind { 628 entry: 629 %0 = load <4 x float>* @llvm_mips_fslt_w_ARG1 630 %1 = load <4 x float>* @llvm_mips_fslt_w_ARG2 631 %2 = tail call <4 x i32> @llvm.mips.fslt.w(<4 x float> %0, <4 x float> %1) 632 store <4 x i32> %2, <4 x i32>* @llvm_mips_fslt_w_RES 633 ret void 634 } 635 636 declare <4 x i32> @llvm.mips.fslt.w(<4 x float>, <4 x float>) nounwind 637 638 ; CHECK: llvm_mips_fslt_w_test: 639 ; CHECK: ld.w 640 ; CHECK: ld.w 641 ; CHECK: fslt.w 642 ; CHECK: st.w 643 ; CHECK: .size llvm_mips_fslt_w_test 644 ; 645 @llvm_mips_fslt_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 646 @llvm_mips_fslt_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 647 @llvm_mips_fslt_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 648 649 define void @llvm_mips_fslt_d_test() nounwind { 650 entry: 651 %0 = load <2 x double>* @llvm_mips_fslt_d_ARG1 652 %1 = load <2 x double>* @llvm_mips_fslt_d_ARG2 653 %2 = tail call <2 x i64> @llvm.mips.fslt.d(<2 x double> %0, <2 x double> %1) 654 store <2 x i64> %2, <2 x i64>* @llvm_mips_fslt_d_RES 655 ret void 656 } 657 658 declare <2 x i64> @llvm.mips.fslt.d(<2 x double>, <2 x double>) nounwind 659 660 ; CHECK: llvm_mips_fslt_d_test: 661 ; CHECK: ld.d 662 ; CHECK: ld.d 663 ; CHECK: fslt.d 664 ; CHECK: st.d 665 ; CHECK: .size llvm_mips_fslt_d_test 666 ; 667 @llvm_mips_fsor_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 668 @llvm_mips_fsor_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 669 @llvm_mips_fsor_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 670 671 define void @llvm_mips_fsor_w_test() nounwind { 672 entry: 673 %0 = load <4 x float>* @llvm_mips_fsor_w_ARG1 674 %1 = load <4 x float>* @llvm_mips_fsor_w_ARG2 675 %2 = tail call <4 x i32> @llvm.mips.fsor.w(<4 x float> %0, <4 x float> %1) 676 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsor_w_RES 677 ret void 678 } 679 680 declare <4 x i32> @llvm.mips.fsor.w(<4 x float>, <4 x float>) nounwind 681 682 ; CHECK: llvm_mips_fsor_w_test: 683 ; CHECK: ld.w 684 ; CHECK: ld.w 685 ; CHECK: fsor.w 686 ; CHECK: st.w 687 ; CHECK: .size llvm_mips_fsor_w_test 688 ; 689 @llvm_mips_fsor_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 690 @llvm_mips_fsor_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 691 @llvm_mips_fsor_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 692 693 define void @llvm_mips_fsor_d_test() nounwind { 694 entry: 695 %0 = load <2 x double>* @llvm_mips_fsor_d_ARG1 696 %1 = load <2 x double>* @llvm_mips_fsor_d_ARG2 697 %2 = tail call <2 x i64> @llvm.mips.fsor.d(<2 x double> %0, <2 x double> %1) 698 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsor_d_RES 699 ret void 700 } 701 702 declare <2 x i64> @llvm.mips.fsor.d(<2 x double>, <2 x double>) nounwind 703 704 ; CHECK: llvm_mips_fsor_d_test: 705 ; CHECK: ld.d 706 ; CHECK: ld.d 707 ; CHECK: fsor.d 708 ; CHECK: st.d 709 ; CHECK: .size llvm_mips_fsor_d_test 710 ; 711 @llvm_mips_fsne_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 712 @llvm_mips_fsne_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 713 @llvm_mips_fsne_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 714 715 define void @llvm_mips_fsne_w_test() nounwind { 716 entry: 717 %0 = load <4 x float>* @llvm_mips_fsne_w_ARG1 718 %1 = load <4 x float>* @llvm_mips_fsne_w_ARG2 719 %2 = tail call <4 x i32> @llvm.mips.fsne.w(<4 x float> %0, <4 x float> %1) 720 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsne_w_RES 721 ret void 722 } 723 724 declare <4 x i32> @llvm.mips.fsne.w(<4 x float>, <4 x float>) nounwind 725 726 ; CHECK: llvm_mips_fsne_w_test: 727 ; CHECK: ld.w 728 ; CHECK: ld.w 729 ; CHECK: fsne.w 730 ; CHECK: st.w 731 ; CHECK: .size llvm_mips_fsne_w_test 732 ; 733 @llvm_mips_fsne_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 734 @llvm_mips_fsne_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 735 @llvm_mips_fsne_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 736 737 define void @llvm_mips_fsne_d_test() nounwind { 738 entry: 739 %0 = load <2 x double>* @llvm_mips_fsne_d_ARG1 740 %1 = load <2 x double>* @llvm_mips_fsne_d_ARG2 741 %2 = tail call <2 x i64> @llvm.mips.fsne.d(<2 x double> %0, <2 x double> %1) 742 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsne_d_RES 743 ret void 744 } 745 746 declare <2 x i64> @llvm.mips.fsne.d(<2 x double>, <2 x double>) nounwind 747 748 ; CHECK: llvm_mips_fsne_d_test: 749 ; CHECK: ld.d 750 ; CHECK: ld.d 751 ; CHECK: fsne.d 752 ; CHECK: st.d 753 ; CHECK: .size llvm_mips_fsne_d_test 754 ; 755 @llvm_mips_fsueq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 756 @llvm_mips_fsueq_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 757 @llvm_mips_fsueq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 758 759 define void @llvm_mips_fsueq_w_test() nounwind { 760 entry: 761 %0 = load <4 x float>* @llvm_mips_fsueq_w_ARG1 762 %1 = load <4 x float>* @llvm_mips_fsueq_w_ARG2 763 %2 = tail call <4 x i32> @llvm.mips.fsueq.w(<4 x float> %0, <4 x float> %1) 764 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsueq_w_RES 765 ret void 766 } 767 768 declare <4 x i32> @llvm.mips.fsueq.w(<4 x float>, <4 x float>) nounwind 769 770 ; CHECK: llvm_mips_fsueq_w_test: 771 ; CHECK: ld.w 772 ; CHECK: ld.w 773 ; CHECK: fsueq.w 774 ; CHECK: st.w 775 ; CHECK: .size llvm_mips_fsueq_w_test 776 ; 777 @llvm_mips_fsueq_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 778 @llvm_mips_fsueq_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 779 @llvm_mips_fsueq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 780 781 define void @llvm_mips_fsueq_d_test() nounwind { 782 entry: 783 %0 = load <2 x double>* @llvm_mips_fsueq_d_ARG1 784 %1 = load <2 x double>* @llvm_mips_fsueq_d_ARG2 785 %2 = tail call <2 x i64> @llvm.mips.fsueq.d(<2 x double> %0, <2 x double> %1) 786 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsueq_d_RES 787 ret void 788 } 789 790 declare <2 x i64> @llvm.mips.fsueq.d(<2 x double>, <2 x double>) nounwind 791 792 ; CHECK: llvm_mips_fsueq_d_test: 793 ; CHECK: ld.d 794 ; CHECK: ld.d 795 ; CHECK: fsueq.d 796 ; CHECK: st.d 797 ; CHECK: .size llvm_mips_fsueq_d_test 798 ; 799 @llvm_mips_fsult_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 800 @llvm_mips_fsult_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 801 @llvm_mips_fsult_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 802 803 define void @llvm_mips_fsult_w_test() nounwind { 804 entry: 805 %0 = load <4 x float>* @llvm_mips_fsult_w_ARG1 806 %1 = load <4 x float>* @llvm_mips_fsult_w_ARG2 807 %2 = tail call <4 x i32> @llvm.mips.fsult.w(<4 x float> %0, <4 x float> %1) 808 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsult_w_RES 809 ret void 810 } 811 812 declare <4 x i32> @llvm.mips.fsult.w(<4 x float>, <4 x float>) nounwind 813 814 ; CHECK: llvm_mips_fsult_w_test: 815 ; CHECK: ld.w 816 ; CHECK: ld.w 817 ; CHECK: fsult.w 818 ; CHECK: st.w 819 ; CHECK: .size llvm_mips_fsult_w_test 820 ; 821 @llvm_mips_fsult_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 822 @llvm_mips_fsult_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 823 @llvm_mips_fsult_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 824 825 define void @llvm_mips_fsult_d_test() nounwind { 826 entry: 827 %0 = load <2 x double>* @llvm_mips_fsult_d_ARG1 828 %1 = load <2 x double>* @llvm_mips_fsult_d_ARG2 829 %2 = tail call <2 x i64> @llvm.mips.fsult.d(<2 x double> %0, <2 x double> %1) 830 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsult_d_RES 831 ret void 832 } 833 834 declare <2 x i64> @llvm.mips.fsult.d(<2 x double>, <2 x double>) nounwind 835 836 ; CHECK: llvm_mips_fsult_d_test: 837 ; CHECK: ld.d 838 ; CHECK: ld.d 839 ; CHECK: fsult.d 840 ; CHECK: st.d 841 ; CHECK: .size llvm_mips_fsult_d_test 842 ; 843 @llvm_mips_fsule_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 844 @llvm_mips_fsule_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 845 @llvm_mips_fsule_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 846 847 define void @llvm_mips_fsule_w_test() nounwind { 848 entry: 849 %0 = load <4 x float>* @llvm_mips_fsule_w_ARG1 850 %1 = load <4 x float>* @llvm_mips_fsule_w_ARG2 851 %2 = tail call <4 x i32> @llvm.mips.fsule.w(<4 x float> %0, <4 x float> %1) 852 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsule_w_RES 853 ret void 854 } 855 856 declare <4 x i32> @llvm.mips.fsule.w(<4 x float>, <4 x float>) nounwind 857 858 ; CHECK: llvm_mips_fsule_w_test: 859 ; CHECK: ld.w 860 ; CHECK: ld.w 861 ; CHECK: fsule.w 862 ; CHECK: st.w 863 ; CHECK: .size llvm_mips_fsule_w_test 864 ; 865 @llvm_mips_fsule_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 866 @llvm_mips_fsule_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 867 @llvm_mips_fsule_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 868 869 define void @llvm_mips_fsule_d_test() nounwind { 870 entry: 871 %0 = load <2 x double>* @llvm_mips_fsule_d_ARG1 872 %1 = load <2 x double>* @llvm_mips_fsule_d_ARG2 873 %2 = tail call <2 x i64> @llvm.mips.fsule.d(<2 x double> %0, <2 x double> %1) 874 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsule_d_RES 875 ret void 876 } 877 878 declare <2 x i64> @llvm.mips.fsule.d(<2 x double>, <2 x double>) nounwind 879 880 ; CHECK: llvm_mips_fsule_d_test: 881 ; CHECK: ld.d 882 ; CHECK: ld.d 883 ; CHECK: fsule.d 884 ; CHECK: st.d 885 ; CHECK: .size llvm_mips_fsule_d_test 886 ; 887 @llvm_mips_fsun_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 888 @llvm_mips_fsun_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 889 @llvm_mips_fsun_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 890 891 define void @llvm_mips_fsun_w_test() nounwind { 892 entry: 893 %0 = load <4 x float>* @llvm_mips_fsun_w_ARG1 894 %1 = load <4 x float>* @llvm_mips_fsun_w_ARG2 895 %2 = tail call <4 x i32> @llvm.mips.fsun.w(<4 x float> %0, <4 x float> %1) 896 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsun_w_RES 897 ret void 898 } 899 900 declare <4 x i32> @llvm.mips.fsun.w(<4 x float>, <4 x float>) nounwind 901 902 ; CHECK: llvm_mips_fsun_w_test: 903 ; CHECK: ld.w 904 ; CHECK: ld.w 905 ; CHECK: fsun.w 906 ; CHECK: st.w 907 ; CHECK: .size llvm_mips_fsun_w_test 908 ; 909 @llvm_mips_fsun_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 910 @llvm_mips_fsun_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 911 @llvm_mips_fsun_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 912 913 define void @llvm_mips_fsun_d_test() nounwind { 914 entry: 915 %0 = load <2 x double>* @llvm_mips_fsun_d_ARG1 916 %1 = load <2 x double>* @llvm_mips_fsun_d_ARG2 917 %2 = tail call <2 x i64> @llvm.mips.fsun.d(<2 x double> %0, <2 x double> %1) 918 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsun_d_RES 919 ret void 920 } 921 922 declare <2 x i64> @llvm.mips.fsun.d(<2 x double>, <2 x double>) nounwind 923 924 ; CHECK: llvm_mips_fsun_d_test: 925 ; CHECK: ld.d 926 ; CHECK: ld.d 927 ; CHECK: fsun.d 928 ; CHECK: st.d 929 ; CHECK: .size llvm_mips_fsun_d_test 930 ; 931 @llvm_mips_fsune_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 932 @llvm_mips_fsune_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 933 @llvm_mips_fsune_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 934 935 define void @llvm_mips_fsune_w_test() nounwind { 936 entry: 937 %0 = load <4 x float>* @llvm_mips_fsune_w_ARG1 938 %1 = load <4 x float>* @llvm_mips_fsune_w_ARG2 939 %2 = tail call <4 x i32> @llvm.mips.fsune.w(<4 x float> %0, <4 x float> %1) 940 store <4 x i32> %2, <4 x i32>* @llvm_mips_fsune_w_RES 941 ret void 942 } 943 944 declare <4 x i32> @llvm.mips.fsune.w(<4 x float>, <4 x float>) nounwind 945 946 ; CHECK: llvm_mips_fsune_w_test: 947 ; CHECK: ld.w 948 ; CHECK: ld.w 949 ; CHECK: fsune.w 950 ; CHECK: st.w 951 ; CHECK: .size llvm_mips_fsune_w_test 952 ; 953 @llvm_mips_fsune_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 954 @llvm_mips_fsune_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16 955 @llvm_mips_fsune_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 956 957 define void @llvm_mips_fsune_d_test() nounwind { 958 entry: 959 %0 = load <2 x double>* @llvm_mips_fsune_d_ARG1 960 %1 = load <2 x double>* @llvm_mips_fsune_d_ARG2 961 %2 = tail call <2 x i64> @llvm.mips.fsune.d(<2 x double> %0, <2 x double> %1) 962 store <2 x i64> %2, <2 x i64>* @llvm_mips_fsune_d_RES 963 ret void 964 } 965 966 declare <2 x i64> @llvm.mips.fsune.d(<2 x double>, <2 x double>) nounwind 967 968 ; CHECK: llvm_mips_fsune_d_test: 969 ; CHECK: ld.d 970 ; CHECK: ld.d 971 ; CHECK: fsune.d 972 ; CHECK: st.d 973 ; CHECK: .size llvm_mips_fsune_d_test 974 ; 975
