1 ; Test the MSA intrinsics that are encoded with the ELM instruction format and 2 ; are element extraction operations. 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ 5 ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ 7 ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 8 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ 9 ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 10 ; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ 11 ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 12 13 @llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 14 @llvm_mips_copy_s_b_RES = global i32 0, align 16 15 16 define void @llvm_mips_copy_s_b_test() nounwind { 17 entry: 18 %0 = load <16 x i8>* @llvm_mips_copy_s_b_ARG1 19 %1 = tail call i32 @llvm.mips.copy.s.b(<16 x i8> %0, i32 1) 20 store i32 %1, i32* @llvm_mips_copy_s_b_RES 21 ret void 22 } 23 24 declare i32 @llvm.mips.copy.s.b(<16 x i8>, i32) nounwind 25 26 ; MIPS-ANY: llvm_mips_copy_s_b_test: 27 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_b_ARG1) 28 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_ARG1) 29 ; MIPS-ANY-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 30 ; MIPS-ANY-DAG: copy_s.b [[RD:\$[0-9]+]], [[WS]][1] 31 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_b_RES) 32 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_RES) 33 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 34 ; MIPS-ANY: .size llvm_mips_copy_s_b_test 35 ; 36 @llvm_mips_copy_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 37 @llvm_mips_copy_s_h_RES = global i32 0, align 16 38 39 define void @llvm_mips_copy_s_h_test() nounwind { 40 entry: 41 %0 = load <8 x i16>* @llvm_mips_copy_s_h_ARG1 42 %1 = tail call i32 @llvm.mips.copy.s.h(<8 x i16> %0, i32 1) 43 store i32 %1, i32* @llvm_mips_copy_s_h_RES 44 ret void 45 } 46 47 declare i32 @llvm.mips.copy.s.h(<8 x i16>, i32) nounwind 48 49 ; MIPS-ANY: llvm_mips_copy_s_h_test: 50 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_h_ARG1) 51 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_ARG1) 52 ; MIPS-ANY-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 53 ; MIPS-ANY-DAG: copy_s.h [[RD:\$[0-9]+]], [[WS]][1] 54 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_h_RES) 55 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_RES) 56 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 57 ; MIPS-ANY: .size llvm_mips_copy_s_h_test 58 ; 59 @llvm_mips_copy_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 60 @llvm_mips_copy_s_w_RES = global i32 0, align 16 61 62 define void @llvm_mips_copy_s_w_test() nounwind { 63 entry: 64 %0 = load <4 x i32>* @llvm_mips_copy_s_w_ARG1 65 %1 = tail call i32 @llvm.mips.copy.s.w(<4 x i32> %0, i32 1) 66 store i32 %1, i32* @llvm_mips_copy_s_w_RES 67 ret void 68 } 69 70 declare i32 @llvm.mips.copy.s.w(<4 x i32>, i32) nounwind 71 72 ; MIPS-ANY: llvm_mips_copy_s_w_test: 73 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_w_ARG1) 74 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_ARG1) 75 ; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 76 ; MIPS-ANY-DAG: copy_s.w [[RD:\$[0-9]+]], [[WS]][1] 77 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_w_RES) 78 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_RES) 79 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 80 ; MIPS-ANY: .size llvm_mips_copy_s_w_test 81 ; 82 @llvm_mips_copy_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 83 @llvm_mips_copy_s_d_RES = global i64 0, align 16 84 85 define void @llvm_mips_copy_s_d_test() nounwind { 86 entry: 87 %0 = load <2 x i64>* @llvm_mips_copy_s_d_ARG1 88 %1 = tail call i64 @llvm.mips.copy.s.d(<2 x i64> %0, i32 1) 89 store i64 %1, i64* @llvm_mips_copy_s_d_RES 90 ret void 91 } 92 93 declare i64 @llvm.mips.copy.s.d(<2 x i64>, i32) nounwind 94 95 ; MIPS-ANY: llvm_mips_copy_s_d_test: 96 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_d_ARG1) 97 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_d_ARG1) 98 ; MIPS32-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 99 ; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 100 ; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2] 101 ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3] 102 ; MIPS64-DAG: copy_s.d [[RD:\$[0-9]+]], [[WS]][1] 103 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_d_RES) 104 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_d_RES) 105 ; MIPS32-DAG: sw [[RD1]], 0([[RES]]) 106 ; MIPS32-DAG: sw [[RD2]], 4([[RES]]) 107 ; MIPS64-DAG: sd [[RD]], 0([[RES]]) 108 ; MIPS-ANY: .size llvm_mips_copy_s_d_test 109 ; 110 @llvm_mips_copy_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 111 @llvm_mips_copy_u_b_RES = global i32 0, align 16 112 113 define void @llvm_mips_copy_u_b_test() nounwind { 114 entry: 115 %0 = load <16 x i8>* @llvm_mips_copy_u_b_ARG1 116 %1 = tail call i32 @llvm.mips.copy.u.b(<16 x i8> %0, i32 1) 117 store i32 %1, i32* @llvm_mips_copy_u_b_RES 118 ret void 119 } 120 121 declare i32 @llvm.mips.copy.u.b(<16 x i8>, i32) nounwind 122 123 ; MIPS-ANY: llvm_mips_copy_u_b_test: 124 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_b_ARG1) 125 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_b_ARG1) 126 ; MIPS-ANY-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) 127 ; MIPS-ANY-DAG: copy_u.b [[RD:\$[0-9]+]], [[WS]][1] 128 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_b_RES) 129 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_b_RES) 130 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 131 ; MIPS-ANY: .size llvm_mips_copy_u_b_test 132 ; 133 @llvm_mips_copy_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 134 @llvm_mips_copy_u_h_RES = global i32 0, align 16 135 136 define void @llvm_mips_copy_u_h_test() nounwind { 137 entry: 138 %0 = load <8 x i16>* @llvm_mips_copy_u_h_ARG1 139 %1 = tail call i32 @llvm.mips.copy.u.h(<8 x i16> %0, i32 1) 140 store i32 %1, i32* @llvm_mips_copy_u_h_RES 141 ret void 142 } 143 144 declare i32 @llvm.mips.copy.u.h(<8 x i16>, i32) nounwind 145 146 ; MIPS-ANY: llvm_mips_copy_u_h_test: 147 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_h_ARG1) 148 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_h_ARG1) 149 ; MIPS-ANY-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) 150 ; MIPS-ANY-DAG: copy_u.h [[RD:\$[0-9]+]], [[WS]][1] 151 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_h_RES) 152 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_h_RES) 153 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 154 ; MIPS-ANY: .size llvm_mips_copy_u_h_test 155 ; 156 @llvm_mips_copy_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 157 @llvm_mips_copy_u_w_RES = global i32 0, align 16 158 159 define void @llvm_mips_copy_u_w_test() nounwind { 160 entry: 161 %0 = load <4 x i32>* @llvm_mips_copy_u_w_ARG1 162 %1 = tail call i32 @llvm.mips.copy.u.w(<4 x i32> %0, i32 1) 163 store i32 %1, i32* @llvm_mips_copy_u_w_RES 164 ret void 165 } 166 167 declare i32 @llvm.mips.copy.u.w(<4 x i32>, i32) nounwind 168 169 ; MIPS-ANY: llvm_mips_copy_u_w_test: 170 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_w_ARG1) 171 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_ARG1) 172 ; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 173 ; MIPS-ANY-DAG: copy_u.w [[RD:\$[0-9]+]], [[WS]][1] 174 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_w_RES) 175 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_RES) 176 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 177 ; MIPS-ANY: .size llvm_mips_copy_u_w_test 178 ; 179 @llvm_mips_copy_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 180 @llvm_mips_copy_u_d_RES = global i64 0, align 16 181 182 define void @llvm_mips_copy_u_d_test() nounwind { 183 entry: 184 %0 = load <2 x i64>* @llvm_mips_copy_u_d_ARG1 185 %1 = tail call i64 @llvm.mips.copy.u.d(<2 x i64> %0, i32 1) 186 store i64 %1, i64* @llvm_mips_copy_u_d_RES 187 ret void 188 } 189 190 declare i64 @llvm.mips.copy.u.d(<2 x i64>, i32) nounwind 191 192 ; MIPS-ANY: llvm_mips_copy_u_d_test: 193 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_d_ARG1) 194 ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_ARG1) 195 ; MIPS32-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) 196 ; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) 197 ; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2] 198 ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3] 199 ; MIPS64-DAG: copy_u.d [[RD:\$[0-9]+]], [[WS]][1] 200 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_d_RES) 201 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_RES) 202 ; MIPS32-DAG: sw [[RD1]], 0([[RES]]) 203 ; MIPS32-DAG: sw [[RD2]], 4([[RES]]) 204 ; MIPS64-DAG: sd [[RD]], 0([[RES]]) 205 ; MIPS-ANY: .size llvm_mips_copy_u_d_test 206 ; 207
