1 ; Test the MSA intrinsics that are encoded with the I5 instruction format. 2 ; There are lots of these so this covers those beginning with 'b' 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7 @llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8 @llvm_mips_bclri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 9 10 define void @llvm_mips_bclri_b_test() nounwind { 11 entry: 12 %0 = load <16 x i8>* @llvm_mips_bclri_b_ARG1 13 %1 = tail call <16 x i8> @llvm.mips.bclri.b(<16 x i8> %0, i32 7) 14 store <16 x i8> %1, <16 x i8>* @llvm_mips_bclri_b_RES 15 ret void 16 } 17 18 declare <16 x i8> @llvm.mips.bclri.b(<16 x i8>, i32) nounwind 19 20 ; CHECK: llvm_mips_bclri_b_test: 21 ; CHECK: ld.b 22 ; andi.b is equivalent to bclri.b 23 ; CHECK: andi.b {{\$w[0-9]}}, {{\$w[0-9]}}, 127 24 ; CHECK: st.b 25 ; CHECK: .size llvm_mips_bclri_b_test 26 ; 27 @llvm_mips_bclri_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 28 @llvm_mips_bclri_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 29 30 define void @llvm_mips_bclri_h_test() nounwind { 31 entry: 32 %0 = load <8 x i16>* @llvm_mips_bclri_h_ARG1 33 %1 = tail call <8 x i16> @llvm.mips.bclri.h(<8 x i16> %0, i32 7) 34 store <8 x i16> %1, <8 x i16>* @llvm_mips_bclri_h_RES 35 ret void 36 } 37 38 declare <8 x i16> @llvm.mips.bclri.h(<8 x i16>, i32) nounwind 39 40 ; CHECK: llvm_mips_bclri_h_test: 41 ; CHECK: ld.h 42 ; CHECK: bclri.h 43 ; CHECK: st.h 44 ; CHECK: .size llvm_mips_bclri_h_test 45 ; 46 @llvm_mips_bclri_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 47 @llvm_mips_bclri_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 48 49 define void @llvm_mips_bclri_w_test() nounwind { 50 entry: 51 %0 = load <4 x i32>* @llvm_mips_bclri_w_ARG1 52 %1 = tail call <4 x i32> @llvm.mips.bclri.w(<4 x i32> %0, i32 7) 53 store <4 x i32> %1, <4 x i32>* @llvm_mips_bclri_w_RES 54 ret void 55 } 56 57 declare <4 x i32> @llvm.mips.bclri.w(<4 x i32>, i32) nounwind 58 59 ; CHECK: llvm_mips_bclri_w_test: 60 ; CHECK: ld.w 61 ; CHECK: bclri.w 62 ; CHECK: st.w 63 ; CHECK: .size llvm_mips_bclri_w_test 64 ; 65 @llvm_mips_bclri_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 66 @llvm_mips_bclri_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 67 68 define void @llvm_mips_bclri_d_test() nounwind { 69 entry: 70 %0 = load <2 x i64>* @llvm_mips_bclri_d_ARG1 71 %1 = tail call <2 x i64> @llvm.mips.bclri.d(<2 x i64> %0, i32 7) 72 store <2 x i64> %1, <2 x i64>* @llvm_mips_bclri_d_RES 73 ret void 74 } 75 76 declare <2 x i64> @llvm.mips.bclri.d(<2 x i64>, i32) nounwind 77 78 ; CHECK: llvm_mips_bclri_d_test: 79 ; CHECK: ld.d 80 ; CHECK: bclri.d 81 ; CHECK: st.d 82 ; CHECK: .size llvm_mips_bclri_d_test 83 ; 84 @llvm_mips_binsli_b_ARG1 = global <16 x i8> zeroinitializer, align 16 85 @llvm_mips_binsli_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 86 @llvm_mips_binsli_b_RES = global <16 x i8> zeroinitializer, align 16 87 88 define void @llvm_mips_binsli_b_test() nounwind { 89 entry: 90 %0 = load <16 x i8>* @llvm_mips_binsli_b_ARG1 91 %1 = load <16 x i8>* @llvm_mips_binsli_b_ARG2 92 %2 = tail call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %0, <16 x i8> %1, i32 7) 93 store <16 x i8> %2, <16 x i8>* @llvm_mips_binsli_b_RES 94 ret void 95 } 96 97 declare <16 x i8> @llvm.mips.binsli.b(<16 x i8>, <16 x i8>, i32) nounwind 98 99 ; CHECK: llvm_mips_binsli_b_test: 100 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_b_ARG1)( 101 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_b_ARG2)( 102 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) 103 ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) 104 ; CHECK-DAG: binsli.b [[R3]], [[R4]], 7 105 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_b_RES)( 106 ; CHECK-DAG: st.b [[R3]], 0([[R5]]) 107 ; CHECK: .size llvm_mips_binsli_b_test 108 109 @llvm_mips_binsli_h_ARG1 = global <8 x i16> zeroinitializer, align 16 110 @llvm_mips_binsli_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 111 @llvm_mips_binsli_h_RES = global <8 x i16> zeroinitializer, align 16 112 113 define void @llvm_mips_binsli_h_test() nounwind { 114 entry: 115 %0 = load <8 x i16>* @llvm_mips_binsli_h_ARG1 116 %1 = load <8 x i16>* @llvm_mips_binsli_h_ARG2 117 %2 = tail call <8 x i16> @llvm.mips.binsli.h(<8 x i16> %0, <8 x i16> %1, i32 7) 118 store <8 x i16> %2, <8 x i16>* @llvm_mips_binsli_h_RES 119 ret void 120 } 121 122 declare <8 x i16> @llvm.mips.binsli.h(<8 x i16>, <8 x i16>, i32) nounwind 123 124 ; CHECK: llvm_mips_binsli_h_test: 125 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_h_ARG1)( 126 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_h_ARG2)( 127 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]]) 128 ; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]]) 129 ; CHECK-DAG: binsli.h [[R3]], [[R4]], 7 130 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_h_RES)( 131 ; CHECK-DAG: st.h [[R3]], 0([[R5]]) 132 ; CHECK: .size llvm_mips_binsli_h_test 133 134 @llvm_mips_binsli_w_ARG1 = global <4 x i32> zeroinitializer, align 16 135 @llvm_mips_binsli_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 136 @llvm_mips_binsli_w_RES = global <4 x i32> zeroinitializer, align 16 137 138 define void @llvm_mips_binsli_w_test() nounwind { 139 entry: 140 %0 = load <4 x i32>* @llvm_mips_binsli_w_ARG1 141 %1 = load <4 x i32>* @llvm_mips_binsli_w_ARG2 142 %2 = tail call <4 x i32> @llvm.mips.binsli.w(<4 x i32> %0, <4 x i32> %1, i32 7) 143 store <4 x i32> %2, <4 x i32>* @llvm_mips_binsli_w_RES 144 ret void 145 } 146 147 declare <4 x i32> @llvm.mips.binsli.w(<4 x i32>, <4 x i32>, i32) nounwind 148 149 ; CHECK: llvm_mips_binsli_w_test: 150 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_w_ARG1)( 151 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_w_ARG2)( 152 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]]) 153 ; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]]) 154 ; CHECK-DAG: binsli.w [[R3]], [[R4]], 7 155 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_w_RES)( 156 ; CHECK-DAG: st.w [[R3]], 0([[R5]]) 157 ; CHECK: .size llvm_mips_binsli_w_test 158 159 @llvm_mips_binsli_d_ARG1 = global <2 x i64> zeroinitializer, align 16 160 @llvm_mips_binsli_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16 161 @llvm_mips_binsli_d_RES = global <2 x i64> zeroinitializer, align 16 162 163 define void @llvm_mips_binsli_d_test() nounwind { 164 entry: 165 %0 = load <2 x i64>* @llvm_mips_binsli_d_ARG1 166 %1 = load <2 x i64>* @llvm_mips_binsli_d_ARG2 167 ; TODO: We use a particularly wide mask here to work around a legalization 168 ; issue. If the mask doesn't fit within a 10-bit immediate, it gets 169 ; legalized into a constant pool. We should add a test to cover the 170 ; other cases once they correctly select binsli.d. 171 %2 = tail call <2 x i64> @llvm.mips.binsli.d(<2 x i64> %0, <2 x i64> %1, i32 61) 172 store <2 x i64> %2, <2 x i64>* @llvm_mips_binsli_d_RES 173 ret void 174 } 175 176 declare <2 x i64> @llvm.mips.binsli.d(<2 x i64>, <2 x i64>, i32) nounwind 177 178 ; CHECK: llvm_mips_binsli_d_test: 179 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_d_ARG1)( 180 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_d_ARG2)( 181 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]]) 182 ; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]]) 183 ; CHECK-DAG: binsli.d [[R3]], [[R4]], 61 184 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_d_RES)( 185 ; CHECK-DAG: st.d [[R3]], 0([[R5]]) 186 ; CHECK: .size llvm_mips_binsli_d_test 187 188 @llvm_mips_binsri_b_ARG1 = global <16 x i8> zeroinitializer, align 16 189 @llvm_mips_binsri_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 190 @llvm_mips_binsri_b_RES = global <16 x i8> zeroinitializer, align 16 191 192 define void @llvm_mips_binsri_b_test() nounwind { 193 entry: 194 %0 = load <16 x i8>* @llvm_mips_binsri_b_ARG1 195 %1 = load <16 x i8>* @llvm_mips_binsri_b_ARG2 196 %2 = tail call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %0, <16 x i8> %1, i32 7) 197 store <16 x i8> %2, <16 x i8>* @llvm_mips_binsri_b_RES 198 ret void 199 } 200 201 declare <16 x i8> @llvm.mips.binsri.b(<16 x i8>, <16 x i8>, i32) nounwind 202 203 ; CHECK: llvm_mips_binsri_b_test: 204 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_b_ARG1)( 205 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_b_ARG2)( 206 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) 207 ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) 208 ; CHECK-DAG: binsri.b [[R3]], [[R4]], 7 209 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_b_RES)( 210 ; CHECK-DAG: st.b [[R3]], 0([[R5]]) 211 ; CHECK: .size llvm_mips_binsri_b_test 212 213 @llvm_mips_binsri_h_ARG1 = global <8 x i16> zeroinitializer, align 16 214 @llvm_mips_binsri_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 215 @llvm_mips_binsri_h_RES = global <8 x i16> zeroinitializer, align 16 216 217 define void @llvm_mips_binsri_h_test() nounwind { 218 entry: 219 %0 = load <8 x i16>* @llvm_mips_binsri_h_ARG1 220 %1 = load <8 x i16>* @llvm_mips_binsri_h_ARG2 221 %2 = tail call <8 x i16> @llvm.mips.binsri.h(<8 x i16> %0, <8 x i16> %1, i32 7) 222 store <8 x i16> %2, <8 x i16>* @llvm_mips_binsri_h_RES 223 ret void 224 } 225 226 declare <8 x i16> @llvm.mips.binsri.h(<8 x i16>, <8 x i16>, i32) nounwind 227 228 ; CHECK: llvm_mips_binsri_h_test: 229 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_h_ARG1)( 230 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_h_ARG2)( 231 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]]) 232 ; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]]) 233 ; CHECK-DAG: binsri.h [[R3]], [[R4]], 7 234 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_h_RES)( 235 ; CHECK-DAG: st.h [[R3]], 0([[R5]]) 236 ; CHECK: .size llvm_mips_binsri_h_test 237 238 @llvm_mips_binsri_w_ARG1 = global <4 x i32> zeroinitializer, align 16 239 @llvm_mips_binsri_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 240 @llvm_mips_binsri_w_RES = global <4 x i32> zeroinitializer, align 16 241 242 define void @llvm_mips_binsri_w_test() nounwind { 243 entry: 244 %0 = load <4 x i32>* @llvm_mips_binsri_w_ARG1 245 %1 = load <4 x i32>* @llvm_mips_binsri_w_ARG2 246 %2 = tail call <4 x i32> @llvm.mips.binsri.w(<4 x i32> %0, <4 x i32> %1, i32 7) 247 store <4 x i32> %2, <4 x i32>* @llvm_mips_binsri_w_RES 248 ret void 249 } 250 251 declare <4 x i32> @llvm.mips.binsri.w(<4 x i32>, <4 x i32>, i32) nounwind 252 253 ; CHECK: llvm_mips_binsri_w_test: 254 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_w_ARG1)( 255 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_w_ARG2)( 256 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]]) 257 ; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]]) 258 ; CHECK-DAG: binsri.w [[R3]], [[R4]], 7 259 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_w_RES)( 260 ; CHECK-DAG: st.w [[R3]], 0([[R5]]) 261 ; CHECK: .size llvm_mips_binsri_w_test 262 263 @llvm_mips_binsri_d_ARG1 = global <2 x i64> zeroinitializer, align 16 264 @llvm_mips_binsri_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16 265 @llvm_mips_binsri_d_RES = global <2 x i64> zeroinitializer, align 16 266 267 define void @llvm_mips_binsri_d_test() nounwind { 268 entry: 269 %0 = load <2 x i64>* @llvm_mips_binsri_d_ARG1 270 %1 = load <2 x i64>* @llvm_mips_binsri_d_ARG2 271 %2 = tail call <2 x i64> @llvm.mips.binsri.d(<2 x i64> %0, <2 x i64> %1, i32 7) 272 store <2 x i64> %2, <2 x i64>* @llvm_mips_binsri_d_RES 273 ret void 274 } 275 276 declare <2 x i64> @llvm.mips.binsri.d(<2 x i64>, <2 x i64>, i32) nounwind 277 278 ; CHECK: llvm_mips_binsri_d_test: 279 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_d_ARG1)( 280 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_d_ARG2)( 281 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]]) 282 ; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]]) 283 ; CHECK-DAG: binsri.d [[R3]], [[R4]], 7 284 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_d_RES)( 285 ; CHECK-DAG: st.d [[R3]], 0([[R5]]) 286 ; CHECK: .size llvm_mips_binsri_d_test 287 288 @llvm_mips_bnegi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 289 @llvm_mips_bnegi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 290 291 define void @llvm_mips_bnegi_b_test() nounwind { 292 entry: 293 %0 = load <16 x i8>* @llvm_mips_bnegi_b_ARG1 294 %1 = tail call <16 x i8> @llvm.mips.bnegi.b(<16 x i8> %0, i32 7) 295 store <16 x i8> %1, <16 x i8>* @llvm_mips_bnegi_b_RES 296 ret void 297 } 298 299 declare <16 x i8> @llvm.mips.bnegi.b(<16 x i8>, i32) nounwind 300 301 ; CHECK: llvm_mips_bnegi_b_test: 302 ; CHECK: ld.b 303 ; CHECK: bnegi.b 304 ; CHECK: st.b 305 ; CHECK: .size llvm_mips_bnegi_b_test 306 ; 307 @llvm_mips_bnegi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 308 @llvm_mips_bnegi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 309 310 define void @llvm_mips_bnegi_h_test() nounwind { 311 entry: 312 %0 = load <8 x i16>* @llvm_mips_bnegi_h_ARG1 313 %1 = tail call <8 x i16> @llvm.mips.bnegi.h(<8 x i16> %0, i32 7) 314 store <8 x i16> %1, <8 x i16>* @llvm_mips_bnegi_h_RES 315 ret void 316 } 317 318 declare <8 x i16> @llvm.mips.bnegi.h(<8 x i16>, i32) nounwind 319 320 ; CHECK: llvm_mips_bnegi_h_test: 321 ; CHECK: ld.h 322 ; CHECK: bnegi.h 323 ; CHECK: st.h 324 ; CHECK: .size llvm_mips_bnegi_h_test 325 ; 326 @llvm_mips_bnegi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 327 @llvm_mips_bnegi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 328 329 define void @llvm_mips_bnegi_w_test() nounwind { 330 entry: 331 %0 = load <4 x i32>* @llvm_mips_bnegi_w_ARG1 332 %1 = tail call <4 x i32> @llvm.mips.bnegi.w(<4 x i32> %0, i32 7) 333 store <4 x i32> %1, <4 x i32>* @llvm_mips_bnegi_w_RES 334 ret void 335 } 336 337 declare <4 x i32> @llvm.mips.bnegi.w(<4 x i32>, i32) nounwind 338 339 ; CHECK: llvm_mips_bnegi_w_test: 340 ; CHECK: ld.w 341 ; CHECK: bnegi.w 342 ; CHECK: st.w 343 ; CHECK: .size llvm_mips_bnegi_w_test 344 ; 345 @llvm_mips_bnegi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 346 @llvm_mips_bnegi_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 347 348 define void @llvm_mips_bnegi_d_test() nounwind { 349 entry: 350 %0 = load <2 x i64>* @llvm_mips_bnegi_d_ARG1 351 %1 = tail call <2 x i64> @llvm.mips.bnegi.d(<2 x i64> %0, i32 7) 352 store <2 x i64> %1, <2 x i64>* @llvm_mips_bnegi_d_RES 353 ret void 354 } 355 356 declare <2 x i64> @llvm.mips.bnegi.d(<2 x i64>, i32) nounwind 357 358 ; CHECK: llvm_mips_bnegi_d_test: 359 ; CHECK: ld.d 360 ; CHECK: bnegi.d 361 ; CHECK: st.d 362 ; CHECK: .size llvm_mips_bnegi_d_test 363 ; 364 @llvm_mips_bseti_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 365 @llvm_mips_bseti_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 366 367 define void @llvm_mips_bseti_b_test() nounwind { 368 entry: 369 %0 = load <16 x i8>* @llvm_mips_bseti_b_ARG1 370 %1 = tail call <16 x i8> @llvm.mips.bseti.b(<16 x i8> %0, i32 7) 371 store <16 x i8> %1, <16 x i8>* @llvm_mips_bseti_b_RES 372 ret void 373 } 374 375 declare <16 x i8> @llvm.mips.bseti.b(<16 x i8>, i32) nounwind 376 377 ; CHECK: llvm_mips_bseti_b_test: 378 ; CHECK: ld.b 379 ; CHECK: bseti.b 380 ; CHECK: st.b 381 ; CHECK: .size llvm_mips_bseti_b_test 382 ; 383 @llvm_mips_bseti_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 384 @llvm_mips_bseti_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 385 386 define void @llvm_mips_bseti_h_test() nounwind { 387 entry: 388 %0 = load <8 x i16>* @llvm_mips_bseti_h_ARG1 389 %1 = tail call <8 x i16> @llvm.mips.bseti.h(<8 x i16> %0, i32 7) 390 store <8 x i16> %1, <8 x i16>* @llvm_mips_bseti_h_RES 391 ret void 392 } 393 394 declare <8 x i16> @llvm.mips.bseti.h(<8 x i16>, i32) nounwind 395 396 ; CHECK: llvm_mips_bseti_h_test: 397 ; CHECK: ld.h 398 ; CHECK: bseti.h 399 ; CHECK: st.h 400 ; CHECK: .size llvm_mips_bseti_h_test 401 ; 402 @llvm_mips_bseti_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 403 @llvm_mips_bseti_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 404 405 define void @llvm_mips_bseti_w_test() nounwind { 406 entry: 407 %0 = load <4 x i32>* @llvm_mips_bseti_w_ARG1 408 %1 = tail call <4 x i32> @llvm.mips.bseti.w(<4 x i32> %0, i32 7) 409 store <4 x i32> %1, <4 x i32>* @llvm_mips_bseti_w_RES 410 ret void 411 } 412 413 declare <4 x i32> @llvm.mips.bseti.w(<4 x i32>, i32) nounwind 414 415 ; CHECK: llvm_mips_bseti_w_test: 416 ; CHECK: ld.w 417 ; CHECK: bseti.w 418 ; CHECK: st.w 419 ; CHECK: .size llvm_mips_bseti_w_test 420 ; 421 @llvm_mips_bseti_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 422 @llvm_mips_bseti_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 423 424 define void @llvm_mips_bseti_d_test() nounwind { 425 entry: 426 %0 = load <2 x i64>* @llvm_mips_bseti_d_ARG1 427 %1 = tail call <2 x i64> @llvm.mips.bseti.d(<2 x i64> %0, i32 7) 428 store <2 x i64> %1, <2 x i64>* @llvm_mips_bseti_d_RES 429 ret void 430 } 431 432 declare <2 x i64> @llvm.mips.bseti.d(<2 x i64>, i32) nounwind 433 434 ; CHECK: llvm_mips_bseti_d_test: 435 ; CHECK: ld.d 436 ; CHECK: bseti.d 437 ; CHECK: st.d 438 ; CHECK: .size llvm_mips_bseti_d_test 439 ; 440
