1 ; Test the MSA intrinsics that are encoded with the VECS10 instruction format. 2 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 5 6 @llvm_mips_bnz_v_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 7 8 define i32 @llvm_mips_bnz_v_test() nounwind { 9 entry: 10 %0 = load <16 x i8>* @llvm_mips_bnz_v_ARG1 11 %1 = tail call i32 @llvm.mips.bnz.v(<16 x i8> %0) 12 %2 = icmp eq i32 %1, 0 13 br i1 %2, label %true, label %false 14 true: 15 ret i32 2 16 false: 17 ret i32 3 18 } 19 20 declare i32 @llvm.mips.bnz.v(<16 x i8>) nounwind 21 22 ; CHECK: llvm_mips_bnz_v_test: 23 ; CHECK-DAG: ld.b [[R0:\$w[0-9]+]] 24 ; CHECK-DAG: bnz.v [[R0]] 25 ; CHECK: .size llvm_mips_bnz_v_test 26 27 @llvm_mips_bz_v_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 28 29 define i32 @llvm_mips_bz_v_test() nounwind { 30 entry: 31 %0 = load <16 x i8>* @llvm_mips_bz_v_ARG1 32 %1 = tail call i32 @llvm.mips.bz.v(<16 x i8> %0) 33 %2 = icmp eq i32 %1, 0 34 br i1 %2, label %true, label %false 35 true: 36 ret i32 2 37 false: 38 ret i32 3 39 } 40 41 declare i32 @llvm.mips.bz.v(<16 x i8>) nounwind 42 43 ; CHECK: llvm_mips_bz_v_test: 44 ; CHECK-DAG: ld.b [[R0:\$w[0-9]+]] 45 ; CHECK-DAG: bz.v [[R0]] 46 ; CHECK: .size llvm_mips_bz_v_test 47 ; 48
