1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s 2 3 ; Test using an integer literal constant. 4 ; Generated ASM should be: 5 ; ADD_INT KC0[2].Z literal.x, 5 6 ; or 7 ; ADD_INT literal.x KC0[2].Z, 5 8 9 ; CHECK: @i32_literal 10 ; CHECK: ADD_INT {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x 11 ; CHECK-NEXT: LSHR 12 ; CHECK-NEXT: 5 13 define void @i32_literal(i32 addrspace(1)* %out, i32 %in) { 14 entry: 15 %0 = add i32 5, %in 16 store i32 %0, i32 addrspace(1)* %out 17 ret void 18 } 19 20 ; Test using a float literal constant. 21 ; Generated ASM should be: 22 ; ADD KC0[2].Z literal.x, 5.0 23 ; or 24 ; ADD literal.x KC0[2].Z, 5.0 25 26 ; CHECK: @float_literal 27 ; CHECK: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x 28 ; CHECK-NEXT: LSHR 29 ; CHECK-NEXT: 1084227584(5.0 30 define void @float_literal(float addrspace(1)* %out, float %in) { 31 entry: 32 %0 = fadd float 5.0, %in 33 store float %0, float addrspace(1)* %out 34 ret void 35 } 36 37 ; Make sure inline literals are folded into REG_SEQUENCE instructions. 38 ; CHECK: @inline_literal_reg_sequence 39 ; CHECK: MOV {{\** *}}T[[GPR:[0-9]]].X, 0.0 40 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Y, 0.0 41 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Z, 0.0 42 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].W, 0.0 43 44 define void @inline_literal_reg_sequence(<4 x i32> addrspace(1)* %out) { 45 entry: 46 store <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> addrspace(1)* %out 47 ret void 48 } 49 50 ; CHECK: @inline_literal_dot4 51 ; CHECK: DOT4 T[[GPR:[0-9]]].X, 1.0 52 ; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0 53 ; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0 54 ; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0 55 define void @inline_literal_dot4(float addrspace(1)* %out) { 56 entry: 57 %0 = call float @llvm.AMDGPU.dp4(<4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>) 58 store float %0, float addrspace(1)* %out 59 ret void 60 } 61 62 declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 63 64 attributes #1 = { readnone } 65
