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      1 ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s
      2 
      3 ; SI-LABEL: @vector_umin
      4 ; SI: V_MIN_U32_e32
      5 define void @vector_umin(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 {
      6 main_body:
      7   %load = load i32 addrspace(1)* %in, align 4
      8   %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %load)
      9   %bc = bitcast i32 %min to float
     10   call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
     11   ret void
     12 }
     13 
     14 ; SI-LABEL: @scalar_umin
     15 ; SI: S_MIN_U32
     16 define void @scalar_umin(i32 %p0, i32 %p1) #0 {
     17 entry:
     18   %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %p1)
     19   %bc = bitcast i32 %min to float
     20   call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
     21   ret void
     22 }
     23 
     24 ; SI-LABEL: @trunc_zext_umin
     25 ; SI: BUFFER_LOAD_UBYTE [[VREG:v[0-9]+]],
     26 ; SI: V_MIN_U32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]]
     27 ; SI-NOT: AND
     28 ; SI: BUFFER_STORE_SHORT [[RESULT]],
     29 define void @trunc_zext_umin(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
     30   %tmp5 = load i8 addrspace(1)* %src, align 1
     31   %tmp2 = zext i8 %tmp5 to i32
     32   %tmp3 = tail call i32 @llvm.AMDGPU.umin(i32 %tmp2, i32 0) nounwind readnone
     33   %tmp4 = trunc i32 %tmp3 to i8
     34   %tmp6 = zext i8 %tmp4 to i16
     35   store i16 %tmp6, i16 addrspace(1)* %out, align 2
     36   ret void
     37 }
     38 
     39 ; Function Attrs: readnone
     40 declare i32 @llvm.AMDGPU.umin(i32, i32) #1
     41 
     42 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
     43 
     44 attributes #0 = { nounwind }
     45 attributes #1 = { nounwind readnone }
     46 
     47 !0 = metadata !{metadata !"const", null, i32 1}
     48