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      1 ; RUN: opt < %s -S -inline -inline-threshold=2 | FileCheck %s
      2 ; RUN: opt < %s -S -strip-debug -inline -inline-threshold=2 | FileCheck %s
      3 ;
      4 ; The purpose of this test is to check that debug info doesn't influence
      5 ; inlining decisions.
      6 
      7 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
      8 target triple = "x86_64-unknown-linux-gnu"
      9 
     10 declare void @llvm.dbg.declare(metadata, metadata) #1
     11 declare void @llvm.dbg.value(metadata, i64, metadata) #1
     12 
     13 define <4 x float> @inner_vectors(<4 x float> %a, <4 x float> %b) {
     14 entry:
     15   call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{})
     16   %mul = fmul <4 x float> %a, <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>
     17   call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{})
     18   %mul1 = fmul <4 x float> %b, <float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00>
     19   call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{})
     20   %add = fadd <4 x float> %mul, %mul1
     21   ret <4 x float> %add
     22 }
     23 
     24 define float @outer_vectors(<4 x float> %a, <4 x float> %b) {
     25 ; CHECK-LABEL: @outer_vectors(
     26 ; CHECK-NOT: call <4 x float> @inner_vectors(
     27 ; CHECK: ret float
     28 
     29 entry:
     30   call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{})
     31   call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{})
     32   %call = call <4 x float> @inner_vectors(<4 x float> %a, <4 x float> %b)
     33   call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{})
     34   %vecext = extractelement <4 x float> %call, i32 0
     35   %vecext1 = extractelement <4 x float> %call, i32 1
     36   %add = fadd float %vecext, %vecext1
     37   %vecext2 = extractelement <4 x float> %call, i32 2
     38   %add3 = fadd float %add, %vecext2
     39   %vecext4 = extractelement <4 x float> %call, i32 3
     40   %add5 = fadd float %add3, %vecext4
     41   ret float %add5
     42 }
     43 
     44 attributes #0 = { nounwind readnone }
     45 
     46 !llvm.dbg.cu = !{!0}
     47 !llvm.module.flags = !{!3, !4}
     48 !llvm.ident = !{!5}
     49 
     50 !0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !{}, metadata !2, metadata !2, metadata !""}
     51 !1 = metadata !{metadata !"", metadata !""}
     52 !2 = metadata !{i32 0}
     53 !3 = metadata !{i32 2, metadata !"Dwarf Version", i32 4}
     54 !4 = metadata !{i32 1, metadata !"Debug Info Version", i32 1}
     55 !5 = metadata !{metadata !""}
     56