1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 def isSI : Predicate<"Subtarget.device()" 11 "->getGeneration() == AMDGPUDeviceInfo::HD7XXX">; 12 13 let Predicates = [isSI] in { 14 15 let neverHasSideEffects = 1 in { 16 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; 17 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; 18 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; 19 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; 20 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>; 21 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; 22 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; 23 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; 24 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; 25 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; 26 } // End neverHasSideEffects = 1 27 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; 28 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; 29 ////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; 30 ////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; 31 ////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; 32 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; 33 ////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; 34 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; 35 //def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; 36 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; 37 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; 38 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; 39 //def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>; 40 //def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>; 41 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; 42 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; 43 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; 44 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; 45 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; 46 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; 47 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; 48 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; 49 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; 50 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; 51 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; 52 ////def S_ANDN2_SAVEEXEC_B64 : SOP1_ANDN2 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; 53 ////def S_ORN2_SAVEEXEC_B64 : SOP1_ORN2 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; 54 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; 55 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; 56 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; 57 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; 58 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; 59 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; 60 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; 61 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; 62 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; 63 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; 64 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; 65 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; 66 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; 67 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; 68 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; 69 70 /* 71 This instruction is disabled for now until we can figure out how to teach 72 the instruction selector to correctly use the S_CMP* vs V_CMP* 73 instructions. 74 75 When this instruction is enabled the code generator sometimes produces this 76 invalid sequence: 77 78 SCC = S_CMPK_EQ_I32 SGPR0, imm 79 VCC = COPY SCC 80 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 81 82 def S_CMPK_EQ_I32 : SOPK < 83 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), 84 "S_CMPK_EQ_I32", 85 [(set SCCReg:$dst, (setcc SReg_32:$src0, imm:$src1, SETEQ))] 86 >; 87 */ 88 89 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; 90 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; 91 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; 92 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; 93 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; 94 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; 95 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; 96 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; 97 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; 98 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; 99 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; 100 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; 101 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; 102 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; 103 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; 104 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; 105 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; 106 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; 107 //def EXP : EXP_ <0x00000000, "EXP", []>; 108 109 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32", []>; 110 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", 111 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LT))] 112 >; 113 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", 114 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_EQ))] 115 >; 116 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", 117 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LE))] 118 >; 119 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", 120 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GT))] 121 >; 122 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", 123 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE))] 124 >; 125 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", 126 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GE))] 127 >; 128 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", []>; 129 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", []>; 130 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32", []>; 131 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32", []>; 132 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32", []>; 133 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32", []>; 134 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", 135 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE))] 136 >; 137 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32", []>; 138 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32", []>; 139 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32", []>; 140 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32", []>; 141 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32", []>; 142 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32", []>; 143 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32", []>; 144 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32", []>; 145 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32", []>; 146 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32", []>; 147 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32", []>; 148 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32", []>; 149 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32", []>; 150 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32", []>; 151 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32", []>; 152 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32", []>; 153 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32", []>; 154 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32", []>; 155 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64", []>; 156 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", []>; 157 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", []>; 158 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", []>; 159 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", []>; 160 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64", []>; 161 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", []>; 162 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", []>; 163 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", []>; 164 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64", []>; 165 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64", []>; 166 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64", []>; 167 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64", []>; 168 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", []>; 169 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64", []>; 170 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64", []>; 171 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64", []>; 172 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64", []>; 173 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64", []>; 174 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64", []>; 175 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64", []>; 176 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64", []>; 177 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64", []>; 178 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64", []>; 179 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64", []>; 180 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64", []>; 181 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64", []>; 182 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64", []>; 183 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64", []>; 184 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64", []>; 185 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64", []>; 186 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64", []>; 187 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32", []>; 188 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32", []>; 189 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32", []>; 190 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32", []>; 191 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32", []>; 192 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32", []>; 193 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32", []>; 194 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32", []>; 195 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32", []>; 196 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32", []>; 197 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32", []>; 198 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32", []>; 199 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32", []>; 200 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32", []>; 201 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32", []>; 202 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32", []>; 203 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32", []>; 204 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32", []>; 205 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32", []>; 206 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32", []>; 207 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32", []>; 208 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32", []>; 209 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32", []>; 210 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32", []>; 211 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32", []>; 212 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32", []>; 213 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32", []>; 214 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32", []>; 215 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32", []>; 216 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32", []>; 217 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32", []>; 218 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32", []>; 219 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64", []>; 220 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64", []>; 221 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64", []>; 222 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64", []>; 223 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64", []>; 224 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64", []>; 225 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64", []>; 226 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64", []>; 227 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64", []>; 228 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64", []>; 229 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64", []>; 230 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64", []>; 231 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64", []>; 232 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64", []>; 233 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64", []>; 234 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64", []>; 235 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64", []>; 236 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64", []>; 237 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64", []>; 238 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64", []>; 239 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64", []>; 240 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64", []>; 241 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64", []>; 242 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64", []>; 243 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64", []>; 244 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64", []>; 245 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64", []>; 246 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64", []>; 247 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64", []>; 248 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64", []>; 249 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64", []>; 250 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64", []>; 251 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32", []>; 252 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", []>; 253 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", 254 [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETEQ))] 255 >; 256 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", []>; 257 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", []>; 258 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", 259 [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETNE))] 260 >; 261 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", []>; 262 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32", []>; 263 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32", []>; 264 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32", []>; 265 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32", []>; 266 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32", []>; 267 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32", []>; 268 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32", []>; 269 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32", []>; 270 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32", []>; 271 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64", []>; 272 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", []>; 273 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", []>; 274 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", []>; 275 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", []>; 276 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", []>; 277 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", []>; 278 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64", []>; 279 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64", []>; 280 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64", []>; 281 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64", []>; 282 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64", []>; 283 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64", []>; 284 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64", []>; 285 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64", []>; 286 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64", []>; 287 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32", []>; 288 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", []>; 289 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", []>; 290 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", []>; 291 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", []>; 292 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", []>; 293 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", []>; 294 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32", []>; 295 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32", []>; 296 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32", []>; 297 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32", []>; 298 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32", []>; 299 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32", []>; 300 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32", []>; 301 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32", []>; 302 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32", []>; 303 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64", []>; 304 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", []>; 305 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", []>; 306 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", []>; 307 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", []>; 308 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", []>; 309 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", []>; 310 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64", []>; 311 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64", []>; 312 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64", []>; 313 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64", []>; 314 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64", []>; 315 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64", []>; 316 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64", []>; 317 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64", []>; 318 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64", []>; 319 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32", []>; 320 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32", []>; 321 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64", []>; 322 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64", []>; 323 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; 324 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; 325 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; 326 def BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; 327 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; 328 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; 329 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; 330 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; 331 //def BUFFER_LOAD_UBYTE : MUBUF_ <0x00000008, "BUFFER_LOAD_UBYTE", []>; 332 //def BUFFER_LOAD_SBYTE : MUBUF_ <0x00000009, "BUFFER_LOAD_SBYTE", []>; 333 //def BUFFER_LOAD_USHORT : MUBUF_ <0x0000000a, "BUFFER_LOAD_USHORT", []>; 334 //def BUFFER_LOAD_SSHORT : MUBUF_ <0x0000000b, "BUFFER_LOAD_SSHORT", []>; 335 //def BUFFER_LOAD_DWORD : MUBUF_ <0x0000000c, "BUFFER_LOAD_DWORD", []>; 336 //def BUFFER_LOAD_DWORDX2 : MUBUF_DWORDX2 <0x0000000d, "BUFFER_LOAD_DWORDX2", []>; 337 //def BUFFER_LOAD_DWORDX4 : MUBUF_DWORDX4 <0x0000000e, "BUFFER_LOAD_DWORDX4", []>; 338 //def BUFFER_STORE_BYTE : MUBUF_ <0x00000018, "BUFFER_STORE_BYTE", []>; 339 //def BUFFER_STORE_SHORT : MUBUF_ <0x0000001a, "BUFFER_STORE_SHORT", []>; 340 //def BUFFER_STORE_DWORD : MUBUF_ <0x0000001c, "BUFFER_STORE_DWORD", []>; 341 //def BUFFER_STORE_DWORDX2 : MUBUF_DWORDX2 <0x0000001d, "BUFFER_STORE_DWORDX2", []>; 342 //def BUFFER_STORE_DWORDX4 : MUBUF_DWORDX4 <0x0000001e, "BUFFER_STORE_DWORDX4", []>; 343 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; 344 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; 345 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; 346 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; 347 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; 348 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; 349 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; 350 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; 351 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; 352 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; 353 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; 354 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; 355 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; 356 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; 357 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; 358 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; 359 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; 360 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; 361 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; 362 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; 363 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; 364 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; 365 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; 366 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; 367 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; 368 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; 369 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; 370 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; 371 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; 372 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; 373 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; 374 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; 375 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; 376 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; 377 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; 378 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; 379 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; 380 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; 381 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; 382 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; 383 //def TBUFFER_STORE_FORMAT_X : MTBUF_ <0x00000004, "TBUFFER_STORE_FORMAT_X", []>; 384 //def TBUFFER_STORE_FORMAT_XY : MTBUF_ <0x00000005, "TBUFFER_STORE_FORMAT_XY", []>; 385 //def TBUFFER_STORE_FORMAT_XYZ : MTBUF_ <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", []>; 386 //def TBUFFER_STORE_FORMAT_XYZW : MTBUF_ <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", []>; 387 388 defm S_LOAD_DWORD : SMRD_32 <0x00000000, "S_LOAD_DWORD", SReg_32>; 389 390 //def S_LOAD_DWORDX2 : SMRD_DWORDX2 <0x00000001, "S_LOAD_DWORDX2", []>; 391 defm S_LOAD_DWORDX4 : SMRD_Helper <0x00000002, "S_LOAD_DWORDX4", SReg_128, v4i32>; 392 defm S_LOAD_DWORDX8 : SMRD_Helper <0x00000003, "S_LOAD_DWORDX8", SReg_256, v8i32>; 393 //def S_LOAD_DWORDX16 : SMRD_DWORDX16 <0x00000004, "S_LOAD_DWORDX16", []>; 394 //def S_BUFFER_LOAD_DWORD : SMRD_ <0x00000008, "S_BUFFER_LOAD_DWORD", []>; 395 //def S_BUFFER_LOAD_DWORDX2 : SMRD_DWORDX2 <0x00000009, "S_BUFFER_LOAD_DWORDX2", []>; 396 //def S_BUFFER_LOAD_DWORDX4 : SMRD_DWORDX4 <0x0000000a, "S_BUFFER_LOAD_DWORDX4", []>; 397 //def S_BUFFER_LOAD_DWORDX8 : SMRD_DWORDX8 <0x0000000b, "S_BUFFER_LOAD_DWORDX8", []>; 398 //def S_BUFFER_LOAD_DWORDX16 : SMRD_DWORDX16 <0x0000000c, "S_BUFFER_LOAD_DWORDX16", []>; 399 400 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; 401 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; 402 //def IMAGE_LOAD : MIMG_NoPattern_ <"IMAGE_LOAD", 0x00000000>; 403 //def IMAGE_LOAD_MIP : MIMG_NoPattern_ <"IMAGE_LOAD_MIP", 0x00000001>; 404 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; 405 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; 406 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; 407 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; 408 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; 409 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; 410 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; 411 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; 412 //def IMAGE_GET_RESINFO : MIMG_NoPattern_ <"IMAGE_GET_RESINFO", 0x0000000e>; 413 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; 414 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; 415 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; 416 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; 417 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; 418 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; 419 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; 420 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; 421 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; 422 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; 423 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; 424 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; 425 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; 426 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; 427 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; 428 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; 429 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; 430 def IMAGE_SAMPLE : MIMG_Load_Helper <0x00000020, "IMAGE_SAMPLE">; 431 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; 432 //def IMAGE_SAMPLE_D : MIMG_NoPattern_ <"IMAGE_SAMPLE_D", 0x00000022>; 433 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; 434 //def IMAGE_SAMPLE_L : MIMG_NoPattern_ <"IMAGE_SAMPLE_L", 0x00000024>; 435 //def IMAGE_SAMPLE_B : MIMG_NoPattern_ <"IMAGE_SAMPLE_B", 0x00000025>; 436 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; 437 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; 438 //def IMAGE_SAMPLE_C : MIMG_NoPattern_ <"IMAGE_SAMPLE_C", 0x00000028>; 439 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; 440 //def IMAGE_SAMPLE_C_D : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D", 0x0000002a>; 441 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; 442 //def IMAGE_SAMPLE_C_L : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L", 0x0000002c>; 443 //def IMAGE_SAMPLE_C_B : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B", 0x0000002d>; 444 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; 445 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; 446 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; 447 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; 448 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; 449 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; 450 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; 451 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; 452 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; 453 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; 454 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; 455 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; 456 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; 457 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; 458 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; 459 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; 460 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; 461 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; 462 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; 463 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; 464 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; 465 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; 466 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; 467 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; 468 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; 469 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; 470 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; 471 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; 472 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; 473 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; 474 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; 475 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; 476 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; 477 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; 478 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; 479 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; 480 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; 481 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; 482 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; 483 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; 484 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; 485 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; 486 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; 487 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; 488 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; 489 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; 490 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; 491 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; 492 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; 493 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; 494 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; 495 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; 496 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; 497 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; 498 499 let neverHasSideEffects = 1 in { 500 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; 501 } // End neverHasSideEffects 502 defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; 503 //defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>; 504 //defm V_CVT_F64_I32 : VOP1_64 <0x00000004, "V_CVT_F64_I32", []>; 505 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", 506 [(set VReg_32:$dst, (fp_to_sint AllReg_32:$src0))] 507 >; 508 //defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", []>; 509 //defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", []>; 510 //defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", []>; 511 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; 512 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; 513 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; 514 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; 515 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; 516 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; 517 //defm V_CVT_F32_F64 : VOP1_32 <0x0000000f, "V_CVT_F32_F64", []>; 518 //defm V_CVT_F64_F32 : VOP1_64 <0x00000010, "V_CVT_F64_F32", []>; 519 //defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; 520 //defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; 521 //defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; 522 //defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; 523 //defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; 524 //defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; 525 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", []>; 526 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", []>; 527 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", []>; 528 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", []>; 529 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", []>; 530 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", []>; 531 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; 532 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", []>; 533 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; 534 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; 535 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", []>; 536 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; 537 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; 538 defm V_RSQ_LEGACY_F32 : VOP1_32 < 539 0x0000002d, "V_RSQ_LEGACY_F32", 540 [(set VReg_32:$dst, (int_AMDGPU_rsq AllReg_32:$src0))] 541 >; 542 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; 543 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", []>; 544 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; 545 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; 546 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; 547 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", []>; 548 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", []>; 549 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; 550 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; 551 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; 552 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; 553 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; 554 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; 555 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; 556 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; 557 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; 558 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; 559 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; 560 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; 561 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; 562 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; 563 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; 564 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; 565 566 def V_INTERP_P1_F32 : VINTRP < 567 0x00000000, 568 (outs VReg_32:$dst), 569 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 570 "V_INTERP_P1_F32", 571 []> { 572 let DisableEncoding = "$m0"; 573 } 574 575 def V_INTERP_P2_F32 : VINTRP < 576 0x00000001, 577 (outs VReg_32:$dst), 578 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 579 "V_INTERP_P2_F32", 580 []> { 581 582 let Constraints = "$src0 = $dst"; 583 let DisableEncoding = "$src0,$m0"; 584 585 } 586 587 def V_INTERP_MOV_F32 : VINTRP < 588 0x00000002, 589 (outs VReg_32:$dst), 590 (ins i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 591 "V_INTERP_MOV_F32", 592 []> { 593 let VSRC = 0; 594 let DisableEncoding = "$m0"; 595 } 596 597 //def S_NOP : SOPP_ <0x00000000, "S_NOP", []>; 598 599 let isTerminator = 1 in { 600 601 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", 602 [(IL_retflag)]> { 603 let SIMM16 = 0; 604 let isBarrier = 1; 605 let hasCtrlDep = 1; 606 } 607 608 let isBranch = 1 in { 609 def S_BRANCH : SOPP < 610 0x00000002, (ins brtarget:$target), "S_BRANCH", 611 [] 612 >; 613 614 let DisableEncoding = "$scc" in { 615 def S_CBRANCH_SCC0 : SOPP < 616 0x00000004, (ins brtarget:$target, SCCReg:$scc), 617 "S_CBRANCH_SCC0", [] 618 >; 619 def S_CBRANCH_SCC1 : SOPP < 620 0x00000005, (ins brtarget:$target, SCCReg:$scc), 621 "S_CBRANCH_SCC1", 622 [] 623 >; 624 } // End DisableEncoding = "$scc" 625 626 def S_CBRANCH_VCCZ : SOPP < 627 0x00000006, (ins brtarget:$target, VCCReg:$vcc), 628 "S_CBRANCH_VCCZ", 629 [] 630 >; 631 def S_CBRANCH_VCCNZ : SOPP < 632 0x00000007, (ins brtarget:$target, VCCReg:$vcc), 633 "S_CBRANCH_VCCNZ", 634 [] 635 >; 636 637 let DisableEncoding = "$exec" in { 638 def S_CBRANCH_EXECZ : SOPP < 639 0x00000008, (ins brtarget:$target, EXECReg:$exec), 640 "S_CBRANCH_EXECZ", 641 [] 642 >; 643 def S_CBRANCH_EXECNZ : SOPP < 644 0x00000009, (ins brtarget:$target, EXECReg:$exec), 645 "S_CBRANCH_EXECNZ", 646 [] 647 >; 648 } // End DisableEncoding = "$exec" 649 650 651 } // End isBranch = 1 652 } // End isTerminator = 1 653 654 //def S_BARRIER : SOPP_ <0x0000000a, "S_BARRIER", []>; 655 def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16", 656 [] 657 >; 658 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; 659 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; 660 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; 661 //def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>; 662 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; 663 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; 664 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; 665 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; 666 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; 667 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; 668 669 /* XXX: No VOP3 version of this instruction yet */ 670 def V_CNDMASK_B32 : VOP2 <0x00000000, (outs VReg_32:$dst), 671 (ins VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1), "V_CNDMASK_B32", 672 [(set (i32 VReg_32:$dst), 673 (select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1))] > { 674 675 let DisableEncoding = "$vcc"; 676 } 677 678 //f32 pattern for V_CNDMASK_B32 679 def : Pat < 680 (f32 (select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1)), 681 (V_CNDMASK_B32 VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1) 682 >; 683 684 defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; 685 defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>; 686 687 defm V_ADD_F32 : VOP2_32 < 688 0x00000003, "V_ADD_F32", 689 [(set VReg_32:$dst, (fadd AllReg_32:$src0, VReg_32:$src1))] 690 >; 691 692 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", 693 [(set VReg_32:$dst, (fsub AllReg_32:$src0, VReg_32:$src1))] 694 >; 695 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", []>; 696 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; 697 defm V_MUL_LEGACY_F32 : VOP2_32 < 698 0x00000007, "V_MUL_LEGACY_F32", 699 [(set VReg_32:$dst, (int_AMDGPU_mul AllReg_32:$src0, VReg_32:$src1))] 700 >; 701 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", []>; 702 //defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", []>; 703 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; 704 //defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", []>; 705 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; 706 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", []>; 707 708 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", 709 [(set VReg_32:$dst, (AMDGPUfmax AllReg_32:$src0, VReg_32:$src1))] 710 >; 711 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; 712 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; 713 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", []>; 714 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", []>; 715 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", []>; 716 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", []>; 717 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", []>; 718 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", []>; 719 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", []>; 720 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", []>; 721 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", []>; 722 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", []>; 723 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", []>; 724 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", []>; 725 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", []>; 726 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>; 727 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; 728 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; 729 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; 730 //defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; 731 //defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; 732 //defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; 733 defm V_ADD_I32 : VOP2_32 <0x00000025, "V_ADD_I32", []>; 734 defm V_SUB_I32 : VOP2_32 <0x00000026, "V_SUB_I32", []>; 735 defm V_SUBREV_I32 : VOP2_32 <0x00000027, "V_SUBREV_I32", []>; 736 defm V_ADDC_U32 : VOP2_32 <0x00000028, "V_ADDC_U32", []>; 737 defm V_SUBB_U32 : VOP2_32 <0x00000029, "V_SUBB_U32", []>; 738 defm V_SUBBREV_U32 : VOP2_32 <0x0000002a, "V_SUBBREV_U32", []>; 739 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; 740 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; 741 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; 742 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; 743 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", 744 [(set VReg_32:$dst, (int_SI_packf16 AllReg_32:$src0, VReg_32:$src1))] 745 >; 746 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; 747 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; 748 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>; 749 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>; 750 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>; 751 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>; 752 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>; 753 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>; 754 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>; 755 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>; 756 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>; 757 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>; 758 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>; 759 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>; 760 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; 761 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; 762 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; 763 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; 764 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; 765 766 let neverHasSideEffects = 1 in { 767 768 def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; 769 def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>; 770 //def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", []>; 771 //def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", []>; 772 773 } // End neverHasSideEffects 774 def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; 775 def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; 776 def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; 777 def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; 778 def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>; 779 def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>; 780 def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; 781 def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>; 782 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>; 783 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; 784 def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; 785 def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; 786 def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; 787 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; 788 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; 789 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; 790 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; 791 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; 792 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; 793 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; 794 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; 795 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; 796 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; 797 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; 798 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; 799 def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; 800 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; 801 def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; 802 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; 803 def V_LSHL_B64 : VOP3_64 <0x00000161, "V_LSHL_B64", []>; 804 def V_LSHR_B64 : VOP3_64 <0x00000162, "V_LSHR_B64", []>; 805 def V_ASHR_I64 : VOP3_64 <0x00000163, "V_ASHR_I64", []>; 806 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; 807 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; 808 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; 809 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; 810 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; 811 def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; 812 def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; 813 def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; 814 def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; 815 def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; 816 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; 817 def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; 818 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; 819 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; 820 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; 821 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; 822 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; 823 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; 824 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; 825 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", []>; 826 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", []>; 827 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", []>; 828 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", []>; 829 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>; 830 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>; 831 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>; 832 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>; 833 834 def S_CSELECT_B32 : SOP2 < 835 0x0000000a, (outs SReg_32:$dst), 836 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", 837 [(set (i32 SReg_32:$dst), (select SCCReg:$scc, SReg_32:$src0, SReg_32:$src1))] 838 >; 839 840 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; 841 842 // f32 pattern for S_CSELECT_B32 843 def : Pat < 844 (f32 (select SCCReg:$scc, SReg_32:$src0, SReg_32:$src1)), 845 (S_CSELECT_B32 SReg_32:$src0, SReg_32:$src1, SCCReg:$scc) 846 >; 847 848 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>; 849 850 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", 851 [(set SReg_64:$dst, (and SReg_64:$src0, SReg_64:$src1))] 852 >; 853 def S_AND_VCC : SOP2_VCC <0x0000000f, "S_AND_B64", 854 [(set VCCReg:$vcc, (SIvcc_and SReg_64:$src0, SReg_64:$src1))] 855 >; 856 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>; 857 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>; 858 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>; 859 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", []>; 860 ////def S_ANDN2_B32 : SOP2_ANDN2 <0x00000014, "S_ANDN2_B32", []>; 861 ////def S_ANDN2_B64 : SOP2_ANDN2 <0x00000015, "S_ANDN2_B64", []>; 862 ////def S_ORN2_B32 : SOP2_ORN2 <0x00000016, "S_ORN2_B32", []>; 863 ////def S_ORN2_B64 : SOP2_ORN2 <0x00000017, "S_ORN2_B64", []>; 864 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; 865 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; 866 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; 867 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; 868 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; 869 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; 870 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", []>; 871 def S_LSHL_B64 : SOP2_64 <0x0000001f, "S_LSHL_B64", []>; 872 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", []>; 873 def S_LSHR_B64 : SOP2_64 <0x00000021, "S_LSHR_B64", []>; 874 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", []>; 875 def S_ASHR_I64 : SOP2_64 <0x00000023, "S_ASHR_I64", []>; 876 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; 877 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; 878 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; 879 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; 880 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; 881 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; 882 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; 883 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; 884 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; 885 886 class V_MOV_IMM <Operand immType, SDNode immNode> : VOP1 < 887 0x1, 888 (outs VReg_32:$dst), 889 (ins immType:$src0), 890 "V_MOV_IMM", 891 [(set VReg_32:$dst, (immNode:$src0))] 892 >; 893 894 def V_MOV_IMM_I32 : V_MOV_IMM<i32imm, imm>; 895 def V_MOV_IMM_F32 : V_MOV_IMM<f32imm, fpimm>; 896 897 def S_MOV_IMM_I32 : SOP1 < 898 0x3, 899 (outs SReg_32:$dst), 900 (ins i32Literal:$src0), 901 "S_MOV_IMM_I32", 902 [(set SReg_32:$dst, (imm:$src0))] 903 >; 904 905 // i64 immediates aren't really supported in hardware, but LLVM will use the i64 906 // type for indices on load and store instructions. The pattern for 907 // S_MOV_IMM_I64 will only match i64 immediates that can fit into 32-bits, 908 // which the hardware can handle. 909 def S_MOV_IMM_I64 : SOP1 < 910 0x3, 911 (outs SReg_64:$dst), 912 (ins i64Literal:$src0), 913 "S_MOV_IMM_I64 $dst, $src0", 914 [(set SReg_64:$dst, (IMM32bitIn64bit:$src0))] 915 >; 916 917 let isCodeGenOnly = 1, isPseudo = 1 in { 918 919 def SET_M0 : InstSI < 920 (outs SReg_32:$dst), 921 (ins i32imm:$src0), 922 "SET_M0", 923 [(set SReg_32:$dst, (int_SI_set_M0 imm:$src0))] 924 >; 925 926 def CONFIG_WRITE : InstSI < 927 (outs i32imm:$reg), 928 (ins i32imm:$val), 929 "CONFIG_WRITE $reg, $val", 930 [] > { 931 field bits<32> Inst = 0; 932 } 933 934 def LOAD_CONST : AMDGPUShaderInst < 935 (outs GPRF32:$dst), 936 (ins i32imm:$src), 937 "LOAD_CONST $dst, $src", 938 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] 939 >; 940 941 let usesCustomInserter = 1 in { 942 943 def SI_V_CNDLT : InstSI < 944 (outs VReg_32:$dst), 945 (ins VReg_32:$src0, VReg_32:$src1, VReg_32:$src2), 946 "SI_V_CNDLT $dst, $src0, $src1, $src2", 947 [(set VReg_32:$dst, (int_AMDGPU_cndlt VReg_32:$src0, VReg_32:$src1, VReg_32:$src2))] 948 >; 949 950 def SI_INTERP : InstSI < 951 (outs VReg_32:$dst), 952 (ins VReg_32:$i, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, SReg_32:$params), 953 "SI_INTERP $dst, $i, $j, $attr_chan, $attr, $params", 954 [] 955 >; 956 957 def SI_INTERP_CONST : InstSI < 958 (outs VReg_32:$dst), 959 (ins i32imm:$attr_chan, i32imm:$attr, SReg_32:$params), 960 "SI_INTERP_CONST $dst, $attr_chan, $attr, $params", 961 [(set VReg_32:$dst, (int_SI_fs_interp_constant imm:$attr_chan, 962 imm:$attr, SReg_32:$params))] 963 >; 964 965 def SI_KIL : InstSI < 966 (outs), 967 (ins VReg_32:$src), 968 "SI_KIL $src", 969 [(int_AMDGPU_kill VReg_32:$src)] 970 >; 971 972 } // end usesCustomInserter 973 974 // SI Psuedo branch instructions. These are used by the CFG structurizer pass 975 // and should be lowered to ISA instructions prior to codegen. 976 977 let isBranch = 1, isTerminator = 1 in { 978 def SI_IF_NZ : InstSI < 979 (outs), 980 (ins brtarget:$target, VCCReg:$vcc), 981 "SI_BRANCH_NZ", 982 [(IL_brcond bb:$target, VCCReg:$vcc)] 983 >; 984 985 def SI_IF_Z : InstSI < 986 (outs), 987 (ins brtarget:$target, VCCReg:$vcc), 988 "SI_BRANCH_Z", 989 [] 990 >; 991 } // end isBranch = 1, isTerminator = 1 992 } // end IsCodeGenOnly, isPseudo 993 994 /* int_SI_vs_load_input */ 995 def : Pat< 996 (int_SI_vs_load_input SReg_128:$tlst, IMM12bit:$attr_offset, 997 VReg_32:$buf_idx_vgpr), 998 (BUFFER_LOAD_FORMAT_XYZW imm:$attr_offset, 0, 1, 0, 0, 0, 999 VReg_32:$buf_idx_vgpr, SReg_128:$tlst, 1000 0, 0, (i32 SREG_LIT_0)) 1001 >; 1002 1003 /* int_SI_export */ 1004 def : Pat < 1005 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 1006 VReg_32:$src0,VReg_32:$src1, VReg_32:$src2, VReg_32:$src3), 1007 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 1008 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3) 1009 >; 1010 1011 /* int_SI_sample */ 1012 def : Pat < 1013 (int_SI_sample imm:$writemask, VReg_128:$coord, SReg_256:$rsrc, SReg_128:$sampler), 1014 (IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_128:$coord, 1015 SReg_256:$rsrc, SReg_128:$sampler) 1016 >; 1017 1018 def CLAMP_SI : CLAMP<VReg_32>; 1019 def FABS_SI : FABS<VReg_32>; 1020 def FNEG_SI : FNEG<VReg_32>; 1021 1022 def : Extract_Element <f32, v4f32, VReg_128, 0, sel_x>; 1023 def : Extract_Element <f32, v4f32, VReg_128, 1, sel_y>; 1024 def : Extract_Element <f32, v4f32, VReg_128, 2, sel_z>; 1025 def : Extract_Element <f32, v4f32, VReg_128, 3, sel_w>; 1026 1027 def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 4, sel_x>; 1028 def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 5, sel_y>; 1029 def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 6, sel_z>; 1030 def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 7, sel_w>; 1031 1032 def : Vector_Build <v4f32, VReg_32>; 1033 def : Vector_Build <v4i32, SReg_32>; 1034 1035 def : BitConvert <i32, f32, SReg_32>; 1036 def : BitConvert <i32, f32, VReg_32>; 1037 1038 def : BitConvert <f32, i32, SReg_32>; 1039 def : BitConvert <f32, i32, VReg_32>; 1040 1041 def : Pat < 1042 (i64 (SIvcc_bitcast VCCReg:$vcc)), 1043 (S_MOV_B64 (COPY_TO_REGCLASS VCCReg:$vcc, SReg_64)) 1044 >; 1045 1046 def : Pat < 1047 (i1 (SIvcc_bitcast SReg_64:$vcc)), 1048 (COPY_TO_REGCLASS SReg_64:$vcc, VCCReg) 1049 >; 1050 1051 /********** ===================== **********/ 1052 /********** Interpolation Paterns **********/ 1053 /********** ===================== **********/ 1054 1055 def : Pat < 1056 (int_SI_fs_interp_linear_center imm:$attr_chan, imm:$attr, SReg_32:$params), 1057 (SI_INTERP (f32 LINEAR_CENTER_I), (f32 LINEAR_CENTER_J), imm:$attr_chan, 1058 imm:$attr, SReg_32:$params) 1059 >; 1060 1061 def : Pat < 1062 (int_SI_fs_interp_linear_centroid imm:$attr_chan, imm:$attr, SReg_32:$params), 1063 (SI_INTERP (f32 LINEAR_CENTROID_I), (f32 LINEAR_CENTROID_J), imm:$attr_chan, 1064 imm:$attr, SReg_32:$params) 1065 >; 1066 1067 def : Pat < 1068 (int_SI_fs_interp_persp_center imm:$attr_chan, imm:$attr, SReg_32:$params), 1069 (SI_INTERP (f32 PERSP_CENTER_I), (f32 PERSP_CENTER_J), imm:$attr_chan, 1070 imm:$attr, SReg_32:$params) 1071 >; 1072 1073 def : Pat < 1074 (int_SI_fs_interp_persp_centroid imm:$attr_chan, imm:$attr, SReg_32:$params), 1075 (SI_INTERP (f32 PERSP_CENTROID_I), (f32 PERSP_CENTROID_J), imm:$attr_chan, 1076 imm:$attr, SReg_32:$params) 1077 >; 1078 1079 /********** ================== **********/ 1080 /********** Intrinsic Patterns **********/ 1081 /********** ================== **********/ 1082 1083 /* llvm.AMDGPU.pow */ 1084 /* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct? */ 1085 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_F32_e32, VReg_32>; 1086 1087 def : Pat < 1088 (int_AMDGPU_div AllReg_32:$src0, AllReg_32:$src1), 1089 (V_MUL_LEGACY_F32_e32 AllReg_32:$src0, (V_RCP_LEGACY_F32_e32 AllReg_32:$src1)) 1090 >; 1091 1092 /********** ================== **********/ 1093 /********** VOP3 Patterns **********/ 1094 /********** ================== **********/ 1095 1096 def : Pat <(f32 (IL_mad AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2)), 1097 (V_MAD_LEGACY_F32 AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2, 1098 0, 0, 0, 0)>; 1099 1100 } // End isSI predicate 1101
