1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "main/macros.h" 25 #include "intel_batchbuffer.h" 26 #include "brw_context.h" 27 #include "brw_state.h" 28 #include "brw_defines.h" 29 30 /** 31 * The following diagram shows how we partition the URB: 32 * 33 * 8kB 8kB Rest of the URB space 34 * ____-____ ____-____ _________________-_________________ 35 * / \ / \ / \ 36 * +-------------------------------------------------------------+ 37 * | VS Push | FS Push | VS | 38 * | Constants | Constants | Handles | 39 * +-------------------------------------------------------------+ 40 * 41 * Notably, push constants must be stored at the beginning of the URB 42 * space, while entries can be stored anywhere. Ivybridge has a maximum 43 * constant buffer size of 16kB. 44 * 45 * Currently we split the constant buffer space evenly between VS and FS. 46 * This is probably not ideal, but simple. 47 * 48 * Ivybridge GT1 has 128kB of URB space. 49 * Ivybridge GT2 has 256kB of URB space. 50 * 51 * See "Volume 2a: 3D Pipeline," section 1.8. 52 */ 53 void 54 gen7_allocate_push_constants(struct brw_context *brw) 55 { 56 struct intel_context *intel = &brw->intel; 57 BEGIN_BATCH(2); 58 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2)); 59 OUT_BATCH(8); 60 ADVANCE_BATCH(); 61 62 BEGIN_BATCH(2); 63 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2)); 64 OUT_BATCH(8 | 8 << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); 65 ADVANCE_BATCH(); 66 } 67 68 const struct brw_tracked_state gen7_push_constant_alloc = { 69 .dirty = { 70 .mesa = 0, 71 .brw = BRW_NEW_CONTEXT, 72 .cache = 0, 73 }, 74 .emit = gen7_allocate_push_constants, 75 }; 76 77 static void 78 gen7_upload_urb(struct brw_context *brw) 79 { 80 struct intel_context *intel = &brw->intel; 81 /* Total space for entries is URB size - 16kB for push constants */ 82 int handle_region_size = (brw->urb.size - 16) * 1024; /* bytes */ 83 84 /* CACHE_NEW_VS_PROG */ 85 brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1); 86 87 int nr_vs_entries = handle_region_size / (brw->urb.vs_size * 64); 88 if (nr_vs_entries > brw->urb.max_vs_entries) 89 nr_vs_entries = brw->urb.max_vs_entries; 90 91 /* According to volume 2a, nr_vs_entries must be a multiple of 8. */ 92 brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 8); 93 94 /* URB Starting Addresses are specified in multiples of 8kB. */ 95 brw->urb.vs_start = 2; /* skip over push constants */ 96 97 assert(brw->urb.nr_vs_entries % 8 == 0); 98 assert(brw->urb.nr_gs_entries % 8 == 0); 99 /* GS requirement */ 100 assert(!brw->gs.prog_active); 101 102 gen7_emit_vs_workaround_flush(intel); 103 gen7_emit_urb_state(brw, brw->urb.nr_vs_entries, brw->urb.vs_size, 104 brw->urb.vs_start); 105 } 106 107 void 108 gen7_emit_urb_state(struct brw_context *brw, GLuint nr_vs_entries, 109 GLuint vs_size, GLuint vs_start) 110 { 111 struct intel_context *intel = &brw->intel; 112 113 BEGIN_BATCH(2); 114 OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2)); 115 OUT_BATCH(nr_vs_entries | 116 ((vs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) | 117 (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); 118 ADVANCE_BATCH(); 119 120 /* Allocate the GS, HS, and DS zero space - we don't use them. */ 121 BEGIN_BATCH(2); 122 OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2)); 123 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | 124 (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); 125 ADVANCE_BATCH(); 126 127 BEGIN_BATCH(2); 128 OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2)); 129 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | 130 (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); 131 ADVANCE_BATCH(); 132 133 BEGIN_BATCH(2); 134 OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2)); 135 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | 136 (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); 137 ADVANCE_BATCH(); 138 } 139 140 const struct brw_tracked_state gen7_urb = { 141 .dirty = { 142 .mesa = 0, 143 .brw = BRW_NEW_CONTEXT, 144 .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG), 145 }, 146 .emit = gen7_upload_urb, 147 }; 148
