1 #ifndef __MSMB_ISP__ 2 #define __MSMB_ISP__ 3 4 #include <linux/videodev2.h> 5 6 #define MAX_PLANES_PER_STREAM 3 7 #define MAX_NUM_STREAM 7 8 9 #define ISP_VERSION_40 40 10 #define ISP_VERSION_32 32 11 #define ISP_NATIVE_BUF_BIT (0x10000 << 0) 12 #define ISP0_BIT (0x10000 << 1) 13 #define ISP1_BIT (0x10000 << 2) 14 #define ISP_META_CHANNEL_BIT (0x10000 << 3) 15 #define ISP_SCRATCH_BUF_BIT (0x10000 << 4) 16 #define ISP_STATS_STREAM_BIT 0x80000000 17 18 enum ISP_START_PIXEL_PATTERN { 19 ISP_BAYER_RGRGRG, 20 ISP_BAYER_GRGRGR, 21 ISP_BAYER_BGBGBG, 22 ISP_BAYER_GBGBGB, 23 ISP_YUV_YCbYCr, 24 ISP_YUV_YCrYCb, 25 ISP_YUV_CbYCrY, 26 ISP_YUV_CrYCbY, 27 ISP_PIX_PATTERN_MAX 28 }; 29 30 enum msm_vfe_plane_fmt { 31 Y_PLANE, 32 CB_PLANE, 33 CR_PLANE, 34 CRCB_PLANE, 35 CBCR_PLANE, 36 VFE_PLANE_FMT_MAX 37 }; 38 39 enum msm_vfe_input_src { 40 VFE_PIX_0, 41 VFE_RAW_0, 42 VFE_RAW_1, 43 VFE_RAW_2, 44 VFE_SRC_MAX, 45 }; 46 47 enum msm_vfe_axi_stream_src { 48 PIX_ENCODER, 49 PIX_VIEWFINDER, 50 CAMIF_RAW, 51 IDEAL_RAW, 52 RDI_INTF_0, 53 RDI_INTF_1, 54 RDI_INTF_2, 55 VFE_AXI_SRC_MAX 56 }; 57 58 enum msm_vfe_frame_skip_pattern { 59 NO_SKIP, 60 EVERY_2FRAME, 61 EVERY_3FRAME, 62 EVERY_4FRAME, 63 EVERY_5FRAME, 64 EVERY_6FRAME, 65 EVERY_7FRAME, 66 EVERY_8FRAME, 67 EVERY_16FRAME, 68 EVERY_32FRAME, 69 SKIP_ALL, 70 MAX_SKIP, 71 }; 72 73 enum msm_vfe_camif_input { 74 CAMIF_DISABLED, 75 CAMIF_PAD_REG_INPUT, 76 CAMIF_MIDDI_INPUT, 77 CAMIF_MIPI_INPUT, 78 }; 79 80 struct msm_vfe_camif_cfg { 81 uint32_t lines_per_frame; 82 uint32_t pixels_per_line; 83 uint32_t first_pixel; 84 uint32_t last_pixel; 85 uint32_t first_line; 86 uint32_t last_line; 87 uint32_t epoch_line0; 88 uint32_t epoch_line1; 89 enum msm_vfe_camif_input camif_input; 90 }; 91 92 enum msm_vfe_inputmux { 93 CAMIF, 94 TESTGEN, 95 EXTERNAL_READ, 96 }; 97 98 struct msm_vfe_pix_cfg { 99 struct msm_vfe_camif_cfg camif_cfg; 100 enum msm_vfe_inputmux input_mux; 101 enum ISP_START_PIXEL_PATTERN pixel_pattern; 102 }; 103 104 struct msm_vfe_rdi_cfg { 105 uint8_t cid; 106 uint8_t frame_based; 107 }; 108 109 struct msm_vfe_input_cfg { 110 union { 111 struct msm_vfe_pix_cfg pix_cfg; 112 struct msm_vfe_rdi_cfg rdi_cfg; 113 } d; 114 enum msm_vfe_input_src input_src; 115 uint32_t input_pix_clk; 116 }; 117 118 struct msm_vfe_axi_plane_cfg { 119 uint32_t output_width; /*Include padding*/ 120 uint32_t output_height; 121 uint32_t output_stride; 122 uint32_t output_scan_lines; 123 uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/ 124 uint32_t plane_addr_offset; 125 uint8_t csid_src; /*RDI 0-2*/ 126 uint8_t rdi_cid;/*CID 1-16*/ 127 }; 128 129 struct msm_vfe_axi_stream_request_cmd { 130 uint32_t session_id; 131 uint32_t stream_id; 132 uint32_t output_format;/*Planar/RAW/Misc*/ 133 enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/ 134 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 135 136 uint32_t burst_count; 137 uint32_t hfr_mode; 138 uint8_t frame_base; 139 140 uint32_t init_frame_drop; /*MAX 31 Frames*/ 141 enum msm_vfe_frame_skip_pattern frame_skip_pattern; 142 uint8_t buf_divert; /* if TRUE no vb2 buf done. */ 143 /*Return values*/ 144 uint32_t axi_stream_handle; 145 }; 146 147 struct msm_vfe_axi_stream_release_cmd { 148 uint32_t stream_handle; 149 }; 150 151 enum msm_vfe_axi_stream_cmd { 152 STOP_STREAM, 153 START_STREAM, 154 }; 155 156 struct msm_vfe_axi_stream_cfg_cmd { 157 uint8_t num_streams; 158 uint32_t stream_handle[MAX_NUM_STREAM]; 159 enum msm_vfe_axi_stream_cmd cmd; 160 }; 161 162 enum msm_vfe_axi_stream_update_type { 163 ENABLE_STREAM_BUF_DIVERT, 164 DISABLE_STREAM_BUF_DIVERT, 165 UPDATE_STREAM_FRAMEDROP_PATTERN, 166 UPDATE_STREAM_REQUEST_FRAMES, 167 }; 168 169 struct msm_vfe_axi_stream_update_cmd { 170 uint32_t stream_handle; 171 enum msm_vfe_axi_stream_update_type update_type; 172 enum msm_vfe_frame_skip_pattern skip_pattern; 173 uint32_t request_frm_num; 174 }; 175 176 enum msm_isp_stats_type { 177 MSM_ISP_STATS_AEC, /* legacy based AEC */ 178 MSM_ISP_STATS_AF, /* legacy based AF */ 179 MSM_ISP_STATS_AWB, /* legacy based AWB */ 180 MSM_ISP_STATS_RS, /* legacy based RS */ 181 MSM_ISP_STATS_CS, /* legacy based CS */ 182 MSM_ISP_STATS_IHIST, /* legacy based HIST */ 183 MSM_ISP_STATS_SKIN, /* legacy based SKIN */ 184 MSM_ISP_STATS_BG, /* Bayer Grids */ 185 MSM_ISP_STATS_BF, /* Bayer Focus */ 186 MSM_ISP_STATS_BE, /* Bayer Exposure*/ 187 MSM_ISP_STATS_BHIST, /* Bayer Hist */ 188 MSM_ISP_STATS_MAX /* MAX */ 189 }; 190 191 struct msm_vfe_stats_stream_request_cmd { 192 uint32_t session_id; 193 uint32_t stream_id; 194 enum msm_isp_stats_type stats_type; 195 uint32_t composite_flag; 196 uint32_t framedrop_pattern; 197 uint32_t irq_subsample_pattern; 198 uint32_t buffer_offset; 199 uint32_t stream_handle; 200 }; 201 202 struct msm_vfe_stats_stream_release_cmd { 203 uint32_t stream_handle; 204 }; 205 struct msm_vfe_stats_stream_cfg_cmd { 206 uint8_t num_streams; 207 uint32_t stream_handle[MSM_ISP_STATS_MAX]; 208 uint8_t enable; 209 }; 210 211 enum msm_vfe_reg_cfg_type { 212 VFE_WRITE, 213 VFE_WRITE_MB, 214 VFE_READ, 215 VFE_CFG_MASK, 216 VFE_WRITE_DMI_16BIT, 217 VFE_WRITE_DMI_32BIT, 218 VFE_WRITE_DMI_64BIT, 219 VFE_READ_DMI_16BIT, 220 VFE_READ_DMI_32BIT, 221 VFE_READ_DMI_64BIT, 222 }; 223 224 struct msm_vfe_cfg_cmd2 { 225 uint16_t num_cfg; 226 uint16_t cmd_len; 227 void __user *cfg_data; 228 void __user *cfg_cmd; 229 }; 230 231 struct msm_vfe_reg_rw_info { 232 uint32_t reg_offset; 233 uint32_t cmd_data_offset; 234 uint32_t len; 235 }; 236 237 struct msm_vfe_reg_mask_info { 238 uint32_t reg_offset; 239 uint32_t mask; 240 uint32_t val; 241 }; 242 243 struct msm_vfe_reg_dmi_info { 244 uint32_t hi_tbl_offset; /*Optional*/ 245 uint32_t lo_tbl_offset; /*Required*/ 246 uint32_t len; 247 }; 248 249 struct msm_vfe_reg_cfg_cmd { 250 union { 251 struct msm_vfe_reg_rw_info rw_info; 252 struct msm_vfe_reg_mask_info mask_info; 253 struct msm_vfe_reg_dmi_info dmi_info; 254 } u; 255 256 enum msm_vfe_reg_cfg_type cmd_type; 257 }; 258 259 enum msm_isp_buf_type { 260 ISP_PRIVATE_BUF, 261 ISP_SHARE_BUF, 262 MAX_ISP_BUF_TYPE, 263 }; 264 265 struct msm_isp_buf_request { 266 uint32_t session_id; 267 uint32_t stream_id; 268 uint8_t num_buf; 269 uint32_t handle; 270 enum msm_isp_buf_type buf_type; 271 }; 272 273 struct msm_isp_qbuf_info { 274 uint32_t handle; 275 int buf_idx; 276 /*Only used for prepare buffer*/ 277 struct v4l2_buffer buffer; 278 /*Only used for diverted buffer*/ 279 uint32_t dirty_buf; 280 }; 281 282 struct msm_vfe_axi_src_state { 283 enum msm_vfe_input_src input_src; 284 uint32_t src_active; 285 }; 286 287 enum msm_isp_event_idx { 288 ISP_REG_UPDATE = 0, 289 ISP_START_ACK = 1, 290 ISP_STOP_ACK = 2, 291 ISP_IRQ_VIOLATION = 3, 292 ISP_WM_BUS_OVERFLOW = 4, 293 ISP_STATS_OVERFLOW = 5, 294 ISP_CAMIF_ERROR = 6, 295 ISP_SOF = 7, 296 ISP_EOF = 8, 297 ISP_EVENT_MAX = 9 298 }; 299 300 #define ISP_EVENT_OFFSET 8 301 #define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) 302 #define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) 303 #define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) 304 #define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) 305 #define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) 306 #define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) 307 #define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) 308 #define ISP_EVENT_WM_BUS_OVERFLOW (ISP_EVENT_BASE + ISP_WM_BUS_OVERFLOW) 309 #define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) 310 #define ISP_EVENT_CAMIF_ERROR (ISP_EVENT_BASE + ISP_CAMIF_ERROR) 311 #define ISP_EVENT_SOF (ISP_EVENT_BASE + ISP_SOF) 312 #define ISP_EVENT_EOF (ISP_EVENT_BASE + ISP_EOF) 313 #define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) 314 #define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) 315 #define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) 316 /* The msm_v4l2_event_data structure should match the 317 * v4l2_event.u.data field. 318 * should not exceed 64 bytes */ 319 320 struct msm_isp_buf_event { 321 uint32_t session_id; 322 uint32_t stream_id; 323 uint32_t handle; 324 int8_t buf_idx; 325 }; 326 struct msm_isp_stats_event { 327 uint32_t stats_mask; /* 4 bytes */ 328 uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */ 329 }; 330 331 struct msm_isp_stream_ack { 332 uint32_t session_id; 333 uint32_t stream_id; 334 uint32_t handle; 335 }; 336 337 struct msm_isp_event_data { 338 /*Wall clock except for buffer divert events 339 *which use monotonic clock 340 */ 341 struct timeval timestamp; 342 /* Monotonic timestamp since bootup */ 343 struct timeval mono_timestamp; 344 /* if pix is a src frame_id is from camif */ 345 uint32_t frame_id; 346 union { 347 /* START_ACK, STOP_ACK */ 348 struct msm_isp_stream_ack stream_ack; 349 /* REG_UPDATE_TRIGGER, bus over flow */ 350 enum msm_vfe_input_src input_src; 351 /* stats notify */ 352 struct msm_isp_stats_event stats; 353 /* IRQ_VIOLATION, STATS_OVER_FLOW, WM_OVER_FLOW */ 354 uint32_t irq_status_mask; 355 struct msm_isp_buf_event buf_done; 356 } u; /* union can have max 52 bytes */ 357 }; 358 359 #define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') 360 #define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') 361 #define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') 362 #define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') 363 #define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') 364 #define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') 365 #define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') 366 #define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') 367 #define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') 368 #define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') 369 #define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') 370 #define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') 371 372 #define VIDIOC_MSM_VFE_REG_CFG \ 373 _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2) 374 375 #define VIDIOC_MSM_ISP_REQUEST_BUF \ 376 _IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request) 377 378 #define VIDIOC_MSM_ISP_ENQUEUE_BUF \ 379 _IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info) 380 381 #define VIDIOC_MSM_ISP_RELEASE_BUF \ 382 _IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request) 383 384 #define VIDIOC_MSM_ISP_REQUEST_STREAM \ 385 _IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd) 386 387 #define VIDIOC_MSM_ISP_CFG_STREAM \ 388 _IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd) 389 390 #define VIDIOC_MSM_ISP_RELEASE_STREAM \ 391 _IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd) 392 393 #define VIDIOC_MSM_ISP_INPUT_CFG \ 394 _IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg) 395 396 #define VIDIOC_MSM_ISP_SET_SRC_STATE \ 397 _IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state) 398 399 #define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \ 400 _IOWR('V', BASE_VIDIOC_PRIVATE+9, \ 401 struct msm_vfe_stats_stream_request_cmd) 402 403 #define VIDIOC_MSM_ISP_CFG_STATS_STREAM \ 404 _IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd) 405 406 #define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \ 407 _IOWR('V', BASE_VIDIOC_PRIVATE+11, \ 408 struct msm_vfe_stats_stream_release_cmd) 409 410 #define VIDIOC_MSM_ISP_UPDATE_STREAM \ 411 _IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd) 412 413 #endif /* __MSMB_ISP__ */ 414
