1 #ifndef _UAPI_MSM_VIDC_DEC_H_ 2 #define _UAPI_MSM_VIDC_DEC_H_ 3 4 #include <linux/types.h> 5 #include <linux/ioctl.h> 6 7 /* STATUS CODES */ 8 /* Base value for status codes */ 9 #define VDEC_S_BASE 0x40000000 10 /* Success */ 11 #define VDEC_S_SUCCESS (VDEC_S_BASE) 12 /* General failure */ 13 #define VDEC_S_EFAIL (VDEC_S_BASE + 1) 14 /* Fatal irrecoverable failure. Need to tear down session. */ 15 #define VDEC_S_EFATAL (VDEC_S_BASE + 2) 16 /* Error detected in the passed parameters */ 17 #define VDEC_S_EBADPARAM (VDEC_S_BASE + 3) 18 /* Command called in invalid state. */ 19 #define VDEC_S_EINVALSTATE (VDEC_S_BASE + 4) 20 /* Insufficient OS resources - thread, memory etc. */ 21 #define VDEC_S_ENOSWRES (VDEC_S_BASE + 5) 22 /* Insufficient HW resources - core capacity maxed out. */ 23 #define VDEC_S_ENOHWRES (VDEC_S_BASE + 6) 24 /* Invalid command called */ 25 #define VDEC_S_EINVALCMD (VDEC_S_BASE + 7) 26 /* Command timeout. */ 27 #define VDEC_S_ETIMEOUT (VDEC_S_BASE + 8) 28 /* Pre-requirement is not met for API. */ 29 #define VDEC_S_ENOPREREQ (VDEC_S_BASE + 9) 30 /* Command queue is full. */ 31 #define VDEC_S_ECMDQFULL (VDEC_S_BASE + 10) 32 /* Command is not supported by this driver */ 33 #define VDEC_S_ENOTSUPP (VDEC_S_BASE + 11) 34 /* Command is not implemented by thedriver. */ 35 #define VDEC_S_ENOTIMPL (VDEC_S_BASE + 12) 36 /* Command is not implemented by the driver. */ 37 #define VDEC_S_BUSY (VDEC_S_BASE + 13) 38 #define VDEC_S_INPUT_BITSTREAM_ERR (VDEC_S_BASE + 14) 39 40 #define VDEC_INTF_VER 1 41 #define VDEC_MSG_BASE 0x0000000 42 /* Codes to identify asynchronous message responses and events that driver 43 wants to communicate to the app.*/ 44 #define VDEC_MSG_INVALID (VDEC_MSG_BASE + 0) 45 #define VDEC_MSG_RESP_INPUT_BUFFER_DONE (VDEC_MSG_BASE + 1) 46 #define VDEC_MSG_RESP_OUTPUT_BUFFER_DONE (VDEC_MSG_BASE + 2) 47 #define VDEC_MSG_RESP_INPUT_FLUSHED (VDEC_MSG_BASE + 3) 48 #define VDEC_MSG_RESP_OUTPUT_FLUSHED (VDEC_MSG_BASE + 4) 49 #define VDEC_MSG_RESP_FLUSH_INPUT_DONE (VDEC_MSG_BASE + 5) 50 #define VDEC_MSG_RESP_FLUSH_OUTPUT_DONE (VDEC_MSG_BASE + 6) 51 #define VDEC_MSG_RESP_START_DONE (VDEC_MSG_BASE + 7) 52 #define VDEC_MSG_RESP_STOP_DONE (VDEC_MSG_BASE + 8) 53 #define VDEC_MSG_RESP_PAUSE_DONE (VDEC_MSG_BASE + 9) 54 #define VDEC_MSG_RESP_RESUME_DONE (VDEC_MSG_BASE + 10) 55 #define VDEC_MSG_RESP_RESOURCE_LOADED (VDEC_MSG_BASE + 11) 56 #define VDEC_EVT_RESOURCES_LOST (VDEC_MSG_BASE + 12) 57 #define VDEC_MSG_EVT_CONFIG_CHANGED (VDEC_MSG_BASE + 13) 58 #define VDEC_MSG_EVT_HW_ERROR (VDEC_MSG_BASE + 14) 59 #define VDEC_MSG_EVT_INFO_CONFIG_CHANGED (VDEC_MSG_BASE + 15) 60 #define VDEC_MSG_EVT_INFO_FIELD_DROPPED (VDEC_MSG_BASE + 16) 61 #define VDEC_MSG_EVT_HW_OVERLOAD (VDEC_MSG_BASE + 17) 62 #define VDEC_MSG_EVT_MAX_CLIENTS (VDEC_MSG_BASE + 18) 63 64 /*Buffer flags bits masks.*/ 65 #define VDEC_BUFFERFLAG_EOS 0x00000001 66 #define VDEC_BUFFERFLAG_DECODEONLY 0x00000004 67 #define VDEC_BUFFERFLAG_DATACORRUPT 0x00000008 68 #define VDEC_BUFFERFLAG_ENDOFFRAME 0x00000010 69 #define VDEC_BUFFERFLAG_SYNCFRAME 0x00000020 70 #define VDEC_BUFFERFLAG_EXTRADATA 0x00000040 71 #define VDEC_BUFFERFLAG_CODECCONFIG 0x00000080 72 73 /*Post processing flags bit masks*/ 74 #define VDEC_EXTRADATA_NONE 0x001 75 #define VDEC_EXTRADATA_QP 0x004 76 #define VDEC_EXTRADATA_MB_ERROR_MAP 0x008 77 #define VDEC_EXTRADATA_SEI 0x010 78 #define VDEC_EXTRADATA_VUI 0x020 79 #define VDEC_EXTRADATA_VC1 0x040 80 81 #define VDEC_EXTRADATA_EXT_DATA 0x0800 82 #define VDEC_EXTRADATA_USER_DATA 0x1000 83 #define VDEC_EXTRADATA_EXT_BUFFER 0x2000 84 85 #define VDEC_CMDBASE 0x800 86 #define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE) 87 88 #define VDEC_IOCTL_MAGIC 'v' 89 90 struct vdec_ioctl_msg { 91 void __user *in; 92 void __user *out; 93 }; 94 95 /* CMD params: InputParam:enum vdec_codec 96 OutputParam: struct vdec_profile_level*/ 97 #define VDEC_IOCTL_GET_PROFILE_LEVEL_SUPPORTED \ 98 _IOWR(VDEC_IOCTL_MAGIC, 0, struct vdec_ioctl_msg) 99 100 /*CMD params:InputParam: NULL 101 OutputParam: uint32_t(bitmask)*/ 102 #define VDEC_IOCTL_GET_INTERLACE_FORMAT \ 103 _IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg) 104 105 /* CMD params: InputParam: enum vdec_codec 106 OutputParam: struct vdec_profile_level*/ 107 #define VDEC_IOCTL_GET_CURRENT_PROFILE_LEVEL \ 108 _IOWR(VDEC_IOCTL_MAGIC, 2, struct vdec_ioctl_msg) 109 110 /*CMD params: SET: InputParam: enum vdec_output_fromat OutputParam: NULL 111 GET: InputParam: NULL OutputParam: enum vdec_output_fromat*/ 112 #define VDEC_IOCTL_SET_OUTPUT_FORMAT \ 113 _IOWR(VDEC_IOCTL_MAGIC, 3, struct vdec_ioctl_msg) 114 #define VDEC_IOCTL_GET_OUTPUT_FORMAT \ 115 _IOWR(VDEC_IOCTL_MAGIC, 4, struct vdec_ioctl_msg) 116 117 /*CMD params: SET: InputParam: enum vdec_codec OutputParam: NULL 118 GET: InputParam: NULL OutputParam: enum vdec_codec*/ 119 #define VDEC_IOCTL_SET_CODEC \ 120 _IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg) 121 #define VDEC_IOCTL_GET_CODEC \ 122 _IOR(VDEC_IOCTL_MAGIC, 6, struct vdec_ioctl_msg) 123 124 /*CMD params: SET: InputParam: struct vdec_picsize outputparam: NULL 125 GET: InputParam: NULL outputparam: struct vdec_picsize*/ 126 #define VDEC_IOCTL_SET_PICRES \ 127 _IOW(VDEC_IOCTL_MAGIC, 7, struct vdec_ioctl_msg) 128 #define VDEC_IOCTL_GET_PICRES \ 129 _IOR(VDEC_IOCTL_MAGIC, 8, struct vdec_ioctl_msg) 130 131 #define VDEC_IOCTL_SET_EXTRADATA \ 132 _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg) 133 #define VDEC_IOCTL_GET_EXTRADATA \ 134 _IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_ioctl_msg) 135 136 #define VDEC_IOCTL_SET_SEQUENCE_HEADER \ 137 _IOW(VDEC_IOCTL_MAGIC, 11, struct vdec_ioctl_msg) 138 139 /* CMD params: SET: InputParam - vdec_allocatorproperty, OutputParam - NULL 140 GET: InputParam - NULL, OutputParam - vdec_allocatorproperty*/ 141 #define VDEC_IOCTL_SET_BUFFER_REQ \ 142 _IOW(VDEC_IOCTL_MAGIC, 12, struct vdec_ioctl_msg) 143 #define VDEC_IOCTL_GET_BUFFER_REQ \ 144 _IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg) 145 /* CMD params: InputParam - vdec_buffer, OutputParam - uint8_t** */ 146 #define VDEC_IOCTL_ALLOCATE_BUFFER \ 147 _IOWR(VDEC_IOCTL_MAGIC, 14, struct vdec_ioctl_msg) 148 /* CMD params: InputParam - uint8_t *, OutputParam - NULL.*/ 149 #define VDEC_IOCTL_FREE_BUFFER \ 150 _IOW(VDEC_IOCTL_MAGIC, 15, struct vdec_ioctl_msg) 151 152 /*CMD params: CMD: InputParam - struct vdec_setbuffer_cmd, OutputParam - NULL*/ 153 #define VDEC_IOCTL_SET_BUFFER \ 154 _IOW(VDEC_IOCTL_MAGIC, 16, struct vdec_ioctl_msg) 155 156 /* CMD params: InputParam - struct vdec_fillbuffer_cmd, OutputParam - NULL*/ 157 #define VDEC_IOCTL_FILL_OUTPUT_BUFFER \ 158 _IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg) 159 160 /*CMD params: InputParam - struct vdec_frameinfo , OutputParam - NULL*/ 161 #define VDEC_IOCTL_DECODE_FRAME \ 162 _IOW(VDEC_IOCTL_MAGIC, 18, struct vdec_ioctl_msg) 163 164 #define VDEC_IOCTL_LOAD_RESOURCES _IO(VDEC_IOCTL_MAGIC, 19) 165 #define VDEC_IOCTL_CMD_START _IO(VDEC_IOCTL_MAGIC, 20) 166 #define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21) 167 #define VDEC_IOCTL_CMD_PAUSE _IO(VDEC_IOCTL_MAGIC, 22) 168 #define VDEC_IOCTL_CMD_RESUME _IO(VDEC_IOCTL_MAGIC, 23) 169 170 /*CMD params: InputParam - enum vdec_bufferflush , OutputParam - NULL */ 171 #define VDEC_IOCTL_CMD_FLUSH _IOW(VDEC_IOCTL_MAGIC, 24, struct vdec_ioctl_msg) 172 173 /* ======================================================== 174 * IOCTL for getting asynchronous notification from driver 175 * ========================================================*/ 176 177 /*IOCTL params: InputParam - NULL, OutputParam - struct vdec_msginfo*/ 178 #define VDEC_IOCTL_GET_NEXT_MSG \ 179 _IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg) 180 181 #define VDEC_IOCTL_STOP_NEXT_MSG _IO(VDEC_IOCTL_MAGIC, 26) 182 183 #define VDEC_IOCTL_GET_NUMBER_INSTANCES \ 184 _IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg) 185 186 #define VDEC_IOCTL_SET_PICTURE_ORDER \ 187 _IOW(VDEC_IOCTL_MAGIC, 28, struct vdec_ioctl_msg) 188 189 #define VDEC_IOCTL_SET_FRAME_RATE \ 190 _IOW(VDEC_IOCTL_MAGIC, 29, struct vdec_ioctl_msg) 191 192 #define VDEC_IOCTL_SET_H264_MV_BUFFER \ 193 _IOW(VDEC_IOCTL_MAGIC, 30, struct vdec_ioctl_msg) 194 195 #define VDEC_IOCTL_FREE_H264_MV_BUFFER \ 196 _IOW(VDEC_IOCTL_MAGIC, 31, struct vdec_ioctl_msg) 197 198 #define VDEC_IOCTL_GET_MV_BUFFER_SIZE \ 199 _IOR(VDEC_IOCTL_MAGIC, 32, struct vdec_ioctl_msg) 200 201 #define VDEC_IOCTL_SET_IDR_ONLY_DECODING \ 202 _IO(VDEC_IOCTL_MAGIC, 33) 203 204 #define VDEC_IOCTL_SET_CONT_ON_RECONFIG \ 205 _IO(VDEC_IOCTL_MAGIC, 34) 206 207 #define VDEC_IOCTL_SET_DISABLE_DMX \ 208 _IOW(VDEC_IOCTL_MAGIC, 35, struct vdec_ioctl_msg) 209 210 #define VDEC_IOCTL_GET_DISABLE_DMX \ 211 _IOR(VDEC_IOCTL_MAGIC, 36, struct vdec_ioctl_msg) 212 213 #define VDEC_IOCTL_GET_DISABLE_DMX_SUPPORT \ 214 _IOR(VDEC_IOCTL_MAGIC, 37, struct vdec_ioctl_msg) 215 216 #define VDEC_IOCTL_SET_PERF_CLK \ 217 _IOR(VDEC_IOCTL_MAGIC, 38, struct vdec_ioctl_msg) 218 219 #define VDEC_IOCTL_SET_META_BUFFERS \ 220 _IOW(VDEC_IOCTL_MAGIC, 39, struct vdec_ioctl_msg) 221 222 #define VDEC_IOCTL_FREE_META_BUFFERS \ 223 _IO(VDEC_IOCTL_MAGIC, 40) 224 225 enum vdec_picture { 226 PICTURE_TYPE_I, 227 PICTURE_TYPE_P, 228 PICTURE_TYPE_B, 229 PICTURE_TYPE_BI, 230 PICTURE_TYPE_SKIP, 231 PICTURE_TYPE_IDR, 232 PICTURE_TYPE_UNKNOWN 233 }; 234 235 enum vdec_buffer { 236 VDEC_BUFFER_TYPE_INPUT, 237 VDEC_BUFFER_TYPE_OUTPUT 238 }; 239 240 struct vdec_allocatorproperty { 241 enum vdec_buffer buffer_type; 242 uint32_t mincount; 243 uint32_t maxcount; 244 uint32_t actualcount; 245 size_t buffer_size; 246 uint32_t alignment; 247 uint32_t buf_poolid; 248 size_t meta_buffer_size; 249 }; 250 251 struct vdec_bufferpayload { 252 void __user *bufferaddr; 253 size_t buffer_len; 254 int pmem_fd; 255 size_t offset; 256 size_t mmaped_size; 257 }; 258 259 struct vdec_setbuffer_cmd { 260 enum vdec_buffer buffer_type; 261 struct vdec_bufferpayload buffer; 262 }; 263 264 struct vdec_fillbuffer_cmd { 265 struct vdec_bufferpayload buffer; 266 void *client_data; 267 }; 268 269 enum vdec_bufferflush { 270 VDEC_FLUSH_TYPE_INPUT, 271 VDEC_FLUSH_TYPE_OUTPUT, 272 VDEC_FLUSH_TYPE_ALL 273 }; 274 275 enum vdec_codec { 276 VDEC_CODECTYPE_H264 = 0x1, 277 VDEC_CODECTYPE_H263 = 0x2, 278 VDEC_CODECTYPE_MPEG4 = 0x3, 279 VDEC_CODECTYPE_DIVX_3 = 0x4, 280 VDEC_CODECTYPE_DIVX_4 = 0x5, 281 VDEC_CODECTYPE_DIVX_5 = 0x6, 282 VDEC_CODECTYPE_DIVX_6 = 0x7, 283 VDEC_CODECTYPE_XVID = 0x8, 284 VDEC_CODECTYPE_MPEG1 = 0x9, 285 VDEC_CODECTYPE_MPEG2 = 0xa, 286 VDEC_CODECTYPE_VC1 = 0xb, 287 VDEC_CODECTYPE_VC1_RCV = 0xc, 288 VDEC_CODECTYPE_HEVC = 0xd, 289 VDEC_CODECTYPE_MVC = 0xe, 290 }; 291 292 enum vdec_mpeg2_profile { 293 VDEC_MPEG2ProfileSimple = 0x1, 294 VDEC_MPEG2ProfileMain = 0x2, 295 VDEC_MPEG2Profile422 = 0x4, 296 VDEC_MPEG2ProfileSNR = 0x8, 297 VDEC_MPEG2ProfileSpatial = 0x10, 298 VDEC_MPEG2ProfileHigh = 0x20, 299 VDEC_MPEG2ProfileKhronosExtensions = 0x6F000000, 300 VDEC_MPEG2ProfileVendorStartUnused = 0x7F000000, 301 VDEC_MPEG2ProfileMax = 0x7FFFFFFF 302 }; 303 304 enum vdec_mpeg2_level { 305 306 VDEC_MPEG2LevelLL = 0x1, 307 VDEC_MPEG2LevelML = 0x2, 308 VDEC_MPEG2LevelH14 = 0x4, 309 VDEC_MPEG2LevelHL = 0x8, 310 VDEC_MPEG2LevelKhronosExtensions = 0x6F000000, 311 VDEC_MPEG2LevelVendorStartUnused = 0x7F000000, 312 VDEC_MPEG2LevelMax = 0x7FFFFFFF 313 }; 314 315 enum vdec_mpeg4_profile { 316 VDEC_MPEG4ProfileSimple = 0x01, 317 VDEC_MPEG4ProfileSimpleScalable = 0x02, 318 VDEC_MPEG4ProfileCore = 0x04, 319 VDEC_MPEG4ProfileMain = 0x08, 320 VDEC_MPEG4ProfileNbit = 0x10, 321 VDEC_MPEG4ProfileScalableTexture = 0x20, 322 VDEC_MPEG4ProfileSimpleFace = 0x40, 323 VDEC_MPEG4ProfileSimpleFBA = 0x80, 324 VDEC_MPEG4ProfileBasicAnimated = 0x100, 325 VDEC_MPEG4ProfileHybrid = 0x200, 326 VDEC_MPEG4ProfileAdvancedRealTime = 0x400, 327 VDEC_MPEG4ProfileCoreScalable = 0x800, 328 VDEC_MPEG4ProfileAdvancedCoding = 0x1000, 329 VDEC_MPEG4ProfileAdvancedCore = 0x2000, 330 VDEC_MPEG4ProfileAdvancedScalable = 0x4000, 331 VDEC_MPEG4ProfileAdvancedSimple = 0x8000, 332 VDEC_MPEG4ProfileKhronosExtensions = 0x6F000000, 333 VDEC_MPEG4ProfileVendorStartUnused = 0x7F000000, 334 VDEC_MPEG4ProfileMax = 0x7FFFFFFF 335 }; 336 337 enum vdec_mpeg4_level { 338 VDEC_MPEG4Level0 = 0x01, 339 VDEC_MPEG4Level0b = 0x02, 340 VDEC_MPEG4Level1 = 0x04, 341 VDEC_MPEG4Level2 = 0x08, 342 VDEC_MPEG4Level3 = 0x10, 343 VDEC_MPEG4Level4 = 0x20, 344 VDEC_MPEG4Level4a = 0x40, 345 VDEC_MPEG4Level5 = 0x80, 346 VDEC_MPEG4LevelKhronosExtensions = 0x6F000000, 347 VDEC_MPEG4LevelVendorStartUnused = 0x7F000000, 348 VDEC_MPEG4LevelMax = 0x7FFFFFFF 349 }; 350 351 enum vdec_avc_profile { 352 VDEC_AVCProfileBaseline = 0x01, 353 VDEC_AVCProfileMain = 0x02, 354 VDEC_AVCProfileExtended = 0x04, 355 VDEC_AVCProfileHigh = 0x08, 356 VDEC_AVCProfileHigh10 = 0x10, 357 VDEC_AVCProfileHigh422 = 0x20, 358 VDEC_AVCProfileHigh444 = 0x40, 359 VDEC_AVCProfileKhronosExtensions = 0x6F000000, 360 VDEC_AVCProfileVendorStartUnused = 0x7F000000, 361 VDEC_AVCProfileMax = 0x7FFFFFFF 362 }; 363 364 enum vdec_avc_level { 365 VDEC_AVCLevel1 = 0x01, 366 VDEC_AVCLevel1b = 0x02, 367 VDEC_AVCLevel11 = 0x04, 368 VDEC_AVCLevel12 = 0x08, 369 VDEC_AVCLevel13 = 0x10, 370 VDEC_AVCLevel2 = 0x20, 371 VDEC_AVCLevel21 = 0x40, 372 VDEC_AVCLevel22 = 0x80, 373 VDEC_AVCLevel3 = 0x100, 374 VDEC_AVCLevel31 = 0x200, 375 VDEC_AVCLevel32 = 0x400, 376 VDEC_AVCLevel4 = 0x800, 377 VDEC_AVCLevel41 = 0x1000, 378 VDEC_AVCLevel42 = 0x2000, 379 VDEC_AVCLevel5 = 0x4000, 380 VDEC_AVCLevel51 = 0x8000, 381 VDEC_AVCLevelKhronosExtensions = 0x6F000000, 382 VDEC_AVCLevelVendorStartUnused = 0x7F000000, 383 VDEC_AVCLevelMax = 0x7FFFFFFF 384 }; 385 386 enum vdec_divx_profile { 387 VDEC_DIVXProfile_qMobile = 0x01, 388 VDEC_DIVXProfile_Mobile = 0x02, 389 VDEC_DIVXProfile_HD = 0x04, 390 VDEC_DIVXProfile_Handheld = 0x08, 391 VDEC_DIVXProfile_Portable = 0x10, 392 VDEC_DIVXProfile_HomeTheater = 0x20 393 }; 394 395 enum vdec_xvid_profile { 396 VDEC_XVIDProfile_Simple = 0x1, 397 VDEC_XVIDProfile_Advanced_Realtime_Simple = 0x2, 398 VDEC_XVIDProfile_Advanced_Simple = 0x4 399 }; 400 401 enum vdec_xvid_level { 402 VDEC_XVID_LEVEL_S_L0 = 0x1, 403 VDEC_XVID_LEVEL_S_L1 = 0x2, 404 VDEC_XVID_LEVEL_S_L2 = 0x4, 405 VDEC_XVID_LEVEL_S_L3 = 0x8, 406 VDEC_XVID_LEVEL_ARTS_L1 = 0x10, 407 VDEC_XVID_LEVEL_ARTS_L2 = 0x20, 408 VDEC_XVID_LEVEL_ARTS_L3 = 0x40, 409 VDEC_XVID_LEVEL_ARTS_L4 = 0x80, 410 VDEC_XVID_LEVEL_AS_L0 = 0x100, 411 VDEC_XVID_LEVEL_AS_L1 = 0x200, 412 VDEC_XVID_LEVEL_AS_L2 = 0x400, 413 VDEC_XVID_LEVEL_AS_L3 = 0x800, 414 VDEC_XVID_LEVEL_AS_L4 = 0x1000 415 }; 416 417 enum vdec_h263profile { 418 VDEC_H263ProfileBaseline = 0x01, 419 VDEC_H263ProfileH320Coding = 0x02, 420 VDEC_H263ProfileBackwardCompatible = 0x04, 421 VDEC_H263ProfileISWV2 = 0x08, 422 VDEC_H263ProfileISWV3 = 0x10, 423 VDEC_H263ProfileHighCompression = 0x20, 424 VDEC_H263ProfileInternet = 0x40, 425 VDEC_H263ProfileInterlace = 0x80, 426 VDEC_H263ProfileHighLatency = 0x100, 427 VDEC_H263ProfileKhronosExtensions = 0x6F000000, 428 VDEC_H263ProfileVendorStartUnused = 0x7F000000, 429 VDEC_H263ProfileMax = 0x7FFFFFFF 430 }; 431 432 enum vdec_h263level { 433 VDEC_H263Level10 = 0x01, 434 VDEC_H263Level20 = 0x02, 435 VDEC_H263Level30 = 0x04, 436 VDEC_H263Level40 = 0x08, 437 VDEC_H263Level45 = 0x10, 438 VDEC_H263Level50 = 0x20, 439 VDEC_H263Level60 = 0x40, 440 VDEC_H263Level70 = 0x80, 441 VDEC_H263LevelKhronosExtensions = 0x6F000000, 442 VDEC_H263LevelVendorStartUnused = 0x7F000000, 443 VDEC_H263LevelMax = 0x7FFFFFFF 444 }; 445 446 enum vdec_wmv_format { 447 VDEC_WMVFormatUnused = 0x01, 448 VDEC_WMVFormat7 = 0x02, 449 VDEC_WMVFormat8 = 0x04, 450 VDEC_WMVFormat9 = 0x08, 451 VDEC_WMFFormatKhronosExtensions = 0x6F000000, 452 VDEC_WMFFormatVendorStartUnused = 0x7F000000, 453 VDEC_WMVFormatMax = 0x7FFFFFFF 454 }; 455 456 enum vdec_vc1_profile { 457 VDEC_VC1ProfileSimple = 0x1, 458 VDEC_VC1ProfileMain = 0x2, 459 VDEC_VC1ProfileAdvanced = 0x4 460 }; 461 462 enum vdec_vc1_level { 463 VDEC_VC1_LEVEL_S_Low = 0x1, 464 VDEC_VC1_LEVEL_S_Medium = 0x2, 465 VDEC_VC1_LEVEL_M_Low = 0x4, 466 VDEC_VC1_LEVEL_M_Medium = 0x8, 467 VDEC_VC1_LEVEL_M_High = 0x10, 468 VDEC_VC1_LEVEL_A_L0 = 0x20, 469 VDEC_VC1_LEVEL_A_L1 = 0x40, 470 VDEC_VC1_LEVEL_A_L2 = 0x80, 471 VDEC_VC1_LEVEL_A_L3 = 0x100, 472 VDEC_VC1_LEVEL_A_L4 = 0x200 473 }; 474 475 struct vdec_profile_level { 476 uint32_t profiles; 477 uint32_t levels; 478 }; 479 480 enum vdec_interlaced_format { 481 VDEC_InterlaceFrameProgressive = 0x1, 482 VDEC_InterlaceInterleaveFrameTopFieldFirst = 0x2, 483 VDEC_InterlaceInterleaveFrameBottomFieldFirst = 0x4 484 }; 485 486 enum vdec_output_fromat { 487 VDEC_YUV_FORMAT_NV12 = 0x1, 488 VDEC_YUV_FORMAT_TILE_4x2 = 0x2 489 }; 490 491 enum vdec_output_order { 492 VDEC_ORDER_DISPLAY = 0x1, 493 VDEC_ORDER_DECODE = 0x2 494 }; 495 496 struct vdec_picsize { 497 uint32_t frame_width; 498 uint32_t frame_height; 499 uint32_t stride; 500 uint32_t scan_lines; 501 }; 502 503 struct vdec_seqheader { 504 void __user *ptr_seqheader; 505 size_t seq_header_len; 506 int pmem_fd; 507 size_t pmem_offset; 508 }; 509 510 struct vdec_mberror { 511 void __user *ptr_errormap; 512 size_t err_mapsize; 513 }; 514 515 struct vdec_input_frameinfo { 516 void __user *bufferaddr; 517 size_t offset; 518 size_t datalen; 519 uint32_t flags; 520 int64_t timestamp; 521 void *client_data; 522 int pmem_fd; 523 size_t pmem_offset; 524 void __user *desc_addr; 525 uint32_t desc_size; 526 }; 527 528 struct vdec_framesize { 529 uint32_t left; 530 uint32_t top; 531 uint32_t right; 532 uint32_t bottom; 533 }; 534 535 struct vdec_aspectratioinfo { 536 uint32_t aspect_ratio; 537 uint32_t par_width; 538 uint32_t par_height; 539 }; 540 541 struct vdec_sep_metadatainfo { 542 void __user *metabufaddr; 543 uint32_t size; 544 }; 545 546 struct vdec_output_frameinfo { 547 void __user *bufferaddr; 548 size_t offset; 549 size_t len; 550 uint32_t flags; 551 int64_t time_stamp; 552 enum vdec_picture pic_type; 553 void *client_data; 554 void *input_frame_clientdata; 555 struct vdec_framesize framesize; 556 enum vdec_interlaced_format interlaced_format; 557 struct vdec_aspectratioinfo aspect_ratio_info; 558 struct vdec_sep_metadatainfo metadata_info; 559 }; 560 561 union vdec_msgdata { 562 struct vdec_output_frameinfo output_frame; 563 void *input_frame_clientdata; 564 }; 565 566 struct vdec_msginfo { 567 uint32_t status_code; 568 uint32_t msgcode; 569 union vdec_msgdata msgdata; 570 size_t msgdatasize; 571 }; 572 573 struct vdec_framerate { 574 unsigned long fps_denominator; 575 unsigned long fps_numerator; 576 }; 577 578 struct vdec_h264_mv{ 579 size_t size; 580 int count; 581 int pmem_fd; 582 int offset; 583 }; 584 585 struct vdec_mv_buff_size{ 586 int width; 587 int height; 588 int size; 589 int alignment; 590 }; 591 592 struct vdec_meta_buffers { 593 size_t size; 594 int count; 595 int pmem_fd; 596 int pmem_fd_iommu; 597 int offset; 598 }; 599 600 #endif /* end of macro _VDECDECODER_H_ */ 601
