Lines Matching refs:r_base
251 LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) {
252 DCHECK(!r_base.IsFloat());
300 return NewLIR3(opcode, dest, r_base.GetReg(), offset);
303 LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
304 DCHECK(!r_base.IsFloat());
353 return NewLIR3(opcode, r_base.GetReg(), offset, src);
364 LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) {
384 LIR *l = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), offset);
386 DCHECK(r_base == rs_rX86_SP);
549 LIR* X86Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) {
557 return NewLIR2(opcode, r_base.GetReg(), disp);
634 LIR* X86Mir2Lir::LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale,
692 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), displacement + LOWORD_OFFSET);
695 if (r_base == r_dest.GetLow()) {
696 load = NewLIR3(opcode, r_dest.GetHighReg(), r_base.GetReg(),
698 load2 = NewLIR3(opcode, r_dest.GetLowReg(), r_base.GetReg(), displacement + LOWORD_OFFSET);
700 load = NewLIR3(opcode, r_dest.GetLowReg(), r_base.GetReg(), displacement + LOWORD_OFFSET);
701 load2 = NewLIR3(opcode, r_dest.GetHighReg(), r_base.GetReg(),
706 DCHECK(r_base == rs_rX86_SP);
716 load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
720 if (r_base == r_dest.GetLow()) {
724 load = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
726 load2 = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale,
731 load = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale,
733 load2 = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale,
740 load = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
742 load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale,
747 load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale,
749 load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale,
761 LIR* X86Mir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest,
763 return LoadBaseIndexedDisp(r_base, r_index, scale, 0, r_dest, size);
766 LIR* X86Mir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
771 LIR* load = LoadBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, r_dest,
781 LIR* X86Mir2Lir::StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale,
834 store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetReg());
837 store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetLowReg());
838 store2 = NewLIR3(opcode, r_base.GetReg(), displacement + HIWORD_OFFSET, r_src.GetHighReg());
841 DCHECK(r_base == rs_rX86_SP);
851 store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale,
855 store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale,
857 store2 = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale,
865 LIR* X86Mir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src,
867 return StoreBaseIndexedDisp(r_base, r_index, scale, 0, r_src, size);
870 LIR* X86Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
879 LIR* store = StoreBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, r_src, size);
