1 //===-- lldb_EmulateInstructionARM.h ------------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef lldb_EmulateInstructionARM_h_ 11 #define lldb_EmulateInstructionARM_h_ 12 13 #include "lldb/Core/EmulateInstruction.h" 14 #include "lldb/Core/ConstString.h" 15 #include "lldb/Core/Error.h" 16 #include "Plugins/Process/Utility/ARMDefines.h" 17 18 namespace lldb_private { 19 20 // ITSession - Keep track of the IT Block progression. 21 class ITSession 22 { 23 public: 24 ITSession() : ITCounter(0), ITState(0) {} 25 ~ITSession() {} 26 27 // InitIT - Initializes ITCounter/ITState. 28 bool InitIT(uint32_t bits7_0); 29 30 // ITAdvance - Updates ITCounter/ITState as IT Block progresses. 31 void ITAdvance(); 32 33 // InITBlock - Returns true if we're inside an IT Block. 34 bool InITBlock(); 35 36 // LastInITBlock - Returns true if we're the last instruction inside an IT Block. 37 bool LastInITBlock(); 38 39 // GetCond - Gets condition bits for the current thumb instruction. 40 uint32_t GetCond(); 41 42 private: 43 uint32_t ITCounter; // Possible values: 0, 1, 2, 3, 4. 44 uint32_t ITState; // A2.5.2 Consists of IT[7:5] and IT[4:0] initially. 45 }; 46 47 class EmulateInstructionARM : public EmulateInstruction 48 { 49 public: 50 typedef enum 51 { 52 eEncodingA1, 53 eEncodingA2, 54 eEncodingA3, 55 eEncodingA4, 56 eEncodingA5, 57 eEncodingT1, 58 eEncodingT2, 59 eEncodingT3, 60 eEncodingT4, 61 eEncodingT5 62 } ARMEncoding; 63 64 65 static void 66 Initialize (); 67 68 static void 69 Terminate (); 70 71 static lldb_private::ConstString 72 GetPluginNameStatic (); 73 74 static const char * 75 GetPluginDescriptionStatic (); 76 77 static lldb_private::EmulateInstruction * 78 CreateInstance (const lldb_private::ArchSpec &arch, 79 InstructionType inst_type); 80 81 static bool 82 SupportsEmulatingIntructionsOfTypeStatic (InstructionType inst_type) 83 { 84 switch (inst_type) 85 { 86 case eInstructionTypeAny: 87 case eInstructionTypePrologueEpilogue: 88 case eInstructionTypePCModifying: 89 return true; 90 91 case eInstructionTypeAll: 92 return false; 93 } 94 return false; 95 } 96 97 virtual lldb_private::ConstString 98 GetPluginName() 99 { 100 return GetPluginNameStatic(); 101 } 102 103 virtual uint32_t 104 GetPluginVersion() 105 { 106 return 1; 107 } 108 109 bool 110 SetTargetTriple (const ArchSpec &arch); 111 112 enum Mode 113 { 114 eModeInvalid = -1, 115 eModeARM, 116 eModeThumb 117 }; 118 119 EmulateInstructionARM (const ArchSpec &arch) : 120 EmulateInstruction (arch), 121 m_arm_isa (0), 122 m_opcode_mode (eModeInvalid), 123 m_opcode_cpsr (0), 124 m_it_session (), 125 m_ignore_conditions (false) 126 { 127 SetArchitecture (arch); 128 } 129 130 // EmulateInstructionARM (const ArchSpec &arch, 131 // bool ignore_conditions, 132 // void *baton, 133 // ReadMemory read_mem_callback, 134 // WriteMemory write_mem_callback, 135 // ReadRegister read_reg_callback, 136 // WriteRegister write_reg_callback) : 137 // EmulateInstruction (arch, 138 // ignore_conditions, 139 // baton, 140 // read_mem_callback, 141 // write_mem_callback, 142 // read_reg_callback, 143 // write_reg_callback), 144 // m_arm_isa (0), 145 // m_opcode_mode (eModeInvalid), 146 // m_opcode_cpsr (0), 147 // m_it_session () 148 // { 149 // } 150 151 virtual bool 152 SupportsEmulatingIntructionsOfType (InstructionType inst_type) 153 { 154 return SupportsEmulatingIntructionsOfTypeStatic (inst_type); 155 } 156 157 virtual bool 158 SetArchitecture (const ArchSpec &arch); 159 160 virtual bool 161 ReadInstruction (); 162 163 virtual bool 164 SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target); 165 166 virtual bool 167 EvaluateInstruction (uint32_t evaluate_options); 168 169 virtual bool 170 TestEmulation (Stream *out_stream, ArchSpec &arch, OptionValueDictionary *test_data); 171 172 virtual bool 173 GetRegisterInfo (uint32_t reg_kind, uint32_t reg_num, RegisterInfo ®_info); 174 175 176 virtual bool 177 CreateFunctionEntryUnwind (UnwindPlan &unwind_plan); 178 179 uint32_t 180 ArchVersion(); 181 182 bool 183 ConditionPassed (const uint32_t opcode, 184 bool *is_conditional = NULL); // Filled in with true if the opcode is a conditional opcode 185 // Filled in with false if the opcode is always executed 186 187 uint32_t 188 CurrentCond (const uint32_t opcode); 189 190 // InITBlock - Returns true if we're in Thumb mode and inside an IT Block. 191 bool InITBlock(); 192 193 // LastInITBlock - Returns true if we're in Thumb mode and the last instruction inside an IT Block. 194 bool LastInITBlock(); 195 196 bool 197 BadMode (uint32_t mode); 198 199 bool 200 CurrentModeIsPrivileged (); 201 202 void 203 CPSRWriteByInstr (uint32_t value, uint32_t bytemask, bool affect_execstate); 204 205 bool 206 BranchWritePC(const Context &context, uint32_t addr); 207 208 bool 209 BXWritePC(Context &context, uint32_t addr); 210 211 bool 212 LoadWritePC(Context &context, uint32_t addr); 213 214 bool 215 ALUWritePC(Context &context, uint32_t addr); 216 217 Mode 218 CurrentInstrSet(); 219 220 bool 221 SelectInstrSet(Mode arm_or_thumb); 222 223 bool 224 WriteBits32Unknown (int n); 225 226 bool 227 WriteBits32UnknownToMemory (lldb::addr_t address); 228 229 bool 230 UnalignedSupport(); 231 232 typedef struct 233 { 234 uint32_t result; 235 uint8_t carry_out; 236 uint8_t overflow; 237 } AddWithCarryResult; 238 239 AddWithCarryResult 240 AddWithCarry(uint32_t x, uint32_t y, uint8_t carry_in); 241 242 // Helper method to read the content of an ARM core register. 243 uint32_t 244 ReadCoreReg (uint32_t regnum, bool *success); 245 246 // See A8.6.96 MOV (immediate) Operation. 247 // Default arguments are specified for carry and overflow parameters, which means 248 // not to update the respective flags even if setflags is true. 249 bool 250 WriteCoreRegOptionalFlags (Context &context, 251 const uint32_t result, 252 const uint32_t Rd, 253 bool setflags, 254 const uint32_t carry = ~0u, 255 const uint32_t overflow = ~0u); 256 257 bool 258 WriteCoreReg (Context &context, 259 const uint32_t result, 260 const uint32_t Rd) 261 { 262 // Don't set the flags. 263 return WriteCoreRegOptionalFlags(context, result, Rd, false); 264 } 265 266 // See A8.6.35 CMP (immediate) Operation. 267 // Default arguments are specified for carry and overflow parameters, which means 268 // not to update the respective flags. 269 bool 270 WriteFlags (Context &context, 271 const uint32_t result, 272 const uint32_t carry = ~0u, 273 const uint32_t overflow = ~0u); 274 275 inline uint64_t 276 MemARead (EmulateInstruction::Context &context, 277 lldb::addr_t address, 278 uint32_t size, 279 uint64_t fail_value, 280 bool *success_ptr) 281 { 282 // This is a stub function corresponding to "MemA[]" in the ARM manual pseudocode, for 283 // aligned reads from memory. Since we are not trying to write a full hardware simulator, and since 284 // we are running in User mode (rather than Kernel mode) and therefore won't have access to many of the 285 // system registers we would need in order to fully implement this function, we will just call 286 // ReadMemoryUnsigned from here. In the future, if we decide we do need to do more faithful emulation of 287 // the hardware, we can update this function appropriately. 288 289 return ReadMemoryUnsigned (context, address, size, fail_value, success_ptr); 290 } 291 292 inline bool 293 MemAWrite (EmulateInstruction::Context &context, 294 lldb::addr_t address, 295 uint64_t data_val, 296 uint32_t size) 297 298 { 299 // This is a stub function corresponding to "MemA[]" in the ARM manual pseudocode, for 300 // aligned writes to memory. Since we are not trying to write a full hardware simulator, and since 301 // we are running in User mode (rather than Kernel mode) and therefore won't have access to many of the 302 // system registers we would need in order to fully implement this function, we will just call 303 // WriteMemoryUnsigned from here. In the future, if we decide we do need to do more faithful emulation of 304 // the hardware, we can update this function appropriately. 305 306 return WriteMemoryUnsigned (context, address, data_val, size); 307 } 308 309 310 inline uint64_t 311 MemURead (EmulateInstruction::Context &context, 312 lldb::addr_t address, 313 uint32_t size, 314 uint64_t fail_value, 315 bool *success_ptr) 316 { 317 // This is a stub function corresponding to "MemU[]" in the ARM manual pseudocode, for 318 // unaligned reads from memory. Since we are not trying to write a full hardware simulator, and since 319 // we are running in User mode (rather than Kernel mode) and therefore won't have access to many of the 320 // system registers we would need in order to fully implement this function, we will just call 321 // ReadMemoryUnsigned from here. In the future, if we decide we do need to do more faithful emulation of 322 // the hardware, we can update this function appropriately. 323 324 return ReadMemoryUnsigned (context, address, size, fail_value, success_ptr); 325 } 326 327 inline bool 328 MemUWrite (EmulateInstruction::Context &context, 329 lldb::addr_t address, 330 uint64_t data_val, 331 uint32_t size) 332 333 { 334 // This is a stub function corresponding to "MemU[]" in the ARM manual pseudocode, for 335 // unaligned writes to memory. Since we are not trying to write a full hardware simulator, and since 336 // we are running in User mode (rather than Kernel mode) and therefore won't have access to many of the 337 // system registers we would need in order to fully implement this function, we will just call 338 // WriteMemoryUnsigned from here. In the future, if we decide we do need to do more faithful emulation of 339 // the hardware, we can update this function appropriately. 340 341 return WriteMemoryUnsigned (context, address, data_val, size); 342 } 343 344 protected: 345 346 // Typedef for the callback function used during the emulation. 347 // Pass along (ARMEncoding)encoding as the callback data. 348 typedef enum 349 { 350 eSize16, 351 eSize32 352 } ARMInstrSize; 353 354 typedef struct 355 { 356 uint32_t mask; 357 uint32_t value; 358 uint32_t variants; 359 EmulateInstructionARM::ARMEncoding encoding; 360 uint32_t vfp_variants; 361 ARMInstrSize size; 362 bool (EmulateInstructionARM::*callback) (const uint32_t opcode, const EmulateInstructionARM::ARMEncoding encoding); 363 const char *name; 364 } ARMOpcode; 365 366 uint32_t 367 GetFramePointerRegisterNumber () const; 368 369 uint32_t 370 GetFramePointerDWARFRegisterNumber () const; 371 372 static ARMOpcode* 373 GetARMOpcodeForInstruction (const uint32_t opcode, uint32_t isa_mask); 374 375 static ARMOpcode* 376 GetThumbOpcodeForInstruction (const uint32_t opcode, uint32_t isa_mask); 377 378 // A8.6.123 PUSH 379 bool 380 EmulatePUSH (const uint32_t opcode, const ARMEncoding encoding); 381 382 // A8.6.122 POP 383 bool 384 EmulatePOP (const uint32_t opcode, const ARMEncoding encoding); 385 386 // A8.6.8 ADD (SP plus immediate) 387 bool 388 EmulateADDRdSPImm (const uint32_t opcode, const ARMEncoding encoding); 389 390 // A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp 391 bool 392 EmulateMOVRdSP (const uint32_t opcode, const ARMEncoding encoding); 393 394 // A8.6.97 MOV (register) -- move from r8-r15 to r0-r7 395 bool 396 EmulateMOVLowHigh (const uint32_t opcode, const ARMEncoding encoding); 397 398 // A8.6.59 LDR (literal) 399 bool 400 EmulateLDRRtPCRelative (const uint32_t opcode, const ARMEncoding encoding); 401 402 // A8.6.8 ADD (SP plus immediate) 403 bool 404 EmulateADDSPImm (const uint32_t opcode, const ARMEncoding encoding); 405 406 // A8.6.9 ADD (SP plus register) 407 bool 408 EmulateADDSPRm (const uint32_t opcode, const ARMEncoding encoding); 409 410 // A8.6.23 BL, BLX (immediate) 411 bool 412 EmulateBLXImmediate (const uint32_t opcode, const ARMEncoding encoding); 413 414 // A8.6.24 BLX (register) 415 bool 416 EmulateBLXRm (const uint32_t opcode, const ARMEncoding encoding); 417 418 // A8.6.25 BX 419 bool 420 EmulateBXRm (const uint32_t opcode, const ARMEncoding encoding); 421 422 // A8.6.26 BXJ 423 bool 424 EmulateBXJRm (const uint32_t opcode, const ARMEncoding encoding); 425 426 // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip 427 bool 428 EmulateSUBR7IPImm (const uint32_t opcode, const ARMEncoding encoding); 429 430 // A8.6.215 SUB (SP minus immediate) -- Rd == ip 431 bool 432 EmulateSUBIPSPImm (const uint32_t opcode, const ARMEncoding encoding); 433 434 // A8.6.215 SUB (SP minus immediate) 435 bool 436 EmulateSUBSPImm (const uint32_t opcode, const ARMEncoding encoding); 437 438 // A8.6.216 SUB (SP minus register) 439 bool 440 EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding encoding); 441 442 // A8.6.194 STR (immediate, ARM) -- Rn == sp 443 bool 444 EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding encoding); 445 446 // A8.6.355 VPUSH 447 bool 448 EmulateVPUSH (const uint32_t opcode, const ARMEncoding encoding); 449 450 // A8.6.354 VPOP 451 bool 452 EmulateVPOP (const uint32_t opcode, const ARMEncoding encoding); 453 454 // A8.6.218 SVC (previously SWI) 455 bool 456 EmulateSVC (const uint32_t opcode, const ARMEncoding encoding); 457 458 // A8.6.50 IT 459 bool 460 EmulateIT (const uint32_t opcode, const ARMEncoding encoding); 461 462 // NOP 463 bool 464 EmulateNop (const uint32_t opcode, const ARMEncoding encoding); 465 466 // A8.6.16 B 467 bool 468 EmulateB (const uint32_t opcode, const ARMEncoding encoding); 469 470 // A8.6.27 CBNZ, CBZ 471 bool 472 EmulateCB (const uint32_t opcode, const ARMEncoding encoding); 473 474 // A8.6.226 TBB, TBH 475 bool 476 EmulateTB (const uint32_t opcode, const ARMEncoding encoding); 477 478 // A8.6.4 ADD (immediate, Thumb) 479 bool 480 EmulateADDImmThumb (const uint32_t opcode, const ARMEncoding encoding); 481 482 // A8.6.5 ADD (immediate, ARM) 483 bool 484 EmulateADDImmARM (const uint32_t opcode, const ARMEncoding encoding); 485 486 // A8.6.6 ADD (register) 487 bool 488 EmulateADDReg (const uint32_t opcode, const ARMEncoding encoding); 489 490 // A8.6.7 ADD (register-shifted register) 491 bool 492 EmulateADDRegShift (const uint32_t opcode, const ARMEncoding encoding); 493 494 // A8.6.97 MOV (register) 495 bool 496 EmulateMOVRdRm (const uint32_t opcode, const ARMEncoding encoding); 497 498 // A8.6.96 MOV (immediate) 499 bool 500 EmulateMOVRdImm (const uint32_t opcode, const ARMEncoding encoding); 501 502 // A8.6.35 CMP (immediate) 503 bool 504 EmulateCMPImm (const uint32_t opcode, const ARMEncoding encoding); 505 506 // A8.6.36 CMP (register) 507 bool 508 EmulateCMPReg (const uint32_t opcode, const ARMEncoding encoding); 509 510 // A8.6.14 ASR (immediate) 511 bool 512 EmulateASRImm (const uint32_t opcode, const ARMEncoding encoding); 513 514 // A8.6.15 ASR (register) 515 bool 516 EmulateASRReg (const uint32_t opcode, const ARMEncoding encoding); 517 518 // A8.6.88 LSL (immediate) 519 bool 520 EmulateLSLImm (const uint32_t opcode, const ARMEncoding encoding); 521 522 // A8.6.89 LSL (register) 523 bool 524 EmulateLSLReg (const uint32_t opcode, const ARMEncoding encoding); 525 526 // A8.6.90 LSR (immediate) 527 bool 528 EmulateLSRImm (const uint32_t opcode, const ARMEncoding encoding); 529 530 // A8.6.91 LSR (register) 531 bool 532 EmulateLSRReg (const uint32_t opcode, const ARMEncoding encoding); 533 534 // A8.6.139 ROR (immediate) 535 bool 536 EmulateRORImm (const uint32_t opcode, const ARMEncoding encoding); 537 538 // A8.6.140 ROR (register) 539 bool 540 EmulateRORReg (const uint32_t opcode, const ARMEncoding encoding); 541 542 // A8.6.141 RRX 543 bool 544 EmulateRRX (const uint32_t opcode, const ARMEncoding encoding); 545 546 // Helper method for ASR, LSL, LSR, ROR (immediate), and RRX 547 bool 548 EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type); 549 550 // Helper method for ASR, LSL, LSR, and ROR (register) 551 bool 552 EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type); 553 554 // LOAD FUNCTIONS 555 556 // A8.6.53 LDM/LDMIA/LDMFD 557 bool 558 EmulateLDM (const uint32_t opcode, const ARMEncoding encoding); 559 560 // A8.6.54 LDMDA/LDMFA 561 bool 562 EmulateLDMDA (const uint32_t opcode, const ARMEncoding encoding); 563 564 // A8.6.55 LDMDB/LDMEA 565 bool 566 EmulateLDMDB (const uint32_t opcode, const ARMEncoding encoding); 567 568 // A8.6.56 LDMIB/LDMED 569 bool 570 EmulateLDMIB (const uint32_t opcode, const ARMEncoding encoding); 571 572 // A8.6.57 LDR (immediate, Thumb) -- Encoding T1 573 bool 574 EmulateLDRRtRnImm (const uint32_t opcode, const ARMEncoding encoding); 575 576 // A8.6.58 LDR (immediate, ARM) - Encoding A1 577 bool 578 EmulateLDRImmediateARM (const uint32_t opcode, const ARMEncoding encoding); 579 580 // A8.6.59 LDR (literal) 581 bool 582 EmulateLDRLiteral (const uint32_t, const ARMEncoding encoding); 583 584 // A8.6.60 LDR (register) - Encoding T1, T2, A1 585 bool 586 EmulateLDRRegister (const uint32_t opcode, const ARMEncoding encoding); 587 588 // A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2, T3 589 bool 590 EmulateLDRBImmediate (const uint32_t opcode, const ARMEncoding encoding); 591 592 // A8.6.62 LDRB (immediate, ARM) 593 bool 594 EmulateLDRBImmediateARM (const uint32_t opcode, const ARMEncoding encoding); 595 596 // A8.6.63 LDRB (literal) - Encoding T1, A1 597 bool 598 EmulateLDRBLiteral (const uint32_t opcode, const ARMEncoding encoding); 599 600 // A8.6.64 LDRB (register) - Encoding T1, T2, A1 601 bool 602 EmulateLDRBRegister (const uint32_t opcode, const ARMEncoding encoding); 603 604 // A8.6.65 LDRBT 605 bool 606 EmulateLDRBT (const uint32_t opcode, const ARMEncoding encoding); 607 608 // A8.6.66 LDRD (immediate) 609 bool 610 EmulateLDRDImmediate (const uint32_t opcode, const ARMEncoding encoding); 611 612 // A8.6.67 613 bool 614 EmulateLDRDLiteral (const uint32_t opcode, const ARMEncoding encoding); 615 616 // A8.6.68 LDRD (register) 617 bool 618 EmulateLDRDRegister (const uint32_t opcode, const ARMEncoding encoding); 619 620 // A8.6.69 LDREX 621 bool 622 EmulateLDREX (const uint32_t opcode, const ARMEncoding encoding); 623 624 // A8.6.70 LDREXB 625 bool 626 EmulateLDREXB (const uint32_t opcode, const ARMEncoding encoding); 627 628 // A8.6.71 LDREXD 629 bool 630 EmulateLDREXD (const uint32_t opcode, const ARMEncoding encoding); 631 632 // A8.6.72 LDREXH 633 bool 634 EmulateLDREXH (const uint32_t opcode, const ARMEncoding encoding); 635 636 // A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2, T3 637 bool 638 EmulateLDRHImmediate (const uint32_t opcode, const ARMEncoding encoding); 639 640 // A8.6.74 LDRS (immediate, ARM) 641 bool 642 EmulateLDRHImmediateARM (const uint32_t opcode, const ARMEncoding encoding); 643 644 // A8.6.75 LDRH (literal) - Encoding T1, A1 645 bool 646 EmulateLDRHLiteral (const uint32_t opcode, const ARMEncoding encoding); 647 648 // A8.6.76 LDRH (register) - Encoding T1, T2, A1 649 bool 650 EmulateLDRHRegister (const uint32_t opcode, const ARMEncoding encoding); 651 652 // A8.6.77 LDRHT 653 bool 654 EmulateLDRHT (const uint32_t opcode, const ARMEncoding encoding); 655 656 // A8.6.78 LDRSB (immediate) - Encoding T1, T2, A1 657 bool 658 EmulateLDRSBImmediate (const uint32_t opcode, const ARMEncoding encoding); 659 660 // A8.6.79 LDRSB (literal) - Encoding T1, A1 661 bool 662 EmulateLDRSBLiteral (const uint32_t opcode, const ARMEncoding encoding); 663 664 // A8.6.80 LDRSB (register) - Encoding T1, T2, A1 665 bool 666 EmulateLDRSBRegister (const uint32_t opcode, const ARMEncoding encoding); 667 668 // A8.6.81 LDRSBT 669 bool 670 EmulateLDRSBT (const uint32_t opcode, const ARMEncoding encoding); 671 672 // A8.6.82 LDRSH (immediate) - Encoding T1, T2, A1 673 bool 674 EmulateLDRSHImmediate (const uint32_t opcode, const ARMEncoding encoding); 675 676 // A8.6.83 LDRSH (literal) - Encoding T1, A1 677 bool 678 EmulateLDRSHLiteral (const uint32_t opcode, const ARMEncoding encoding); 679 680 // A8.6.84 LDRSH (register) - Encoding T1, T2, A1 681 bool 682 EmulateLDRSHRegister (const uint32_t opcode, const ARMEncoding encoding); 683 684 // A8.6.85 LDRSHT 685 bool 686 EmulateLDRSHT (const uint32_t opcode, const ARMEncoding encoding); 687 688 // A8.6.86 689 bool 690 EmulateLDRT (const uint32_t opcode, const ARMEncoding encoding); 691 692 693 // STORE FUNCTIONS 694 695 // A8.6.189 STM/STMIA/STMEA 696 bool 697 EmulateSTM (const uint32_t opcode, const ARMEncoding encoding); 698 699 // A8.6.190 STMDA/STMED 700 bool 701 EmulateSTMDA (const uint32_t opcode, const ARMEncoding encoding); 702 703 // A8.6.191 STMDB/STMFD 704 bool 705 EmulateSTMDB (const uint32_t opcode, const ARMEncoding encoding); 706 707 // A8.6.192 STMIB/STMFA 708 bool 709 EmulateSTMIB (const uint32_t opcode, const ARMEncoding encoding); 710 711 // A8.6.193 STR (immediate, Thumb) 712 bool 713 EmulateSTRThumb(const uint32_t opcode, const ARMEncoding encoding); 714 715 // A8.6.194 STR (immediate, ARM) 716 bool 717 EmulateSTRImmARM (const uint32_t opcode, const ARMEncoding encoding); 718 719 // A8.6.195 STR (register) 720 bool 721 EmulateSTRRegister (const uint32_t opcode, const ARMEncoding encoding); 722 723 // A8.6.196 STRB (immediate, Thumb) 724 bool 725 EmulateSTRBThumb (const uint32_t opcode, const ARMEncoding encoding); 726 727 // A8.6.197 STRB (immediate, ARM) 728 bool 729 EmulateSTRBImmARM (const uint32_t opcode, const ARMEncoding encoding); 730 731 // A8.6.198 STRB (register) 732 bool 733 EmulateSTRBReg (const uint32_t opcode, const ARMEncoding encoding); 734 735 // A8.6.199 STRBT 736 bool 737 EmulateSTRBT (const uint32_t opcode, const ARMEncoding encoding); 738 739 // A8.6.200 STRD (immediate) 740 bool 741 EmulateSTRDImm (const uint32_t opcode, const ARMEncoding encoding); 742 743 // A8.6.201 STRD (register) 744 bool 745 EmulateSTRDReg (const uint32_t opcode, const ARMEncoding encoding); 746 747 // A8.6.202 STREX 748 bool 749 EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding); 750 751 // A8.6.203 STREXB 752 bool 753 EmulateSTREXB (const uint32_t opcode, const ARMEncoding encoding); 754 755 // A8.6.204 STREXD 756 bool 757 EmulateSTREXD (const uint32_t opcode, const ARMEncoding encoding); 758 759 // A8.6.205 STREXH 760 bool 761 EmulateSTREXH (const uint32_t opcode, const ARMEncoding encoding); 762 763 // A8.6.206 STRH (immediate, Thumb) 764 bool 765 EmulateSTRHImmThumb (const uint32_t opcode, const ARMEncoding encoding); 766 767 // A8.6.207 STRH (immediate, ARM) 768 bool 769 EmulateSTRHImmARM (const uint32_t opcode, const ARMEncoding encoding); 770 771 // A8.6.208 STRH (register) 772 bool 773 EmulateSTRHRegister (const uint32_t opcode, const ARMEncoding encoding); 774 775 // A8.6.209 STRHT 776 bool 777 EmulateSTRHT (const uint32_t opcode, const ARMEncoding encoding); 778 779 // A8.6.210 STRT 780 bool 781 EmulateSTRT (const uint32_t opcode, const ARMEncoding encoding); 782 783 // A8.6.1 ADC (immediate) 784 bool 785 EmulateADCImm (const uint32_t opcode, const ARMEncoding encoding); 786 787 // A8.6.2 ADC (Register) 788 bool 789 EmulateADCReg (const uint32_t opcode, const ARMEncoding encoding); 790 791 // A8.6.10 ADR 792 bool 793 EmulateADR (const uint32_t opcode, const ARMEncoding encoding); 794 795 // A8.6.11 AND (immediate) 796 bool 797 EmulateANDImm (const uint32_t opcode, const ARMEncoding encoding); 798 799 // A8.6.12 AND (register) 800 bool 801 EmulateANDReg (const uint32_t opcode, const ARMEncoding encoding); 802 803 // A8.6.19 BIC (immediate) 804 bool 805 EmulateBICImm (const uint32_t opcode, const ARMEncoding encoding); 806 807 // A8.6.20 BIC (register) 808 bool 809 EmulateBICReg (const uint32_t opcode, const ARMEncoding encoding); 810 811 // A8.6.26 BXJ 812 bool 813 EmulateBXJ (const uint32_t opcode, const ARMEncoding encoding); 814 815 // A8.6.32 CMN (immediate) 816 bool 817 EmulateCMNImm (const uint32_t opcode, const ARMEncoding encoding); 818 819 // A8.6.33 CMN (register) 820 bool 821 EmulateCMNReg (const uint32_t opcode, const ARMEncoding encoding); 822 823 // A8.6.44 EOR (immediate) 824 bool 825 EmulateEORImm (const uint32_t opcode, const ARMEncoding encoding); 826 827 // A8.6.45 EOR (register) 828 bool 829 EmulateEORReg (const uint32_t opcode, const ARMEncoding encoding); 830 831 // A8.6.105 MUL 832 bool 833 EmulateMUL (const uint32_t opcode, const ARMEncoding encoding); 834 835 // A8.6.106 MVN (immediate) 836 bool 837 EmulateMVNImm (const uint32_t opcode, const ARMEncoding encoding); 838 839 // A8.6.107 MVN (register) 840 bool 841 EmulateMVNReg (const uint32_t opcode, const ARMEncoding encoding); 842 843 // A8.6.113 ORR (immediate) 844 bool 845 EmulateORRImm (const uint32_t opcode, const ARMEncoding encoding); 846 847 // A8.6.114 ORR (register) 848 bool 849 EmulateORRReg (const uint32_t opcode, const ARMEncoding encoding); 850 851 // A8.6.117 PLD (immediate, literal) - Encoding T1, T2, T3, A1 852 bool 853 EmulatePLDImmediate (const uint32_t opcode, const ARMEncoding encoding); 854 855 // A8.6.119 PLI (immediate,literal) - Encoding T3, A1 856 bool 857 EmulatePLIImmediate (const uint32_t opcode, const ARMEncoding encoding); 858 859 // A8.6.120 PLI (register) - Encoding T1, A1 860 bool 861 EmulatePLIRegister (const uint32_t opcode, const ARMEncoding encoding); 862 863 // A8.6.141 RSB (immediate) 864 bool 865 EmulateRSBImm (const uint32_t opcode, const ARMEncoding encoding); 866 867 // A8.6.142 RSB (register) 868 bool 869 EmulateRSBReg (const uint32_t opcode, const ARMEncoding encoding); 870 871 // A8.6.144 RSC (immediate) 872 bool 873 EmulateRSCImm (const uint32_t opcode, const ARMEncoding encoding); 874 875 // A8.6.145 RSC (register) 876 bool 877 EmulateRSCReg (const uint32_t opcode, const ARMEncoding encoding); 878 879 // A8.6.150 SBC (immediate) 880 bool 881 EmulateSBCImm (const uint32_t opcode, const ARMEncoding encoding); 882 883 // A8.6.151 SBC (register) 884 bool 885 EmulateSBCReg (const uint32_t opcode, const ARMEncoding encoding); 886 887 // A8.6.211 SUB (immediate, Thumb) 888 bool 889 EmulateSUBImmThumb (const uint32_t opcode, const ARMEncoding encoding); 890 891 // A8.6.212 SUB (immediate, ARM) 892 bool 893 EmulateSUBImmARM (const uint32_t opcode, const ARMEncoding encoding); 894 895 // A8.6.213 SUB (register) 896 bool 897 EmulateSUBReg (const uint32_t opcode, const ARMEncoding encoding); 898 899 // A8.6.214 SUB (register-shifted register) 900 bool 901 EmulateSUBRegShift (const uint32_t opcode, const ARMEncoding encoding); 902 903 // A8.6.222 SXTB - Encoding T1 904 bool 905 EmulateSXTB (const uint32_t opcode, const ARMEncoding encoding); 906 907 // A8.6.224 SXTH - EncodingT1 908 bool 909 EmulateSXTH (const uint32_t opcode, const ARMEncoding encoding); 910 911 // A8.6.227 TEQ (immediate) - Encoding A1 912 bool 913 EmulateTEQImm (const uint32_t opcode, const ARMEncoding encoding); 914 915 // A8.6.228 TEQ (register) - Encoding A1 916 bool 917 EmulateTEQReg (const uint32_t opcode, const ARMEncoding encoding); 918 919 // A8.6.230 TST (immediate) - Encoding A1 920 bool 921 EmulateTSTImm (const uint32_t opcode, const ARMEncoding encoding); 922 923 // A8.6.231 TST (register) - Encoding T1, A1 924 bool 925 EmulateTSTReg (const uint32_t opcode, const ARMEncoding encoding); 926 927 // A8.6.262 UXTB - Encoding T1 928 bool 929 EmulateUXTB (const uint32_t opcode, const ARMEncoding encoding); 930 931 // A8.6.264 UXTH - Encoding T1 932 bool 933 EmulateUXTH (const uint32_t opcode, const ARMEncoding encoding); 934 935 // B6.1.8 RFE 936 bool 937 EmulateRFE (const uint32_t opcode, const ARMEncoding encoding); 938 939 // A8.6.319 VLDM 940 bool 941 EmulateVLDM (const uint32_t opcode, const ARMEncoding encoding); 942 943 // A8.6.399 VSTM 944 bool 945 EmulateVSTM (const uint32_t opcode, const ARMEncoding encoding); 946 947 // A8.6.307 VLD1 (multiple single elements) 948 bool 949 EmulateVLD1Multiple (const uint32_t opcode, const ARMEncoding encoding); 950 951 // A8.6.308 VLD1 (single element to one lane) 952 bool 953 EmulateVLD1Single (const uint32_t opcode, const ARMEncoding encoding); 954 955 // A8.6.309 VLD1 (single element to all lanes) 956 bool 957 EmulateVLD1SingleAll (const uint32_t opcode, const ARMEncoding encoding); 958 959 // A8.6.391 VST1 (multiple single elements) 960 bool 961 EmulateVST1Multiple (const uint32_t opcode, const ARMEncoding encoding); 962 963 // A8.6.392 VST1 (single element from one lane) 964 bool 965 EmulateVST1Single (const uint32_t opcode, const ARMEncoding encoding); 966 967 // A8.6.317 VLDR 968 bool 969 EmulateVLDR (const uint32_t opcode, const ARMEncoding encoding); 970 971 972 // A8.6.400 VSTR 973 bool 974 EmulateVSTR (const uint32_t opcode, const ARMEncoding encoding); 975 976 // B6.2.13 SUBS PC, LR and related instructions 977 bool 978 EmulateSUBSPcLrEtc (const uint32_t opcode, const ARMEncoding encoding); 979 980 uint32_t m_arm_isa; 981 Mode m_opcode_mode; 982 uint32_t m_opcode_cpsr; 983 uint32_t m_new_inst_cpsr; // This can get updated by the opcode. 984 ITSession m_it_session; 985 bool m_ignore_conditions; 986 }; 987 988 } // namespace lldb_private 989 990 #endif // lldb_EmulateInstructionARM_h_ 991
