/external/llvm/lib/Target/AArch64/ |
AArch64ExpandPseudoInsts.cpp | 105 const unsigned DstReg = MI.getOperand(0).getReg(); 109 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 110 .addReg(DstReg) 170 const unsigned DstReg = MI.getOperand(0).getReg(); 186 .addReg(DstReg, 188 .addReg(DstReg) 211 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 212 .addReg(DstReg) 353 const unsigned DstReg = MI.getOperand(0).getReg(); 360 .addReg(DstReg, [all...] |
AArch64InstrInfo.cpp | 412 unsigned DstReg, 497 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { 501 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { 505 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { 508 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { 540 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm( 590 unsigned &SrcReg, unsigned &DstReg, 603 DstReg = MI.getOperand(0).getReg(); 1001 unsigned DstReg = MI->getOperand(0).getReg(); 1002 return (AArch64::GPR32RegClass.contains(DstReg) || [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
R600ExpandSpecialInstrs.cpp | 96 unsigned DstReg = MI.getOperand(0).getReg(); 120 DstReg = TRI.getSubReg(DstReg, SubRegIndex); 124 Flags |= (Chan != TRI.getHWRegChan(DstReg) ? MO_FLAG_MASK : 0); 125 unsigned DstBase = TRI.getHWRegIndex(DstReg); 126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); 151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
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/external/llvm/lib/CodeGen/ |
ExpandPostRAPseudos.cpp | 86 unsigned DstReg = MI->getOperand(0).getReg(); 92 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); 94 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && 112 if (DstReg != InsReg) { 124 // Implicitly define DstReg for subsequent uses. 127 CopyMI->addRegisterDefined(DstReg);
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OptimizePHIs.cpp | 91 unsigned DstReg = MI->getOperand(0).getReg(); 104 if (SrcReg == DstReg) 134 unsigned DstReg = MI->getOperand(0).getReg(); 135 assert(TargetRegisterInfo::isVirtualRegister(DstReg) && 146 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) {
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RegisterCoalescer.h | 31 /// DstReg - The register that will be left after coalescing. It can be a 33 unsigned DstReg; 35 /// SrcReg - the virtual register that will be coalesced into dstReg. 38 /// DstIdx - The sub-register index of the old DstReg in the new coalesced 52 /// Flipped - True when DstReg and SrcReg are reversed from the original 56 /// NewRC - The register class of the coalesced register, or NULL if DstReg 58 /// SrcReg and DstReg. 63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), 77 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossibl [all...] |
MachineSink.cpp | 120 unsigned DstReg = MI->getOperand(0).getReg(); 122 !TargetRegisterInfo::isVirtualRegister(DstReg) || 127 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); 136 MRI->replaceRegWith(DstReg, SrcReg);
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EarlyIfConversion.cpp | 113 // Latencies from Cond+Branch, TReg, and FReg to DstReg. 463 unsigned DstReg = PI.PHI->getOperand(0).getReg(); 464 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); 484 unsigned DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst)); 485 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); 488 // Rewrite PHI operands TPred -> (DstReg, Head), remove FPred. 493 PI.PHI->getOperand(i-2).setReg(DstReg);
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LiveDebugVariables.cpp | 580 unsigned DstReg = MI->getOperand(0).getReg(); 586 if (!TargetRegisterInfo::isVirtualRegister(DstReg)) 596 if (!LIS.hasInterval(DstReg)) 598 LiveInterval *DstLI = &LIS.getInterval(DstReg); [all...] |
PeepholeOptimizer.cpp | 265 unsigned SrcReg, DstReg, SubIdx; 266 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) 269 if (TargetRegisterInfo::isPhysicalRegister(DstReg) || 277 // Ensure DstReg can get a register class that actually supports 279 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); 295 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg)) 373 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg)) 385 // About to add uses of DstReg, clear DstReg's kill flags. 387 MRI->clearKillFlags(DstReg); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonExpandPredSpillCode.cpp | 131 // DstReg = LDriw_pred [R30], ofst. 132 int DstReg = MI->getOperand(0).getReg(); 133 assert(Hexagon::PredRegsRegClass.contains(DstReg) && 154 DstReg).addReg(HEXAGON_RESERVED_REG_2); 163 DstReg).addReg(HEXAGON_RESERVED_REG_2); 169 DstReg).addReg(HEXAGON_RESERVED_REG_2);
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HexagonPeephole.cpp | 142 unsigned DstReg = Dst.getReg(); 145 if (TargetRegisterInfo::isVirtualRegister(DstReg) && 150 PeepholeMap[DstReg] = SrcReg; 164 unsigned DstReg = Dst.getReg(); 166 PeepholeMap[DstReg] = SrcReg; 181 unsigned DstReg = Dst.getReg(); 183 PeepholeDoubleRegsMap[DstReg] = 193 unsigned DstReg = Dst.getReg(); 196 if (TargetRegisterInfo::isVirtualRegister(DstReg) && 201 PeepholeMap[DstReg] = SrcReg [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430RegisterInfo.cpp | 143 unsigned DstReg = MI.getOperand(0).getReg(); 145 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) 146 .addReg(DstReg).addImm(-Offset); 148 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg) 149 .addReg(DstReg).addImm(Offset);
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/external/llvm/lib/Target/R600/ |
SIFixSGPRCopies.cpp | 181 unsigned DstReg = Copy.getOperand(0).getReg(); 184 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
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R600ExpandSpecialInstrs.cpp | 125 unsigned DstReg; 128 DstReg = MI.getOperand(Chan).getReg(); 130 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W; 133 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); 154 unsigned DstReg; 157 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y; 159 DstReg = MI.getOperand(Chan-2).getReg(); 162 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); 182 unsigned DstReg = MI.getOperand(0).getReg(); 186 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg) [all...] |
R600OptimizeVectorRegisters.cpp | 190 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 196 DstReg) 210 SrcVec = DstReg;
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/external/mesa3d/src/gallium/drivers/radeon/ |
R600ExpandSpecialInstrs.cpp | 96 unsigned DstReg = MI.getOperand(0).getReg(); 120 DstReg = TRI.getSubReg(DstReg, SubRegIndex); 124 Flags |= (Chan != TRI.getHWRegChan(DstReg) ? MO_FLAG_MASK : 0); 125 unsigned DstBase = TRI.getHWRegIndex(DstReg); 126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); 151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
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/external/chromium_org/third_party/mesa/src/src/mesa/main/ |
atifragshader.h | 56 struct atifragshader_dst_register DstReg[2];
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/external/mesa3d/src/mesa/main/ |
atifragshader.h | 56 struct atifragshader_dst_register DstReg[2];
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
radeon_program.h | 79 struct rc_dst_register DstReg;
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/external/llvm/lib/Target/ARM/ |
MLxExpansionPass.cpp | 275 unsigned DstReg = MI->getOperand(0).getReg(); 301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
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Thumb2ITBlockPass.cpp | 119 unsigned DstReg = MI->getOperand(0).getReg(); 123 if (Uses.count(DstReg) || Defs.count(SrcReg))
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/external/llvm/lib/Target/Mips/ |
MipsOptimizePICCall.cpp | 135 unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64; 136 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg) 138 I->getOperand(0).setReg(DstReg);
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MipsSEInstrInfo.cpp | 480 unsigned DstReg = I->getOperand(0).getReg(); 481 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 482 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); 494 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; 503 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 506 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 509 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); 515 unsigned DstReg = I->getOperand(0).getReg() [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/ |
radeon_program.h | 79 struct rc_dst_register DstReg;
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