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    Searched defs:Opc (Results 1 - 25 of 88) sorted by null

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  /external/llvm/lib/Target/Mips/
MipsAnalyzeImmediate.h 20 unsigned Opc, ImmOpnd;
21 Inst(unsigned Opc, unsigned ImmOpnd);
MipsInstrInfo.cpp 71 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
74 assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
80 Cond.push_back(MachineOperand::CreateImm(Opc));
101 unsigned Opc = Cond[0].getImm();
102 const MCInstrDesc &MCID = get(Opc);
126 // Floating point branches: 1 (opc)
127 // Int BranchZero: 2 (opc, reg)
128 // Int Branch: 3 (opc, reg0, reg1)
Mips16ISelDAGToDAG.cpp 46 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty,
49 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
259 unsigned Opc = InFlag.getOpcode(); (void)Opc;
260 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
261 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
Mips16InstrInfo.cpp 68 unsigned Opc = 0;
72 Opc = Mips::MoveR3216;
75 Opc = Mips::Move32R16;
78 Opc = Mips::Mfhi16, SrcReg = 0;
82 Opc = Mips::Mflo16, SrcReg = 0;
85 assert(Opc && "Cannot copy registers");
87 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
104 unsigned Opc = 0;
106 Opc = Mips::SwRxSpImmX16;
107 assert(Opc && "Register class not handled!")
    [all...]
MipsFastISel.cpp 97 MachineInstrBuilder EmitInst(unsigned Opc) {
98 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
101 MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
102 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
106 MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
108 return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
111 MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg,
113 return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
160 unsigned Opc;
164 Opc = Mips::LW
    [all...]
  /external/llvm/lib/Target/X86/
X86FrameLowering.cpp 108 unsigned Opc = MBBI->getOpcode();
109 switch (Opc) {
155 unsigned Opc;
157 Opc = getLEArOpcode(IsLP64);
159 Opc = isSub
174 Opc = isSub
177 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
189 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
192 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
212 unsigned Opc = PI->getOpcode()
    [all...]
X86RegisterInfo.cpp 480 unsigned Opc = MI.getOpcode();
481 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
506 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
  /external/llvm/lib/Target/ARM/
ARMInstrInfo.cpp 53 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
54 switch (Opc) {
125 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ?
129 TII.get(Opc), TempReg)
131 if (Opc == ARM::LDRcp)
137 Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? ARM::tPICADD
139 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
142 if (Opc == ARM::PICADD)
Thumb1RegisterInfo.cpp 127 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
130 if (Opc != ARM::tADDhirr)
141 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
146 if (Opc == ARM::tADDrSPi) {
180 int Opc = 0;
188 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
201 Opc = ARM::tADDrSPi;
210 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
215 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8
    [all...]
Thumb1FrameLowering.cpp 73 unsigned Opc = Old->getOpcode();
74 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
77 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
  /external/llvm/lib/Target/Hexagon/
HexagonExpandPredSpillCode.cpp 85 int Opc = MI->getOpcode();
86 if (Opc == Hexagon::STriw_pred) {
130 } else if (Opc == Hexagon::LDriw_pred) {
HexagonSplitConst32AndConst64.cpp 87 int Opc = MI->getOpcode();
88 if (Opc == Hexagon::CONST32_set) {
101 else if (Opc == Hexagon::CONST32_set_jt) {
114 else if (Opc == Hexagon::CONST32_Label) {
127 else if (Opc == Hexagon::CONST32_Int_Real) {
138 else if (Opc == Hexagon::CONST64_Int_Real) {
HexagonCFGOptimizer.cpp 61 static bool IsConditionalBranch(int Opc) {
62 return (Opc == Hexagon::JMP_t) || (Opc == Hexagon::JMP_f)
63 || (Opc == Hexagon::JMP_tnew_t) || (Opc == Hexagon::JMP_fnew_t);
67 static bool IsUnconditionalJump(int Opc) {
68 return (Opc == Hexagon::JMP);
114 int Opc = MI->getOpcode();
115 if (IsConditionalBranch(Opc)) {
  /external/llvm/lib/Target/MSP430/
MSP430InstrInfo.cpp 95 unsigned Opc;
97 Opc = MSP430::MOV16rr;
99 Opc = MSP430::MOV8rr;
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
MSP430FrameLowering.cpp 142 unsigned Opc = PI->getOpcode();
143 if (Opc != MSP430::POP16r && !PI->isTerminator())
MSP430ISelDAGToDAG.cpp 366 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
371 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
  /external/llvm/lib/Target/AArch64/
AArch64AdvSIMDScalarPass.cpp 160 static int getTransformOpcode(unsigned Opc) {
161 switch (Opc) {
171 return Opc;
175 int Opc = MI->getOpcode();
176 return Opc != getTransformOpcode(Opc);
AArch64LoadStoreOptimizer.cpp 113 static bool isUnscaledLdst(unsigned Opc) {
114 switch (Opc) {
178 static unsigned getMatchingPairOpcode(unsigned Opc) {
179 switch (Opc) {
215 static unsigned getPreIndexedOpcode(unsigned Opc) {
216 switch (Opc) {
242 static unsigned getPostIndexedOpcode(unsigned Opc) {
243 switch (Opc) {
392 int Opc = FirstMI->getOpcode();
394 bool IsUnscaled = isUnscaledLdst(Opc);
    [all...]
AArch64ConditionalCompares.cpp 580 unsigned Opc = 0;
584 Opc = AArch64::SUBSWri;
588 Opc = AArch64::SUBSXri;
593 const MCInstrDesc &MCID = TII->get(Opc);
612 unsigned Opc = 0;
618 case AArch64::SUBSWri: Opc = AArch64::CCMPWi; break;
619 case AArch64::SUBSWrr: Opc = AArch64::CCMPWr; break;
620 case AArch64::SUBSXri: Opc = AArch64::CCMPXi; break;
621 case AArch64::SUBSXrr: Opc = AArch64::CCMPXr; break;
622 case AArch64::ADDSWri: Opc = AArch64::CCMNWi; break
    [all...]
  /external/llvm/lib/Target/Sparc/
SparcCodeEmitter.cpp 235 unsigned Opc = MI.getOpcode();
236 switch (Opc) {
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
AMDILISelDAGToDAG.cpp 155 unsigned int Opc = N->getOpcode();
159 switch (Opc) {
  /external/llvm/lib/Target/PowerPC/
PPCCTRLoops.cpp 590 unsigned Opc = I->getOpcode();
591 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) {
652 unsigned Opc = MII->getOpcode();
653 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ ||
654 Opc == PPC::BDZ8 || Opc == PPC::BDZ)
  /external/llvm/lib/Target/XCore/
XCoreInstrInfo.cpp 297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
298 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
306 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
307 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
  /external/mesa3d/src/gallium/drivers/radeon/
AMDILISelDAGToDAG.cpp 155 unsigned int Opc = N->getOpcode();
159 switch (Opc) {
  /external/llvm/lib/MC/MCAnalysis/
MCModuleYAML.cpp 74 bool matchOpcode(StringRef Name, unsigned &Opc) {
78 Opc = It->getValue();
267 unsigned Opc;
268 if (!IRI->matchOpcode(Scalar, Opc))
270 Val = Opc;

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