| /external/llvm/lib/Target/XCore/ |
| XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
42 LRSpillSlot = MFI->CreateFixedObject(RC->getSize(), 0, true);
44 LRSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
56 FPSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
67 EHSpillSlot[0] = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true)
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveStackAnalysis.cpp | 59 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
65 S2RCMap.insert(std::make_pair(Slot, RC));
69 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
81 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
82 if (RC)
83 OS << " [" << RC->getName() << "]\n";
|
| AggressiveAntiDepBreaker.h | 44 /// RC - The register class
45 const TargetRegisterClass *RC;
|
| RegisterClassInfo.cpp | 76 /// compute - Compute the preferred allocation order for RC with reserved
79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
80 RCInfo &RCI = RegClass[RC->getID()];
83 unsigned NumRegs = RC->getNumRegs();
96 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
132 // Check if RC is a proper sub-class.
133 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
134 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
141 dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
155 const TargetRegisterClass *RC = nullptr
[all...] |
| TargetRegisterInfo.cpp | 87 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
88 if (!RC || RC->isAllocatable())
89 return RC;
91 const unsigned *SubClass = RC->getSubClassMask();
118 const TargetRegisterClass* RC = *I;
119 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
120 (!BestRC || BestRC->hasSubClass(RC)))
121 BestRC = RC;
[all...] |
| CriticalAntiDepBreaker.cpp | 403 const TargetRegisterClass *RC,
406 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
637 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg]
639 assert((AntiDepReg == 0 || RC != nullptr) &&
641 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
655 RC, ForbidRegs)) {
|
| LocalStackSlotAllocation.cpp | 391 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF);
392 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
|
| StackMaps.cpp | 124 const TargetRegisterClass *RC =
128 Location(Location::Register, RC->getSize(), MOI->getReg(), 0));
|
| VirtRegMap.cpp | 76 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
77 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
78 RC->getAlignment());
105 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
106 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
|
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 36 const CodeGenRegisterClass *RC;
255 const CodeGenRegisterClass *RC = nullptr;
259 RC = &Target.getRegisterClass(OpLeafRec);
261 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
263 RC = OrigDstRC;
268 if (!RC)
274 if (DstRC != RC && !DstRC->hasSubClass(RC))
277 DstRC = RC;
651 OS << "&" << InstNS << Memo.RC->getName() << "RegClass"
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 83 const TargetRegisterClass *RC;
85 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
87 RC = ST.isABI_N64() ?
90 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
101 const TargetRegisterClass *RC;
102 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
103 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC);
109 const TargetRegisterClass *RC = ST.isABI_N64() ?
112 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
113 RC->getAlignment(), false)
[all...] |
| MipsSERegisterInfo.cpp | 169 const TargetRegisterClass *RC =
172 unsigned Reg = RegInfo.createVirtualRegister(RC);
|
| Mips16ISelDAGToDAG.cpp | 77 const TargetRegisterClass *RC =
80 V0 = RegInfo.createVirtualRegister(RC);
81 V1 = RegInfo.createVirtualRegister(RC);
82 V2 = RegInfo.createVirtualRegister(RC);
|
| MipsFastISel.cpp | 86 unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
91 unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
325 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
326 unsigned DestReg = createResultReg(RC);
331 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
332 unsigned DestReg = createResultReg(RC);
346 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
347 unsigned DestReg = createResultReg(RC);
360 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
367 return Materialize32BitInt(Imm, RC);
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIFixSGPRLiveRanges.cpp | 95 const TargetRegisterClass *RC = MRI.getRegClass(Def.getReg());
97 if (!TRI->isSGPRClass(RC))
|
| SIFixSGPRCopies.cpp | 143 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
144 RC = TRI->getSubRegClass(RC, SubReg);
149 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI,
156 return RC;
165 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg);
166 return TRI->getSubRegClass(RC, SubReg);
224 const TargetRegisterClass *RC = inferRegClassFromDef(TRI, MRI, Reg,
226 MRI.constrainRegClass(Reg, RC);
[all...] |
| /external/chromium_org/third_party/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
| SkPdfAppearanceCharacteristicsDictionary_autogen.cpp | 59 SkString SkPdfAppearanceCharacteristicsDictionary::RC(SkPdfNativeDoc* doc) {
60 SkPdfNativeObject* ret = get("RC", "");
68 return get("RC", "") != NULL;
|
| /external/clang/test/Layout/ |
| ms-x86-pack-and-align.cpp | 450 struct RC {
456 RC c;
488 // CHECK-NEXT: 0 | struct RC
496 // CHECK-NEXT: 1 | struct RC c
531 // CHECK-X64-NEXT: 0 | struct RC
539 // CHECK-X64-NEXT: 1 | struct RC c
569 sizeof(RC)+
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 133 const TargetRegisterClass *RC = nullptr;
135 RC = TRI->getAllocatableClass(
139 UseRC = RC;
140 else if (RC) {
142 TRI->getCommonSubClass(UseRC, RC);
220 const TargetRegisterClass *RC =
229 if (RC)
230 VTRC = TRI->getCommonSubClass(RC, VTRC);
232 RC = VTRC;
251 if (RegRC == RC) {
[all...] |
| ResourcePriorityQueue.cpp | 371 const TargetRegisterClass *RC = *I;
372 RegBalance += rawRegPressureDelta(SU, RC->getID());
378 const TargetRegisterClass *RC = *I;
379 if ((RegPressure[RC->getID()] +
380 rawRegPressureDelta(SU, RC->getID()) > 0) &&
381 (RegPressure[RC->getID()] +
382 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()]))
383 RegBalance += rawRegPressureDelta(SU, RC->getID());
491 const TargetRegisterClass *RC = TLI->getRegClassFor(VT)
[all...] |
| ScheduleDAGSDNodes.cpp | 128 const TargetRegisterClass *RC =
130 Cost = RC->getCopyCost();
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86VZeroUpper.cpp | 261 const TargetRegisterClass *RC = &X86::VR256RegClass;
262 for (TargetRegisterClass::iterator i = RC->begin(), e = RC->end();
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 96 const TargetRegisterClass *RC, bool isVector,
248 // Prints the register in MO using class RC using the offset in the
252 const TargetRegisterClass *RC,
258 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
299 const TargetRegisterClass *RC;
302 RC = &AArch64::FPR8RegClass;
305 RC = &AArch64::FPR16RegClass;
308 RC = &AArch64::FPR32RegClass;
311 RC = &AArch64::FPR64RegClass;
314 RC = &AArch64::FPR128RegClass
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 266 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
267 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RC,
320 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
321 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
|
